Upload
cais
View
56
Download
0
Embed Size (px)
DESCRIPTION
- PowerPoint PPT Presentation
Citation preview
ITRS 2000 Update Work In Progress - Do Not Publish!
1
ITRS/ORTC Table UpdateTechnology Node, DRAM Chip Size,
and Logic Chip Size Update, Based on the IRC “Best Case Opportunities”
Proposal, 7/11
ITRS 2000 UpdateRev 1ke, 7/28/00
Rev 1kb: 1) New Definition wording proposal Rev 1; 2) Document 7/11 IRC Technology Node decisions ; 3) Chip sizes updated to new “Best Case” aggressive technology node impact; 4)
Other TWG table line items impact Proposal added (Pin Count, Frequency, Voltage/Power, Defect Density, Cost) 4) ongoing misc.
corrections
Contact: Alan Allan 480-554-8624, [email protected]
ITRS 2000 Update Work In Progress - Do Not Publish!
2
ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00
• Technology Requirements Perspective- Near-Term Years : First Yr. Ref.+ 6 yrs F’cast (ex. 1999 through 2005), annually- Long-Term Years : Following 9 years (ex.: 2008, 2011, and 2014), every 3 years
• Technology Node : - General indices of technology development. - Approximately 70% of the preceding node, 50% of 2 preceding nodes. - Each step represents the creation of significant technology progress- Example: DRAM half pitches (2000 ITRS) of 180, 130, 90, 65, 45 and 33 nm*Year 2000 : Smallest 1/2 pitch among DRAM, ASIC, MPU, etc
• Year of Production: - The volume = *10K units (devices)/month. ASICs manufactured by same
process technology are granted as same devices- Beginning of manufacturing by *a company and another company starts
production within 3 months
• Technology Requirements Color :- : Manufacturable Solutions are NOT known
- : Manufacturable Solutions are known
- : Manufacturable Solutions exist, and they are being optimized
*Year 2000 : Red cannot exist in next 3 years (2000, 2001, 2002)***Year 2000 : Yellow cannot exist in next 1 year (2000)
Red
Yellow
White
** Exception: Solution NOT known, but does not prevent Production manufacturing
ITRS 2000 Update Work In Progress - Do Not Publish!
3
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS(“Best Case” Proposal) (Technology
Node):Technology Node Assumptions (per IRC Proposal 7/11/00): a) DRAM Half-Pitch:WAS: 3-year Node cycle (0.7x/3yrs), except year 2005 shifted off trendIS [2]: 130nm pull-in to 2001 and ~.7x/3yrs(.5x/6yrs) reduction rate,
rounded to nearest 5nm
WAS (nm): 1999/180, 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; 2008/70, 2011/50, 2014/35
IS (nm): 1999/180, 2000/150, 2001/130, 2002/115, 2003/100, 2004/90, 2005/80; 2008/60, 2011/40, 2014/30
Note: .7x/Node(.5x/2 Nodes): 2001/130; 04/90; 07/65; 10/45; 13/33; 16/23
b) MPU/ASIC Half-Pitch:WAS: MPU/ASIC Half-Pitch Same, lagged typically 1-2 years behind DRAMIS [tied to DRAM[2] ]: pull-in one year starting 160nm in 2001, then
~.7x/3yrs(.5x/6yrs) reduction rate, rounded to nearest 5nm
WAS: 1999/230, 2000/210, 2001/180, 2002/160, 2003/145, 2004/130, 2005/115; 2008/80, 2011/55, 2014/40
IS: 1999/230, 2000/190, 2001/160, 2002/145, 2003/130, 2004/115, 2005/100; 2008/70, 2011/50, 2014/35
ITRS 2000 Update Work In Progress - Do Not Publish!
4
Technology Node Assumptions (cont.):
c) MPU/ASIC “In Resist” Gate Length:
WAS: MPU Gate Length 2-year node cycle (.7x/2yrs) to 2001, then 3-year node cycle (.7x/3yrs); ASIC Gate Length typically lagged ~1 node behind MPU
IS: 1. MPU Same as 1999 ITRS, except Variable ranges in 2002, 2011, 2014 replaced by single targets; 2. ASIC same as MPU
WAS (nm): MPU: 1999/140 , 2000/120, 2001/100, 2002/85-90, 2003/80, 2004/70, 2005/65;
2008/45, 2011/30-32, 2014/20-22
ASIC: 1999/180 , 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; 2008/70, 2011/50, 2014/35
IS (nm): MPU/ASIC: 1999/140 , 2000/120, 2001/100, 2002/90, 2003/80, 2004/70, 2005/65; 2008/45, 2011/33, 2014/23
d) NEW: MPU/ASIC “Physical Bottom” Gate Length line item targets added
which are pulled-in 1 year from the Lithography “In Resist” targets.
NEW (nm): 1999/120, 2000/100, 2001/90, 2002/80, 2003/70, 2004/65, 2005/60; 2008/40, 2011/30, 2014/20
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS/NEW(“Best Case” Proposal) (Technology Node):
ITRS 2000 Update Work In Progress - Do Not Publish!
5
Table 1a Product Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE
1999180 nm
2000 2001 2002130 nm
2003 2004 2005100 nm
DRIVER
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005 DRIVER
Lithography- Based Characteristics
DRAM ½ Pitch (nm) 180 165 150 130 120 110 100 D ½
DRAM ½ Pitch (nm) I Spull- in 1 year and .7x/3yrsreduction rate
180 150 130 115 100 90 80 D ½
MPU/ ASIC ½ Pitch (nm) WAS 230 210 180 160 145 130 115 M AND A ½
MPU/ ASIC ½ Pitch (nm) ) I STied to DRAM[2]
230 190 160 145 130 115 100 M AND A ½
MPU Gate Length (nm) †† WAS 140 120 100 85-90 80 70 65 M GATE
ASIC Gate Length (nm) WAS 180 165 150 130 120 110 100 A GATE
MPU/ ASIC Gate Length (I nResist) (nm) †† I S
140 120 100 90 80 70 65 M AND AGATE
Physical Bottom Gate- Length
MPU/ASI C Gate Length (nm)
†† NEW120 100 90 80 70 65 60 COST/PERFORM
ANCE
=> Roadmap portion still under discussion
ITRS 2000 Update Work In Progress - Do Not Publish!
6
Table 1b Product Generations and Chip Size Model—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE ( § NOTE THAT ACTUAL NODE YEARS ARE NOW
2007/65NM; 2010/45NM; 2013/33NM; 2016/23NM) I S
2008[60 NM§]
2011[40 NM§]
2014[30 NM§]
Lithography- Based Characteristics
DRAM ½ Pitch (nm) 70 50 35
DRAM ½ Pitch (nm) I S [2]pull- in and .7x reduction rate
60 40 30
MPU/ ASIC ½ Pitch (nm) WAS 80 55 40
MPU/ASIC ½ Pitch (nm) ) I S Tied to DRAM [2] 70 50 35
MPU Gate Length (nm) †† WAS 45 30-32 20-22
ASIC Gate Length (nm) WAS 70 50 35
MPU/ ASIC Gate Length (I n Resist) (nm) †† I S 45 33 23
Physical Bottom Gate- Length
MPU/ASI C Gate Length (nm) †† NEW 40 30 20
=> Roadmap portion still under discussion
ITRS 2000 Update Work In Progress - Do Not Publish!
7
ITRS Roadmap Acceleration Continues... (Including MPU/ASIC “Physical Gate Length” Proposal)
95 97 99 01 04 07 10
1994
1997
1998
an
d M
PU
/AS
IC G
ate
Le
ng
th M
inim
um
Fe
atu
re S
ize
(n
m) 500
350
250
180
130
100
70
50
35
25 DRAM Half Pitch95 97 99 01 04 07 10
13
13
1999
MPU/ASIC Gate “Physical”
2000Proposal
MPU/ASIC Gate “In Resist” 7/11 IRC Proposal - Best Case Opportunities*
XXX90
XX 65
XX 45
XX 33
XX 23
~.7x per technology node (.5x per 2 nodes)
Year of Production
* Note: MPU ASIC Physical Bottom Gate Length Preliminary 2000 Update TWG table targets are still under discussion.
Tec
hn
olo
gy
No
de
- D
RA
M H
alf-
Pit
ch (
nm
)
Technology Node
Minimum Feature
ITRS 2000 Update Work In Progress - Do Not Publish!
8
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS(“Best Case” Proposal) (cont.- DRAM):
DRAM Assumptions:
a) Cell Area Factor Limits (from FEP TWG):
WAS: 8x/1999 -> 6x/2002 -> 4.4x/2005 -> 3.0x/2011 -> 2.5x/2014
IS: 8x/1999-2004, 6x/2005-2010, 4x/2011-16b) Cell Array Efficiency Limit Trends (from FEP, Nikkei Microdevices):
WAS: Intro: 1999/70% --> 2016/75%
IS: Intro: 1999/70% --> 2016/75%WAS: Production 1999/53% --> 2016/57%
IS: Production 1999/53% --> 2016/58%c) Litho Field Size Maximum Limit (from Litho TWG):
WAS: 4x Magnification, 6-inch Reticle
Intro 1999-2016 25x32 = 800mm2
Production 1999-2016 12.5x32 = 400mm (2 chips/field)
IS: 5x Magnification, 6-inch ReticleIntro 1999-2016 22x26 = 572mm2Production 1999-2016 11x26 = 286mm2 (2
chips/field)d) Bits/Chip Product Generation Growth Rate:
WAS: 1999-2014:2x bits/chip every 2 years
IS: @ Introduction: Through 8Gbit: 2x bits/chip every 2 years;After 8Gbit: 2x bits/chip every 2-3 years (4x/5years)
@ Production: Through 32Gbit: 2x bits/chip every 2 years;After 32Gbit: 2x bits/chip every 2-3 years (4x/5years)
ITRS 2000 Update Work In Progress - Do Not Publish!
9
Summary of Key Assumption Proposed Changes WAS(1999 ITRS) vs. IS IS(“Best Case” Proposal) (cont.- Logic):
MPU Assumptions:
a) High Performance (HP) MPU @Ramp Starting Chip Size:
WAS: 2Mbyte on-chip (6t) SRAM in 1999
(170mm2 Core plus 280mm2 SRAM = 450mm2/1999)
IS: 1Mbyte on-chip (6t) SRAM in 1999 (170mm2 Core plus 140mm2 SRAM =
310mm2/1999)b) Cost Performance (CP) Starting Chip Size (SAME as 1999 ITRS):
MPU @Introduction/340mm2
MPU @Ramp/170mm2
c) SRAM and Logic Transistors/chip Trend (SAME as ITRS) = 2x/2yrs
d) Chip Size Growth Rate Trend
WAS/ IS(7/11): Flat chip sizes through 2001, then 1.2x/4rs
ITRS 2000 Update Work In Progress - Do Not Publish!
10
Table 1a Product Generations and Chip Size Model—[Assumptions, Notes]†† WAS: Range of [MPU Gate-Length] node targets indicates the acknowledgment of the difficulty of
projecting the impact of the return to the 3-year technology node cycle starting in 2001 and theuncertainty of the long term years of the Roadmap timeframe.
†† I S: [No Ranges in cells]. MPU and ASI C Gate- length (I n Resist) node targets refer to mostaggressive requirements, as printed in photoresist (which was by definition also “as etched inpolysilicon”, in the 1999 ITRS). NEW:Trends have been identified, in which the MPU and ASI C “physical bottom” gate lengths may bereduced from the “as- printed” dimension. These “physical bottom” gate- length targets are alsoincluded in the FEP, PI Ds, and Design TWG Tables as needs which drive device and processtechnology requirements.
§ WAS: DRAM Model—Generations 4 bits/ chip every four years with interim 2 bits/ chip generations;InTER-generation chip size growth rate model is 1.2 every four years; InTRA-generation chip sizeshrink model is 0.5 every three years beginning 1999.
§ I S: DRAM Model—Cell Factor (design/process improvement) targets are: 1999- 2004/8x;2005- 2010/6x; 2011- 2016/4x. DRAM product generations are usually increased by 4 bits/ chipevery four years with interim 2 bits/ chip generations, except: 1) at the I ntroduction phase, afterthe 8Gbit interim generation, the introduction rate is 4x/5years (2x/2- 3yrs); and 2) at theProduction phase, after the interim 32Gbit generation, the introduction rate is 4x/5years(2x/2- 3yrs). InTER-generation chip size growth rate varies to maintain 1 die per 572mm2 field atI ntroduction and 2 die per 572mm2 field at Production. The more aggressive “best caseopportunity” technology node trends allow the Production- phase products to remain at 2xbits/chip every 2 years and still fit within the target of two DRAM chips per 572mm2 field size,through the 32Gbit interim generation. The InTRA-generation chip size shrink model is 0.5 everytechnology node in- between cell factor reductions.
Note: Long- Range Forecast Nodes now fall on: 2010/45; 2013/33; 2016/25
Chip Size - Model Assumptions, Notes, Tables
ITRS 2000 Update Work In Progress - Do Not Publish!
11
Table 1a Product Generations and Chip Size Model—[Assumptions,Notes]
† WAS/I S: p is processor, numerals reflect year of introduction, c is cost-performance product.
‡ WAS/I S: p is processor, numerals reflect year at ramp, h is high-performance product.
* WAS/I S: MPU Cost-performance Model—Cost-performance MPU includes small level 1 (L1)on-chip SRAM (32Kbyte/ 1999), but consists primarily of logic transistor functionality; bothSRAM and Logic functionality doubles every two years.
** WAS: MPU High-performance Model—High-performance MPU includes large level 2 (L2) on-chip SRAM (2MByte/ 1999) added to ramp-level cost-performance core functionality shrunk from2-year-prior generation (P99h = 11.9M transistor (Mtransistors) (shrunk P97 core) +98Mtransistors (2048 bytes 8 bits/ byte 6 transistors/ bit) L2 SRAM =110Mtransistors/ 1999); both SRAM and Logic functionality doubles every two years.
** I S: MPU High-performance Model—High-performance MPU includes large level 2 (L2) on-chipSRAM (1MByte/ 1999) added to ramp-level cost-performance core functionality shrunk from 2-year-prior generation (P99h = 11.9M transistor (Mtransistors) (shrunk P97 core) +49Mtransistors (1024 bytes 8 bits/ byte 6 transistors/ bit) L2 SRAM = 61Mtransistors/ 1999);both SRAM and Logic functionality doubles every two years.
*** WAS/I S: MPU Chip Size Model—Both the cost-performance and high-performance MPUsInTER-generation chip size growth rates can be kept flat through 2001, due to the moreaggressive MPU/ASI C half- pitch technology node trend; but beyond 2001, the target growthrate is 1.2 growth every four years. The InTRA-generation chip size shrink model is 0.5 everytwo years through 2001, then 0.5 every three years after 2001.
Chip Size - Model Assumptions, Notes, Tables (cont. - MPU)
ITRS 2000 Update Work In Progress - Do Not Publish!
12
Part 2 -
DRAM TablesRev 1ke, 7/28/00
( § Note that target node years are now proposed to be: 1999/180nm;
2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm; 2013/33nm;
2016/23nm)
ITRS 2000 Update Work In Progress - Do Not Publish!
13
Table 1a Product Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nmDRIVER
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005 DRIVER
DRAM ½ Pitch [f] (nm) WAS 180 165 150 130 120 110 100 D ½
DRAM ½ Pitch [f] (nm) I S 180 150 130 115 100 90 80 D ½Memory (cont.)
Cell area factor [A] WAS
8.0 7.3 6.6 6.0 5.4 4.9 4.4 Market —Cost/ Timing
Cell area factor [A] I S 8.0 8.0 8.0 8.0 8.0 8.0 6.0 Market —Cost/ Timing
Cell area [Ca = Af2] (m2)
WAS
0.26 0.20 0.15 0.10 0.08 0.059 0.044 Market —Cost/ Timing
Cell area [Ca = Af2] (m2) I S 0.26 0.18 0.13 0.10 0.082 0.065 0.039 Market —
Cost/ Timing
Cell array area at production(% of chip size) § WAS
53% — 55% — 53% — 54% Market —Cost/ Timing
Cell array area at production(% of chip size) § I S
53.0% 54.0% 54.8% 55.3% 55.7% 56.1% 56.4% Market —Cost/ Timing
Generation at production §WAS/I S
256M — 512M — 1G — 2G Market —Cost/ Timing
Functions per chip (Gbits) NEW 0.268 0.380 0.537 0.759 1.07 1.52 2.15 Market —Cost/Timing
Chip size at production (mm2) §WAS
132 — 145 — 159 — 174 Market —Cost/ Timing
Chip size at production (mm2) § I S 131 129 127 141 157 175 147 Market —Cost/ Timing
Gbits/ cm2 at production § WAS 0.20 — 0.37 — 0.68 — 1.23 Market —
Cost/ Timing
Gbits/ cm2 at production § I S 0.20 0.29 0.42 0.54 0.68 0.87 1.46 Market —
Cost/ Timing
ITRS 2000 Update Work In Progress - Do Not Publish!
14
Table 1b Product Generations and Chip Size Model—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 nm§]2011
[40 nm§]2014
[30 nm§]
DRAM ½ Pitch [f] (nm) WAS 70 50 35
DRAM ½ Pitch [f] (nm) I S 60 40 30
Memory
Cell area factor [A] WAS 3.5 3.0 2.5
Cell area factor [A] I S 6.0 4.0 4.0
Cell area [Ca = Af2] (m2) WAS 0.017 0.008 0.003
Cell area [Ca = Af2] (m2) I S 0.019 0.0064 0.0032
Cell array area at production(% of chip size) § WAS
52% 56% 57%
Cell array area at production(% of chip size) § I S
57.3% 57.8% 58.2%
Generation at production § WAS [5.7] 16G [45.2G]
Generation at production § I S [6G] 16G [48G]
Functions per chip (Gbits) NEW 6.1 17.2 48.6
Chip size at production (mm2) § WAS 199 229 262
Chip size at production (mm2) § I S 205 191 268
Gbits/cm2 at production § WAS 3.05 7.51 18.5
Gbits/cm2 at production § I S 2.97 8.99 18.1
ITRS 2000 Update Work In Progress - Do Not Publish!
15
Table 1a Product Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nmDRIVER
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005 DRIVER
DRAM ½ Pitch [f] (nm) WAS 180 165 150 130 120 110 100 D ½
DRAM ½ Pitch [f] (nm) I S 180 150 130 115 100 90 80 D ½Memory
Cell area factor [A]WAS
8.0 7.3 6.6 6.0 5.4 4.9 4.4 Market —Cost/ Timing
Cell area factor [A] I S 8.0 8.0 8.0 8.0 8.0 8.0 6.0 Market —Cost/ Timing
Cell area [Ca = Af2] (m2)
WAS
0.26 0.20 0.15 0.10 0.08 0.059 0.044 Market —Cost/ Timing
Cell area [Ca = Af2] (m2) I S 0.259 0.183 0.130 0.103 0.082 0.065 0.039 Market —
Cost/ Timing
Cell array area at introduction(% of chip size) § WAS
70% — 72% — 70% — 72% Market —Cost/ Timing
Cell array area at introduction(% of chip size) § I S
69.5% 70.5% 71.3% 71.8% 72.2% 72.6% 72.9% Market —Cost/ Timing
Generation at introduction § WAS 1G — 2G — 4G — 8G —
Generation at introduction § I S 1G — 2G — 4G — 8G —
Functions per chip (Gbits) WAS 1.07 — 2.15 — 4.29 — 8.59 Market —Moore’s Law
Functions per chip (Gbits) I S 1.07 1.52 2.15 3.04 4.29 6.07 8.59 Market —Cost/Timing
Chip size at introduction (mm2) §WAS
400 — 438 — 480 — 526 Market —Cost/ Timing
Chip size at introduction (mm2) §I S
400 395 390 435 485 542 454 Market —Cost/ Timing
Gbits/ cm2 at introduction § WAS 0.27 — 0.49 — 0.89 — 1.63 Market —
Cost/ Timing
Gbits/ cm2 at introduction § I S 0.27 0.38 0.55 0.70 0.88 1.12 1.89 Market —
Cost/ Timing
ITRS 2000 Update Work In Progress - Do Not Publish!
16
Table 1b Product Generations and Chip Size Model—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008[60 NM§ ]
2011[40 NM§]
2014[30 NM§ ]
DRAM ½ Pitch [f] (nm) WAS 70 50 35
DRAM ½ Pitch [f] (nm) I S 60 40 30
Memory
Cell area factor [A] WAS 3.5 3.0 2.5
Cell area factor [A] I S 6.0 4.0 4.0
Cell area [Ca = Af2] (m2) WAS 0.017 0.008 0.003
Cell area [Ca = Af2] (m2) I S 0.019 0.0064 0.0032
Cell array area at introduction(% of chip size) § WAS
69% 75% 75%
Cell array area at introduction(% of chip size) § I S
73.3% 74.3% 74.7%
Generation at introduction § WAS [22.6G] 64G [181G]
Generation at introduction § I S [20G] [45G] [104G]
Functions per chip (Gbits) WAS 24.3 68.7 194
Functions per chip (Gbits) I S 19.7 45.3 104.2
Chip size at introduction (mm2) § WAS 603 691 792
Chip size at introduction (mm2) § I S 516 392 448
Gbits/cm2 at introduction § WAS 4.03 9.94 24.5
Gbits/cm2 at introduction § I S 3.82 11.56 23.25
ITRS 2000 Update Work In Progress - Do Not Publish!
17
DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal ["I S", 7/11/00]:
Year 1999 2000 2001 2002 2003 2004 2005 2006 Technol ogy Node [ WAS, 1999] 180 130 100
Technol ogy Node [ I S, 7/ 11/ 00] 180 130 90F ( nm) [ r ounded, I S] 180 150 130 115 100 90 80 70
F ( nm) [ act ual ****, I S] 180 151. 361 127. 3 113. 4 101. 0 90. 0 80. 2 71. 4Cel l Ar ea Fact or , I S 8 8 8 8 8 8 6 6Cel l Ar ea ( um2) , I S 0. 259 0. 183 0. 130 0. 103 0. 082 0. 065 0. 039 0. 031DRAM @ Introduction, IS Var i abl e bi t / chi p gr owt h per schedul e bel ow**, i ncl udi ng annual i zi ng i nser t i on, as r equi r ed*Gbi t / Chi p ( var . **) 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07 8. 59 11. 33
DRAM Pr oductCel l effi ci ency 69. 5% 70. 5% 71. 3% 71. 8% 72. 2% 72. 6% 72. 9% 73. 2%
Tot al Cel l Ar ea ( mm2) 278 278 278 312 351 394 331 347Chi p Si ze ( mm2) 400 395 390 435 485 542 454 474
Densi t y ( Gbi t s/ cm2) 0. 27 0. 38 0. 55 0. 70 0. 88 1. 12 1. 89 2. 39DRAM @ Production, IS Const ant bi t per / chi p gr owt h per schedul e bel ow***
Gbi t / Chi p ( const . ***) 0. 27 0. 38 0. 54 0. 76 1. 07 1. 52 2. 15 3. 04DRAM Pr oduct
Cel l effi ci ency 53. 0% 54. 0% 54. 8% 55. 3% 55. 7% 56. 1% 56. 4% 56. 7%Tot al Cel l Ar ea ( mm2) 70 70 70 78 88 98 83 93
Chi p Si ze ( mm2) 131 129 127 141 157 175 147 164Densi t y ( Gbi t s/ cm2) 0. 20 0. 29 0. 42 0. 54 0. 68 0. 87 1. 46 1. 85
Bi t / Chi p Gr owt h/ yr ( var . **) 1. 41421 For DRAM I nt r oduct i on t hr ough 8Gb and Pr oduct i on Thr ough 32Gb ( 4x/ 4year s)Bi t / Chi p Gr owt h/ yr ( var . **) 1. 31951 For DRAM I nt r oduct i on beyond 8Gb and Pr oduct i on beyond 32Gb ( 4x/ 5year s)
Gbi t / Chi p ( annual i ze*) 1. 07 1. 52 2. 15 3. 04 4. 29 6. 07 8. 59 12. 15DRAM Pr oduct 1G 2G 4G 8G
Bi t / Chi p Gr owt h/ yr ( const . ***) 1. 41421 For I nt r oduct i on and Pr oduct i on DRAM up t o and beyond 2Gb ( 4x/ 4year s)
New Li t hogr aphy Fi el d Si ze Li mi t at i on beyond year 2005 i s 572mm2 ( 22mmX26mm) f or 5X r educt i on r et i cl e
**** "act ual " = cal cul at ed st ar t i ng f r om 130nm usi ng 0. 5 (̂ 1/ 6 yr s) Reduct i on r at e = 0. 8909/ year = 0. 7071/ 3yr s = "~0. 7x per year " I RC Defi ni t i on
Not e: = 1999 I TRS, 2000 Updat e Year Header s
= 2001 I TRS Year Header s
1G
256M 512M 1G 2G
2G 4G 8G
ITRS 2000 Update Work In Progress - Do Not Publish!
18
DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal [IS, 7/11/00] (cont):
2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016100 70 50 35
65 45 33 2380 70 65 60 50 45 40 35 33 30 25 23
80. 2 71. 4 63. 6 56. 7 50. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 56 6 6 6 6 6 4 4 4 4 4 4
0. 039 0. 031 0. 024 0. 019 0. 015 0. 012 0. 0064 0. 0051 0. 0041 0. 0032 0. 0026 0. 0020Var i abl e bi t / chi p gr owt h per schedul e bel ow**, i ncl udi ng annual i zi ng i nser t i on, as r equi r ed*
8. 59 11. 33 14. 96 19. 73 26. 04 34. 36 45. 34 59. 82 78. 94 104. 16 137. 44 181. 35
72. 9% 73. 2% 73. 5% 73. 8% 74. 0% 74. 2% 74. 3% 74. 5% 74. 6% 74. 7% 74. 8% 74. 9%331 347 363 381 399 417 291 305 320 335 351 367454 474 494 516 539 563 392 410 429 448 469 4901. 89 2. 39 3. 03 3. 82 4. 83 6. 10 11. 56 14. 60 18. 42 23. 25 29. 33 37. 00
Const ant bi t per / chi p gr owt h per schedul e bel ow***2. 15 3. 04 4. 29 6. 07 8. 59 12. 15 17. 18 24. 30 34. 36 45. 34 59. 82 78. 94
56. 4% 56. 7% 57. 0% 57. 3% 57. 5% 57. 7% 57. 8% 58. 0% 58. 1% 58. 2% 58. 3% 58. 4%83 93 104 117 131 148 110 124 139 146 153 160147 164 183 205 229 256 191 214 239 250 262 2741. 46 1. 85 2. 35 2. 97 3. 75 4. 75 8. 99 11. 36 14. 35 18. 11 22. 86 28. 85
For DRAM I nt r oduct i on t hr ough 8Gb and Pr oduct i on Thr ough 32Gb ( 4x/ 4year s)For DRAM I nt r oduct i on beyond 8Gb and Pr oduct i on beyond 32Gb ( 4x/ 5year s)
8. 59 12. 15 17. 18 24. 30 34. 36 48. 59 68. 72 97. 18 137. 44 194. 37 274. 88 388. 748G 16G 32G 64G 128G 256G
For I nt r oduct i on and Pr oduct i on DRAM up t o and beyond 2Gb ( 4x/ 4year s)
New Li t hogr aphy Fi el d Si ze Li mi t at i on beyond year 2005 i s 572mm2 ( 22mmX26mm) f or 5X r educt i on r et i cl e
**** "act ual " = cal cul at ed st ar t i ng f r om 130nm usi ng 0. 5 (̂ 1/ 6 yr s) Reduct i on r at e = 0. 8909/ year = 0. 7071/ 3yr s = "~0. 7x per year " I RC Defi ni t i on
= 1999 I TRS, 2000 Updat e Year Header s
* 16G 32G 2G 4G
8G
8G
* 128G 32G *
ITRS 2000 Update Work In Progress - Do Not Publish!
19
MPU/ASIC Tables
ITRS 2000 Update Work In Progress - Do Not Publish!
20
MPU/ASIC Tables
- Functions/Chip
- Chip Size
- Density
ITRS 2000 Update Work In Progress - Do Not Publish!
21
Table 1a Product Generations and Chip Size Model—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nmDRIVER
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005 DRIVER
Logic (High-volume Microprocessor) Cost-performance *
Process/ design annualimprovement factor ++
0.90 0.90 0.90 0.91 0.92 0.93 0.93 Market —Cost/ Timing
I S 1.00 1.00 1.00 0.93 0.93 0.93 0.93
Transistor density SRAM at
introduction (Mtransistors/ cm2)
35 50 70 95 128 173 234 Market —Cost/ Timing
Transistor density logic atintroduction (Mtransistors/ cm
2)
6.6 9.4 13 18 24 33 44 Market —Cost/ Timing
Generation at introduction † p99c — p01c — p03c — p05c —
Functions per chip (milliontransistors [Mtransistors])
23.8 — 47.6 — 95.2 — 190 Market —Moore’s Law
I S 23.8 33.7 47.6 67.3 95.2 135 190
Chip size at introduction (mm2) *** 340 — 340 — 372 — 408 Market —Cost/ Timing
I S 340 340 340 356 372 390 408
Cost performance MPU
(Mtransistors/ cm2 at introduction)
(including on-chip SRAM) ***
7 — 14 — 26 — 47 M Gate and
M and A ½
I S 7.0 9.9 14.0 18.9 25.6 34.5 46.7
Generation at production † p97c — p99c — p01c — P03c —
Chip size at production (mm2) *** 170 — 170 — 214 — 235 Market —Cost/ Timing
I S 170 170 170 178 186 195 204
Cost performance MPU
(Mtransistors/ cm2 at production,
including on-chip SRAM) ***
7 — 14 — 22 — 41 M Gate and
M and A ½
I S 7.0 9.9 14.0 18.9 25.6 34.5 46.7
++ The MPU Process/ design improvement factor is an estimate of the additional annual functionalarea reduction required beyond the area reduction contributed by the MPU metal half-pitchreduction. Note that this additional area reduction for transistor density plays a rolegenerally analogous to the "cell area factor" for DRAMs. It has been achieved historicallythrough a combination of many factors, for example: use of additional interconnect levels, self-alignment techniques, and more efficient circuit layout.
ITRS 2000 Update Work In Progress - Do Not Publish!
22
Table 1b Product Generations and Chip Size Model—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008[60 NM§]
2011[40 NM§]
2014[30 NM§]
Logic (High-volume Microprocessor) Cost-performance *
Process/ design improvement factor 0.93 0.93 0.93
I S 0.93 0.93 0.93
Transistor density SRAM at introduction (Mtransistors/ cm2) 577 1,423 3,510
Transistor density logic at introduction (Mtransistors/ cm2) 109 269 664
Generation at introduction † — p11c —
Functions per chip (million transistors (Mtransistors)) 539 1,523 4,308
Chip size at introduction (mm2) *** 468 536 615
I S 468 536 615
Cost-performance MPU Mtransistors/ cm2 at introduction
(including on-chip SRAM) ***
115 284 701
I S 115 284 701
Generation at production † — p09c —
Chip size at production (mm2) *** 269 308 354
I S 234 268 307
Cost performance MPU Mtransistors/ cm2 at production
(including on-chip SRAM) ***
100 247 609
I S 115 284 701
ITRS 2000 Update Work In Progress - Do Not Publish!
23
Table 1a Product Generations and Chip Size Model—Near Term Years (continued)YEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nmDRIVER
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005 DRIVER
Logic (Low-volume Microprocessor) High-performance **
Generation at production ‡ p99h — p01h — p03h — p05h —
Functions per chip(million transistors)
110 — 220 — 441 — 882 Market —Moore’s Law
I S 61 86 122 173 244 345 488
Chip size at production (mm2) *** 450 — 450 — 567 — 622 Market —Cost/ Timing
I S 310 310 310 325 340 356 372
High-performance MPU
Mtransistors/ cm2 at production
(including on-chip SRAM) ***
24 — 49 — 78 — 142 M Gate and
M and A ½
I S 19.7 27.8 39.4 53.2 71.9 97.1 131
ASIC
ASIC usable Mtransistors/ cm2
(auto layout)
20 28 40 54 73 99 133 M Gate and
M and A ½
I S 19.7 27.8 39.4 53.2 71.9 97.1 131
ASIC max chip size at production(mm2) (maximum lithographic fieldsize)
800 800 800 800 800 800 800 LithographicField Size
I S 800 800 800 800 572 572 572
ASIC maximum functions per chipat production (Mtransistors/ chip) (fit in maximum lithographic fieldsize)
160 224 320 432 584 800 1064 Market —Performance/
Timing
I S 157 223 315 426 411 556 751
ITRS 2000 Update Work In Progress - Do Not Publish!
24
Table 1b Product Generations and Chip Size Model—Long Term Years(continued)
YEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008[60 NM§ ]
2011[40 NM§ ]
2014[30 NM§ ]
Logic (Low-volume Microprocessor) High-performance **
Generation at production ‡ — p11h —
Functions per chip(million transistors)
2,494 7,053 19,949
I S 1,381 3,907 11,052
Chip size at production (mm2) *** 713 817 937
I S 427 489 561
High-performance MPU Mtransistors/ cm2 at production
(including on-chip SRAM) ***
350 863 2,130
I S 324 799 1970
ASIC
ASIC usable Mtransistors/ cm2
(auto layout)
328 811 2,000
I S 324 799 1970
ASIC maximum chip size at production (mm2)(maximum lithographic field size) WAS
800 800 800
I S 572 572 572
ASIC maximum functions per chip at ramp (Mtransistors/ chip)(fit in maximum lithographic field size)
2,624 6,488 16,000
I S 1852 4568 11269
Since only the 2011 odd-year product generation data column is available in the Long Term tableformat, interpolated numbers were calculated and included in the 2008 and 2014 node columns. Theextended market-need-based product trends for the product generation two-year-cycle years (1999, 2001,2003, 2005, 2007, 2009, 2011, 2013) are forecast to follow patterns established in Near Term Table 1a.
ITRS 2000 Update Work In Progress - Do Not Publish!
25
MPU/ASIC (M/A) ORTC Chip Size Model Per IRC Technology Node Proposal ["I S", 7/11/00]:
Year 1999 2000 2001 2002 2003 2004 2005 2006 Technol ogy Node [ WAS, 1999] 180 130 100
Technol ogy Node [ I S, 7/ 11/ 00] 180 130 90F ( nm) [ r ounded, 7/ 11] 180 150 130 115 100 90 80 70
F ( nm) [ act ual ****, 7/ 11] 180 151. 361 127. 3 113. 4 101. 0 90. 0 80. 2 71. 4M/ A [ r ounded] :
M/ A H- Pi t ch ( nm) [ WAS, 1999] 230 210 180 160 145 130 115M/ A H- Pi t ch ( nm) [ I S, 7/ 11/ 00] 230 190 160 145 130 115 100 90
MPU Pr i nt ed G- Lengt h ( nm) [ WAS, 1999] 140 120 100 85- 90 80 70 65M/ A Pr i nt ed G- Lengt h ( nm) [ I S, 7/ 11/ 00] 140 120 100 90 80 70 65 60
M/ A Physi cal G- Lengt h ( nm) [ NEW, 7/ 11/ 00] 120 100 90 80 70 65 60 50M/ A [ act ual ****] :
M/ A H- Pi t ch ( nm) , I S 226. 8 190. 7 160. 4 142. 9 127. 3 113. 4 101. 0 90. 0M/ A Pr i nt ed G- Lengt h ( nm) I S 142. 9 120. 1 101. 0 90. 0 80. 2 71. 4 63. 6 56. 7
M/ A Physi cal G- Lengt h ( nm) [ NEW] 120. 1 101. 0 90. 0 80. 2 71. 4 63. 6 56. 7 50. 5
Densi t y Gr owt h Rat e [ ( t / cm2) / yr ] : 2x/ 2yr s 1999- 2001; t hen
[ 2x/ 2yr s/ 1. 2x/ 4yr s] 1. 414 1. 414 1. 414 1. 351 1. 351 1. 351 1. 351 1. 351Densi t y Gr owt h Rat e Cont r i but i on Due t o
Li t ho. Reduct i on 1. 414 1. 414 1. 414 1. 260 1. 260 1. 260 1. 260 1. 260Tr ansi st or Desi gn/ Pr ocess Annual
I mpr ovement Fact or Requi r ed 1. 00 1. 00 1. 00 0. 93 0. 93 0. 93 0. 93 0. 93SRAM Tr . Densi t y ( Mt / cm2) 35 50 70 95 128 173 234 316Logi c Tr . Densi t y ( Mt / cm2) 6. 6 9. 4 13 18 24 33 44 60
Cost-Perf. MPU @ Introduction, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct
SRAM Mt / chi p 1. 5 2. 2 3. 1 4. 3 6. 1 8. 7 12. 3 17. 4Logi c Mt / chi p 22. 3 31. 5 44. 5 63. 0 89. 1 125. 9 178. 1 251. 9Tot al Mt / chi p 23. 8 33. 7 47. 6 67. 3 95. 2 135 190 269
SRAM Ar ea ( mm2) 4. 4 4. 4 4. 4 4. 6 4. 8 5. 0 5. 3 5. 5Logi c Ar ea ( mm2) 335. 6 335. 6 335. 6 351. 3 367. 7 384. 8 402. 7 421. 5
Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 340 340 340 356 372 390 408 427Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 7. 00 9. 90 14. 0 18. 9 25. 6 34. 5 46. 7 63. 1
Cost-Perf. MPU @ Production, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct
SRAM ( Level 1) Mt / chi p 0. 8 1. 1 1. 5 2. 2 3. 1 4. 3 6. 1 8. 7Logi c Mt / chi p 11. 1 15. 7 22. 3 31. 5 44. 5 63. 0 89. 1 125. 9Tot al Mt / chi p 12 17 24 34 48 67 95 135
SRAM Ar ea ( mm2) 2. 2 2. 2 2. 2 2. 3 2. 4 2. 5 2. 6 2. 8Logi c Ar ea ( mm2) 167. 8 167. 8 167. 8 175. 6 183. 8 192. 4 201. 4 210. 8
Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 170 170 170 178 186 195 204 214Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 7. 00 9. 90 14. 0 18. 9 25. 6 34. 5 46. 7 63. 1
High-Perf. MPU @ Production, IS Const ant t r ansi st or s per / chi p gr owt h = 2x/ 2year sMPU Pr oduct
SRAM ( on- chi p Level 2) Mt / chi p 49. 2 69. 5 98. 3 139. 0 196. 6 278. 0 393. 2 556. 1Logi c ( Cor e, i ncl . L1 SRAM) Mt / chi p 11. 9 16. 8 23. 8 33. 7 47. 6 67. 3 95. 2 134. 6
Tot al Mt / chi p 61 86 122 173 244 345 488 691SRAM Ar ea ( mm2) 140. 2 140. 2 140. 2 146. 7 153. 5 160. 7 168. 2 176. 0Logi c Ar ea ( mm2) 170. 0 170. 0 170. 0 177. 9 186. 2 194. 9 204. 0 213. 5
Chi p Si ze ( mm2) [ 1. 2x/ 4yr s] 310 310 310 325 340 356 372 390Ave Densi t y ( i ncl . SRAM) ( Mt / cm2) 19. 7 27. 8 39. 4 53. 2 71. 9 97. 1 131 177
High-Perf. ASIC @ Production, ISTot al Mt / chi p 157 223 315 426 411 556 751 1014
Chi p Si ze ( mm2) [ max. Li t ho Fi el d] 800 800 800 800 572 572 572 572Usabl e Tr ansi st or Densi t y ( Mt / cm2) 19. 7 27. 8 39. 4 53. 2 71. 9 97. 1 131 177
New Li t hogr aphy Fi el d Si ze Li mi t at i on beyond year 2005 i s 572mm2 ( 22mmX26mm) f or 5X r educt i on r et i cl e
**** "act ual " = cal cul at ed st ar t i ng f r om 130nm usi ng 0. 5 (̂ 1/ 6 yr s) Reduct i on r at e = 0. 8909/ year = 0. 7071/ 3yr s = "~0. 7x per year " I RC Defi ni t i on
Not e: = 1999 I TRS, 2000 Updat e Year Header s
= 2001 I TRS Year Header s
p97c p99c
p99h p01h p03h p05h
p01c p03c
p99c p01c p03c p05c
2007 2008 2009 2010 2011 2012 2013 2014 2015 201670 50 35
65 45 33 2365 60 50 45 40 35 33 30 25 23
63. 6 56. 7 50. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5
80 55 4080 70 65 60 50 45 40 35 33 30
45 30- 32 20- 2250 45 40 35 33 30 25 23 20 1845 40 35 33 30 25 23 20 18 16
80. 2 71. 4 63. 6 56. 7 50. 5 45. 0 40. 1 35. 7 31. 8 28. 350. 5 45. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5 20. 0 17. 945. 0 40. 1 35. 7 31. 8 28. 3 25. 3 22. 5 20. 0 17. 9 15. 9
1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351 1. 351
1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260 1. 260
0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93 0. 93427 577 779 1053 1423 1922 2598 3510 4743 640881 109 147 199 269 364 491 664 897 1212
24. 6 34. 8 49. 2 69. 5 98. 3 139. 0 196. 6 278. 0 393. 2 556. 1356. 2 503. 8 712. 4 1007. 6 1424. 9 2015. 1 2849. 8 4030. 2 5699. 6 8060. 4381 539 762 1077 1523 2154 3046 4308 6093 86175. 8 6. 0 6. 3 6. 6 6. 9 7. 2 7. 6 7. 9 8. 3 8. 7
441. 2 461. 8 483. 3 505. 8 529. 4 554. 1 580. 0 607. 0 635. 3 664. 9447 468 490 512 536 561 588 615 644 67485. 2 115. 1 155. 6 210. 2 284. 0 383. 7 518. 5 700. 6 946. 7 1279. 2
12. 3 17. 4 24. 6 34. 8 49. 2 69. 5 98. 3 139. 0 196. 6 278. 0178. 1 251. 9 356. 2 503. 8 712. 4 1007. 6 1424. 9 2015. 1 2849. 8 4030. 2190 269 381 539 762 1077 1523 2154 3046 43082. 9 3. 0 3. 2 3. 3 3. 5 3. 6 3. 8 4. 0 4. 1 4. 3
220. 6 230. 9 241. 6 252. 9 264. 7 277. 1 290. 0 303. 5 317. 7 332. 5223 234 245 256 268 281 294 307 322 33785. 2 115. 1 155. 6 210. 2 284. 0 383. 7 518. 5 700. 6 946. 7 1279. 2
786. 4 1112 1573 2224 3146 4449 6291 8897 12583 17795190. 4 269. 3 380. 8 538. 5 761. 6 1077. 1 1523. 2 2154. 1 3046. 4 4308. 3977 1381 1954 2763 3907 5526 7815 11052 15629 22103
184. 2 192. 8 201. 8 211. 2 221. 1 231. 4 242. 2 253. 5 265. 3 277. 7223. 5 233. 9 244. 8 256. 2 268. 2 280. 7 293. 8 307. 5 321. 8 336. 8408 427 447 467 489 512 536 561 587 614240 324 437 591 799 1079 1458 1970 2662 3597
1370 1852 2502 3381 4568 6172 8340 11269 15227 20575572 572 572 572 572 572 572 572 572 572240 324 437 591 799 1079 1458 1970 2662 3597
**** "act ual " = cal cul at ed st ar t i ng f r om 130nm usi ng 0. 5 (̂ 1/ 6 yr s) Reduct i on r at e = 0. 8909/ year = 0. 7071/ 3yr s = "~0. 7x per year " I RC Defi ni t i on
p05c p07c p09c p11c
p07h p09h
p15c
p11h p13h p15h
p13c
p07c p09c p11c p13c
ITRS 2000 Update Work In Progress - Do Not Publish!
26
MPU/ASIC (M/A) - ORTC Chip Size Model Per IRC Technology Node Proposal [IS, 7/11/00] (cont):
ITRS 2000 Update Work In Progress - Do Not Publish!
27
Part 3 -
Other ORTC Table TWG Line Items
Rev 1ke, 7/28/00
( § Note that actual node years are now proposed to be:
1999/180nm; 2001/130nm; 2004/90nm; 2007/65nm; 2010/45nm;
2013/33nm; 2016/23nm)
ITRS 2000 Update Work In Progress - Do Not Publish!
28
Other ORTC Table TWG Line Items- Table 2a,b Litho Field Size Litho
Wafer Size FEP, FI
- Table 3a,b # of Chip I/O’s Test, Design
# of Package Pins/Balls Test, A&P
- Table 4a,b Chip Pad Pitch A&P
Cost-Per-Pin A&P
Chip Frequency Design
Max # Wire Levels Interconnect
- Table 5a,b Electrical Defects Def. Reduct.
- Table 6a,b P.Supply Volt. PIDs
Max. Power Design, PIDs
- Table 7a,b Affordable Cost Economic (AA actg)
Test Cost Test
ITRS 2000 Update Work In Progress - Do Not Publish!
29
Table 2a Chip-Size, Lithographic-Field and Wafer-Size Trends—Near Term Years(Note: 1999 Lithographic field sizes represent current capability)
YEAR
TECHNOLOGY NODE
1999180 nm
2000 2001 2002130 nm
2003 2004 2005100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005
Lithography Field Size
Maximum lithographic field size — area (mm2) 800 800 800 800 800 800 800
I S 800 800 800 800 572 572 572
Maximum lithographic field size — length (mm) 32 32 32 32 32 32 32
I S 32 32 32 32 22 22 22
Maximum lithographic field size — width (mm) 25 25 25 25 25 25 25
I S 25 25 25 25 26 26 26
Minimum lithographic field size — area (mm2) 484 506 529 552 576 600 625
I S 484 506 529 552 572 572 572
Minimum lithographic field size — length (mm) 22 22.5 23 23.5 24 24.5 25
I S 22 22.5 23 23.5 22 22 22
Minimum lithographic field size — width (mm) 22 22.5 23 23.5 24 24.5 25
I S 22 22.5 23 23.5 26 26 26
Maximum Substrate Diameter (mm) — High-volume Production (>20K wafer starts per month)
Bulk or epitaxial or SOI wafer 200 200 300 300 300 300 300
I S 200 200 300 300 300 300 300
ITRS 2000 Update Work In Progress - Do Not Publish!
30
Table 2b Chip-Size, Lithographic-Field and Wafer Size Trends—Long Term YearsYEAR
TECHNOLOGY NODE2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 NM§]2011
[40 NM§]2014
[30 NM§]
Lithography Field Size
Maximum lithographic field size—area (mm2) 800 800 800
I S 572 572 572
Maximum lithographic field size—length (mm) 32 32 32
I S 22 22 22
Maximum lithographic field size—width (mm) 25 25 25
I S 26 26 26
Minimum lithographic field size—area (mm2) 625 625 625
I S 572 572 572
Minimum lithographic field size—length (mm) 25 25 25
I S 22 22 22
Minimum lithographic field size—width (mm) 25 25 25
I S 26 26 26
Maximum Substrate Diameter (mm)—High-volume Production (>20K wafer starts per month)
Bulk or epitaxial or SOI wafer 300 300 450
I S 300 450 450
ITRS 2000 Update Work In Progress - Do Not Publish!
31
Table 3a Performance of Packaged Chips: Number of Pads and Pins—Near Term Years(I S unchanged as of 7/ 26/ 00)
YEAR
TECHNOLOGY NODE
1999180 nm
2000 2001 2002130 nm
2003 2004 2005100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90 nm2005
Number of Chip I/Os (Number of Total Chip Pads) — Maximum
Total pads—MPU 2,304 2,560 3,042 3,042 3,042 3,042 3,042
Signal I / O—MPU (1/ 3 of total pads) 768 1,024 1,024 1,024 1,024 1,024 1,024
Power and ground pads—MPU (2/ 3 of total pads) 1,536 1,536 2,018 2,018 2,018 2,018 2,018
Total pads—ASIC high-performance 1,400 1,800 2,200 2,600 3,000 3,400 3,800
Signal I / O pads—ASIC high-performance(½ of total pads)
700 900 1,100 1,300 1,500 1,700 1,900
Power and ground pads—ASIC high-performance (½of total pads)
700 900 1,100 1,300 1,500 1,700 1,900
Chip-to-package pads (Peripheral) 368 397 429 464 501 541 584
Number of Total Package Pins/Balls—Maximum
Microprocessor/ controller, cost-performance 740 821 912 1,012 1,123 1,247 1,384
ASIC (high-performance) 1,600 1,792 2,007 2,248 2,518 2,820 3,158
ITRS 2000 Update Work In Progress - Do Not Publish!
32
Table 3b Performance of Packaged Chips: Number of Pads and Pins—Long Term Years(I S unchanged as of 7/ 26/ 00)
YEAR
TECHNOLOGY NODE
200870 nm
201150 nm
201435 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 nm§]2011
[40 nm§]2014
[30 nm§]
Number of Chip I/Os (Number of Total Chip Pads)—Maximum
Total pads—MPU 3,840 4,224 4,416
Signal I / O pads—MPU (1/ 3 of total pads) 1,280 1,408 1,472
Power and ground pads—MPU (2/ 3 of total pads) 2,560 2,816 2,944
Total pads—ASIC high-performance 4,600 5,400 6,000
Signal I / O pads—ASIC high-performance(½ of total pads)
2,300 2,700 3,000
Power and ground pads—ASIC high-performance (½ oftotal pads)
2,300 2,700 3,000
Chip-to-package pads (Peripheral) 736 927 1,167
Number of Total Package Pins/Balls—Maximum
Microprocessor/ controller, cost-performance 1,893 2,589 3,541
ASIC (high-performance) 4,437 6,234 8,758
ITRS 2000 Update Work In Progress - Do Not Publish!
33
Table 4a Performance and Package Chips: Pads, Cost, and Frequency—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005
Chip Pad Pitch (micron)
Pad pitch—ball bond 50 48 47 45 43 42 40
I S 50 50 45 35 30 25 20
Pad pitch—wedge bond 45 43 42 40 39 38 35
I S 45 45 40 35 30 25 20
Pad pitch—area array (cost- performance, high- performance) 200 200 200 200 182 165 150
I S (unchanged as of 7/26/00)
Pad Pitch—area array (handheld, low- cost, harsh) NEW 180 165 150 130 120 110 100
Cost-Per-Pin
Package cost (cents/ pin) (cost-performance)—maximum 1.90 1.81 1.71 1.63 1.55 1.47 1.40
I S (unchanged as of 7/26/00)
Package cost (cents/ pin) (cost-performance)—minimum 0.90 0.86 0.81 0.77 0.73 0.70 0.66
I S (unchanged as of 7/26/00)
Package cost (cents/ pin) (Memory)—maximum 1.90 1.71 1.54 1.39 1.25 1.12 1.01
I S (unchanged as of 7/26/00)
Package cost (cents/ pin) (Memory)—minimum 0.40 0.38 0.36 0.34 0.33 0.31 0.29
I S (unchanged as of 7/26/00)
ITRS 2000 Update Work In Progress - Do Not Publish!
34
Table 4b Performance and Package Chips: Pads, Cost, and Frequency—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 NM§]2011
[40 NM§]2014
[30 NM§]
Chip Pad Pitch (micron)
Pad pitch—ball bond 40 40 40
I S 20 20 20
Pad Pitch—wedge bond 35 35 35
I S 20 20 20
Pad Pitch—area array (cost- performance, high- performance) 150 150 150
I S (unchanged as of 7/26/00)
Pad Pitch—area array (handheld, low- cost, harsh) NEW 70 50 35
Cost-Per-Pin
Package cost (cents/ pin) (cost-performance)—maximum 1.20 1.03 0.88
I S (unchanged as of 7/26/00)
Package cost (cents/ pin) (cost-performance)—minimum 0.57 0.49 0.42
I S (unchanged as of 7/26/00)
Package cost (cents/ pin) (memory)—maximum 0.74 0.54 0.39
I S (unchanged as of 7/26/00)
Package cost (cents/ pin) (memory)—minimum 0.25 0.22 0.19
I S (unchanged as of 7/26/00)
ITRS 2000 Update Work In Progress - Do Not Publish!
35
Table 4a Performance and Package Chips: Pads, Cost, and Frequency—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005
Chip Frequency (MHz)
On-chip local clock, (high-performance ) 1,250 1,486 1,767 2,100 2,490 2,952 3,500
I S 1620 2,100 2,490 2,952 3,500 4,150
On-chip, across-chip clock (high-performance) 1,200 1,321 1,454 1,600 1,724 1,857 2,000
I S 1,386 1,600 1,724 1,857 2,000 2,155
On-chip, across-chip clock, high-performance ASIC 500 559 626 700 761 828 900
I S 592 700 761 828 900 980
On-chip, across-chip clock (cost-performance) 600 660 727 800 890 989 1,100
I S 693 800 890 989 1,100 1,225
Chip-to-board (off-chip) speed(high-performance, reduced-width, multiplexed bus)
1,200 1,321 1,454 1,600 1,724 1,857 2,000
I S 1386 1,600 1,724 1,857 2,000 2,155
Chip-to-board (off-chip) speed(high-performance, for peripheral buses)
480 589 722 885 932 982 1,035
I S 652 885 932 982 1,035 1,090
Maximum number wiring levels—maximum 7 7 7 8 8 8 9
Maximum number wiring levels—minimum 6 6 7 7 8 8 8
ITRS 2000 Update Work In Progress - Do Not Publish!
36
Table 4b Performance and Package Chips: Pads, Cost, and Frequency—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 NM§]2011
[40 NM§]2014
[30 NM§ ]
Chip Frequency (MHz)
On-chip local clock, (high-performance ) 6,000 10,000 13,500
I S 7,115 11,050 14,920
On-chip, across-chip clock (high-performance) 2,500 3,000 3,600
I S 2,655 3,190 3,825
On-chip, across-chip clock (high-performance ASIC) 1,200 1,500 1,800
I S 1,295 1,595 1,913
On-chip, across-chip clock (cost-performance) 1,400 1,800 2,200
I S 1,522 1,925 2,350
Chip-to-board (off-chip) speed(high-performance, reduced-width, multiplexed bus)
2,500 3,000 3,600
I S 2,655 3,190 3,825
Chip-to-board (off-chip) speed (high-performance, for peripheral buses) 1,285 1,540 1,800
I S 1,365 1,620 1,895
Maximum number wiring levels—maximum 9 10 10
Maximum number wiring levels—minimum 9 9 10
ITRS 2000 Update Work In Progress - Do Not Publish!
37
Table 5a Electrical Defects—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005
Defect Reduction
DRAM at production electrical D0
chip size at 85% yield (d/ m2) §
1,249 1,193 1,140 1,089 1,040 994 950
I S 1,259 1,282 1,302 1,170 1,050 942 1126
MPU at ramp electrical D0
chip size at 75% yield (d/ m2) ***
1,742 1,742 1,742 1,552 1,383 1,321 1,262
I S 1,742 1,742 1,742 1,664 1,590 1,519 1,452
ASIC first year electrical D0 at 65% yield (d/ m2) 562 562 562 562 562 562 562
I S 562 562 562 562 787 787 787
Minimum, mask count—maximum 24 24 24 24 25 25 26
I S 24 24 24 25 25 26 26
Minimum, mask count—minimum 22 23 23 24 24 24 24
I S 22 23 24 24 24 24 24
ITRS 2000 Update Work In Progress - Do Not Publish!
38
Table 5b Electrical Defects—Long Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 NM§]2011
[40 NM§]2014
[30 NM§]
Defect Reduction
DRAM at production electrical D0
chip size at 85% yield (d/ m2) §
828 723 630
I S 807 865 660
MPU at ramp electrical D0
chip size at 75% yield (d/ m2) ***
1,101 960 837
I S 1,266 1,104 963
ASIC first year electrical D0 at 65% yield (d/ m2) 562 562 562
I S 787 787 787
Minimum, mask count—maximum 28 28 30
I S 28 28 30
Minimum, mask count—minimum 26 28 29
I S 26 28 29
D0 —defect density
ITRS 2000 Update Work In Progress - Do Not Publish!
39
Table 6a Power Supply and Power Dissipation—Near Term YearsYEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005
Power Supply Voltage (V)
Minimum logic Vdd (V)—maximum(for maximum performance)
1.8 1.8 1.5 1.5 1.5 1.2 1.2
I S 1.8 1.8 1.5 1.5 1.2 1.2 1.1
Minimum logic Vdd (V)—minimum(for lowest power))
1.5 1.5 1.2 1.2 1.2 0.9 0.9
I S 1.5 1.5 1.2 1.2 0.9 0.9 0.8
Maximum Power
High-performance with heatsink (W) 90 100 115 130 140 150 160
I S 90 108 130 140 150 160 170
Battery (W)—(hand-held) 1.4 1.6 1.7 2.0 2.1 2.3 2.4
I S 1.4 1.7 2.0 2.1 2.3 2.4 2.6
ITRS 2000 Update Work In Progress - Do Not Publish!
40
Table 6b Power Supply and Power Dissipation—Long Term YearsYEAR
TECHNOLOGY NODE
200870 nm
201150 nm
201435 nm
2008[60 NM§]
2011[40 NM§]
2014[30 NM§]
Power Supply Voltage (V)
Minimum logic Vdd (V)—maximum(for maximum performance)
0.9 0.6 0.60
I S 0.9 0.6 0.60
Minimum logic Vdd (V)—minimum (for lowest power)) 0.6 0.5 0.30
I S 0.6 0.5 0.30
Maximum Power
High-performance with heatsink (W) 170 174 183
I S 171 177 186
Battery (W)—(hand-held) 2.0 2.2 2.4
I S 2.1 2.3 2.5
ITRS 2000 Update Work In Progress - Do Not Publish!
41
Table 7a Cost—Near Term Years (I S unchanged as of 7/26/00)
YEAR OF PRODUCTION
TECHNOLOGY NODE WAS1999
180 nm2000 2001 2002
130 nm2003 2004 2005
100 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S1999
180 nm2000 2001
130 nm2002 2003 2004
90nm2005
Affordable Cost per Function ++
DRAM cost/ bit at (packaged microcents)at samples/ introduction
42 — 21 — 11 — 5.3
DRAM cost/ bit at (packaged microcents) at production § 15 — 7.6 — 3.8 — 1.9
Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at introduction ***
1,735 — 868 — 434 — 217
Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at ramp ***
1,050 — 525 — 262 — 131
High-performance MPU (microcents/ transistor) (including on-chip SRAM) at ramp ***
245 — 123 — 61 — 31
Cost-Per-Pin (see Table 4) — — — — — — —
Test
Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—maximum
8 7 7 6 6 5 5
Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—minimum
4 3 3 3 3 2 2
Volume tester cost/ pin ($K/ pin) (cost-performance MPU) 8 8 7 7 6 6 5
ITRS 2000 Update Work In Progress - Do Not Publish!
42
Table 7b Cost—Long Term Years (I S unchanged as of 7/26/00)
YEAR OF PRODUCTION
TECHNOLOGY NODE WAS2008
70 nm2011
50 nm2014
35 nm
YEAR OF PRODUCTION
TECHNOLOGY NODE I S2008
[60 NM§]2011
[40 NM§ ]2014
[30 NM§]
Affordable Cost per Function ++
DRAM cost/ bit (packaged microcents) at samples/ introduction — 0.66 —
DRAM cost/ bit (packaged microcents) at production § — 0.24 —
Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at introduction ***
— 27 —
Cost-performance MPU (microcents/ transistor)(including on-chip SRAM) at ramp ***
— 16 —
High-performance MPU (microcents/ transistor)(including on-chip SRAM) at ramp ***
— 3.8 —
Cost-Per-Pin (see Table 4) — — —
Test
Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—maximum
5 5 5
Volume tester cost per high-frequency signal pin ($K/ pin)(high-performance ASIC)—minimum
N/A N/A N/A
Volume tester cost/ pin ($K/ pin) (cost-performance MPU) 4 2 2
++ Affordable packaged unit cost per function based upon Average Selling Prices (ASPs) available from various analystreports less Gross Profit Margins (GPMs); 35% GPM used for commodity DRAMs and 60% GPM used for MPUs;0.5/ two years inTER-generation reduction rate model used; .55/ year inTRA-generation reduction rate model used;DRAM unit volume life-cycle peak occurs when inTRA-generation cost per function is crossed by next generation, typically7–8 years after introduction; MPU unit volume life-cycle peak occurs typically after four years, when the next generationprocessor enters its ramp phase (typically two years after introduction).