ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 1

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Nano-Electro-Mechanical SwitchesNano-Electro-Mechanical Switches

David Elata

On sabbatical leave from Faculty of Mechanical Engineering

Technion - Israel Institute of Technology

Visiting at Stanford UniversityProfessor Roger T. Howe

David Elata

On sabbatical leave from Faculty of Mechanical Engineering

Technion - Israel Institute of Technology

Visiting at Stanford UniversityProfessor Roger T. Howe #

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 2

International Technology Roadmap for Semiconductor

Evaluation of Emerging Research Devices

for "Beyond CMOS" information processing.

International Technology Roadmap for Semiconductor

Evaluation of Emerging Research Devices

for "Beyond CMOS" information processing.

Motivation for critique● Is any device ready for accelerated

engineering development?● Could any be ready for manufacturing

within the next 5 - 10 years?

Two types of devices considered:NEM relay and NEM-FET

Two types of devices considered:NEM relay and NEM-FET

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 3

Intended applicationIntended application

Low-cycle switch power management and

reconfigurable circuits

Intermediate-cycle switchstatic and non-volatile memory

High-cycle switchlogic

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 4

Intended applicationIntended application

Low-cycle switch (power management and reconfigurable circuits)

Switch may be big Preferable zero-power latching High current capability

Technology proven (for RF-MEMS)

Reported [1]: over 1x109 cycles of cold switching~1.5 V actuation, ~50s switching time, 2 W peak power

[1] Intel paper: Ma et al. "Metal contact reliability of RF MEMS switches", SPIE 6463, 646305, 2007.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 5

Intended application (cont'd) Intended application (cont'd)

Intermediate-cycle switch (static and non-volatile memory)

Switch must be small

Many attributes similar to high-cycle switch

High-cycle switch (logic)

Switch must be small (~10nm gap & beam width), low voltage (power management), fast.

Hot switching essential.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 6

NEM relayNEM relay

Obvious Advantages Zero off-state current

Zero sub-threshold swing (naturally digital)

Apparent limitations Switching speed

Theoretical prediction 1~10ns due to mechanical motion [2,3]

[2] K. Akarvardar et al. "Design Considerations for Complementary Nanoelectromechanical Logic Gates", IEDM 2007, 299-303, 2008.

[3] K. Akarvardar et al. "Energy-Reversible Complementary NEM Logic Gates", 66th DRC, 2008.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 7

NEM relayNEM relayTechnological challengesStructural: ● Structures must be compensated for residual and thermal stress

(average and gradient) - no cantilevers or membranes, symmetric

structures preferable. ● Deformable structures must be made from amorphous or single

crystalline (avoid grain-size effects [4]).

Dynamic motion: The unwarranted impact bouncing and release vibrations may be

alleviated by using the energy-reversible operation scheme [3].

Fabrication of laterally actuated devices facilitates symmetric design which enable energy-reversible operation.

[4] S. Givli et al., Int. J. Solids and Struct., 40, 6703-6722, 2003.

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[5] W. W. Jang et al. "Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap", App. Phys. Lett., 92, 103110, 2008.

NEM relay Technological challenges (cont'd)NEM relay Technological challenges (cont'd)

Operation voltage: All demonstrated nano-switches to date (NEM cantilever beam,

CNT, nanowire) required voltages higher than CMOS (3~10V).

The energy-reversible scheme has the potential for lower operation voltage, but is yet to be demonstrated.

Contact conduction: Fast operation requires low contact resistance but too little

resistance leads to failure [5] (Three-terminal device currently characterized):

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 9

NEM relay Technological challenges (cont'd)NEM relay Technological challenges (cont'd)

Contact conduction (cont'd): Conduction at the nano-scale must be better understood to improve

design. In macroscopic relays, where free particles have no effect, the dynamic electrode 'scratches' the static electrode. Abrasive contact in NEMS is not an option.

In test devices, switches are loaded through pads that have huge parasitic capacitance, therefore switches drain uncontrolled current upon contact. In actual devices this capacitance will be lower.

Packaging: RF ohmic switches that were tested in air (even with N2 purge),

failed due to polymerization of organic molecules on the contacting electrodes [1]. This failure mechanism turns ohmic switches into capacitive switches.

Hermetic packaging of test devices seems to be crucial.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 10

NEM relay Technological challenges (cont'd)NEM relay Technological challenges (cont'd)

Surface interaction: Casimir and van der Waals surface interaction forces must be

better modeled, and characterized with test structures 2<g<15nm. (calibrate the effects of finite conductivity and surface roughness).

Surface interaction forces may be used to increase contact force, and latch the switch in contact (turning switch into non-volatile memory).

[6] U. Mohideen et al. "Precision Measurement of the Casimir Force from 0.1 to 0.9 um", Phys. Lett. Rev., 81, 4549 - 4552, 1998.

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NEM relay Technological challenges (cont'd)NEM relay Technological challenges (cont'd)

Materials: ● Coveted: high stiffness, high strength, low density, low resistance,

chemical and mechanical stability.

Aligned CNT structural layers micromachined by masking/plasma etching [7].

[7] Y. Hayamizu et al. "Integrated three-dimensional microelectromechanical devices from processable carbon nanotube wafers", Nature Nanotechnology, 3, 289-294, 2008.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 12

NEM-FETNEM-FETObvious Advantages Dynamic threshold voltage

low sub-threshold leakage with high on-state current

Low sub-threshold swing (2mV/decade).

Conduction through channel in semiconductor - no ohmic contact required.

Apparent limitations Switching speed.

Driving voltage: mV range + fast switching, while retaining high Con/Coff. Is it possible at the nano-scale?

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 13

NEM-FETNEM-FETTechnological challenges

Nano switch + capacitive RF-MEMS

Dielectric charging!40nm gate oxide,12V pull-in [8] 3 MV/cm - Frenkel-Pool leakage

Fixed (injected) charge in dielectric isolation layer can be used to achieve non-volatile memory.

Can dielectric charging be controlled?

Capacitive switches are adversely affected not only by the net (average) fixed charge but also by its spatial distribution (variance) [9].

Possible remedy: Raytheon Schottky switch with recombination of injected charge [10].

[8] N. Abele et al., "Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor", IEDM 2005, 479-481, 2005.

[9] X. Rottenberg et al. "Analytical model of the DC actuation of electrostatic MEMS devices with distributed dielectric charging and nonplanar electrodes", JMEMS, 16, 1243-1253, 2007.

[10] B. Pillans et al. "Schottky barrier contact-based RF MEMS switch", MEMS 2007, 167-170, 2007.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 14

NEM-FET Technological challenges (cont'd)NEM-FET Technological challenges (cont'd)

Thermal stability: Thermal dependence of dielectric charging.

Charging in logic NEM-FET, discharging in NEM-FET non-volatile memory.

Packaging: Hermetic sealing important as in RF-MEMS

Beyond CMOS - more than Moore: NEM-FET nano resonator [11]

Resonant Suspended Gate MOSFET

high Q

[11] C. Durand et al. "In-Plane Silicon-On-Nothing Nanometer-Scale Resonant Suspended Gate MOSFET for In-IC Integration Perspectives", Electron Device Letters, 29, 494-496, 2008.

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 15

● Is any device ready for accelerated engineering development?

● Could any be ready for manufacturing within the next 5 - 10 years?

Motivation for critiqueMotivation for critique

ITRS ERD WG 7/12 San FranciscoITRS ERD WG 7/12 San FranciscoDavid Elata, TechnionDavid Elata, Technion 16

ObservationObservation

Out-of-plane nano switch 2008, KAIST

Samsung Electronics

Lateral E-R nano switch2008, Stanford

SEMATECH

Suspended-Gate MOSFET2008, EPFL + IEMN

CEA-LETI +STMicroelecronics

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SummarySummary● Engineering development is already occurring, often

in form of academia-industry collaboration.● Accelerated engineering development requires

tackling the technological challenges. Finding design solutions, in parallel to identification of failure mechanisms in test devices.

● Could any be ready for manufacturing within the next 5 - 10 years?● It took 10 years to develop the TI-DLP. Patent submitted 1987

(after 10 years of work on MEMS mirrors), first projectors sold1996). Most effort invested on fabrication solutions (materials and processes) to overcome failure modes.

● The maturing MEMS technology provides an excellent starting point for down-scaling MEMS to nanometric dimensions.

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Technion Haifa

Thank you for your attention