ITRS 2008

System Drivers TEXT

UPDATED

DesignTEXT

TEXT ADDED

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TEXT UPDATED

TEXT

TEXT

TEXT

TEXT

TEXT

Test and Test EquipmentTEXT

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TEXT

2008 FOCUS ITWG TABLES:System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process Integration, Devices, & Structures (PIDS)

Link to file for Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Processes (FEP), Lithography, Interconnect, Factory Integration, and Assembly & Packaging

Link to file for Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulation

Link to the 2008 Update Overview

Link to the 2007 ITRS chapters

Table SYSD1

Table SYSD2

Table SYSD3

Table SYSD4

Table DESN1

Table DESN X

Table DESN2

Table DESN3

Table DESN4

Table DESN5

Table DESN6

Table DESN7

Table DESN8

Table DESN9

Table DESN10

Table DESN11

Table DESN12

Table TST1

Table TST2

Table TST3

Table TST4

Table TST5

Table TST6

Table TST7

Table TST8

Table TST9

Table TST10

Table TST11

ORTCINDEX

2007 ITRS Chapters

http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_B.xls

http://www.itrs.net/Links/2008ITRS/Update/2008Tables_CROSSCUT.xls

http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf

http://www.itrs.net/Links/2007ITRS/Home2007.htm

TEXT

RF and AMS for WirelessUPDATED

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Process Integration, Devices, and Structures (PIDS)TEXT

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TEXT

TO ACCESS THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE

Emerging Research DevicesTEXT Please refer to the ERD summary in the 2008 Update Overview

Emerging Research MaterialsTEXT Please refer to the ERM summary in the 2008 Update Overview

Front End ProcessesTEXT Table FEP1

UPDATED Table FEP2

UPDATED Table FEP3

UPDATED Table FEP4a

UPDATED Table FEP4b

UPDATED Table FEP5

UPDATED Table FEP6

UPDATED Table FEP7

UPDATED Table FEP8

Table TST12

Table TST13

Table TST14

Table TST15

Table RFAMS1

Table RFAMS2

Table RFAMS3

Table RFAMS4

Table RFAMS5

Table RFAMS6

Table RFAMS7

Table RFAMS8

Table PIDS1

Table PIDS2

Table PIDS3a and b

Table PIDS3c and d

Table PIDS4

Table PIDS5

Table PIDS6

Table PIDS7

Table FEP9

LithographyTEXT Table LITH1

TEXT Table LITH2

UPDATED Table LITH3

UPDATED Table LITH4AB

Table LITH4C

UPDATED Table LITH5AB

UPDATED Table LITH5CD

UPDATED Table LITH5EF

Table LITH6

InterconnectTEXT Table INTC1

UPDATED Table INTC2

UPDATED Table INTC3

Table INTC4

TEXT Table INTC5

UPDATED Table INTC6

Table INTC7

Factory IntegrationTEXT Table FAC1

TEXT Table FAC2

Table FAC3

UPDATED Table FAC4

Table FAC5

UPDATED Table FAC6

Table FAC7

TEXT Table FAC8

TEXT Table FAC9

Assembly and PackagingTEXT Table AP1

Table AP2

UPDATED Table AP3

UPDATED Table AP4

ADD Table AP4B

UPDATED Table AP5A

UPDATED Table AP5B

UPDATED Table AP5C

Table AP6

Table AP7

TEXT Table AP8

UPDATED Table AP9

TEXT UPDATED Table AP10

UPDATED Table AP11

Table AP12a and b

TEXT Table AP12c

TEXT Table AP13

TEXT Table AP14



TEXT Table AP17

TEXT Table AP18


Table AP20

UPDATED Table AP21


CROSSCUT WORKING GROUP TABLES

Environment, Safety, and HealthTEXT Table ESH1

UPDATED Table ESH2a

UPDATED Table ESH2b

Table ESH3

Table ESH4a

Table ESH4b

UPDATED Table ESH5

Table ESH6

Yield EnhancementTEXT Table YE1

TEXT Table YE2

UPDATED Table YE3

UPDATED Table YE4

UPDATED Table YE5

UPDATED Table YE6

UPDATED Table YE7

UPDATED Table YE8

UPDATED Table YE9

MetrologyTEXT Table MET1

Table MET2

Table MET3

Table MET4a and b

Table MET4c and d

UPDATED Table MET5a

Table MET5b

Table MET6

Modeling and SimulationTEXT UPDATED Table MS1

UPDATED Table MS2a

UPDATED Table MS2b

UPDATED Table MS3

Major Product Market Segments and Impact on System DriversSOC Consumer Driver Design Productivity TrendsProjected Mixed-Signal Figures of Merit for Four Circuit TypesEmbedded Memory Requirements

Overall Design Technology ChallengesDescription of ImprovementSystem-Level Design RequirementsCorrespondence Between System-Level Design Requirements and SolutionsLogical/Circuit/Physical Design Technology RequirementsCorrespondence Between Logical/Circuit/Physical Requirements and SolutionsDesign Verification RequirementsCorrespondence Between Design Verification Requirements and SolutionsDesign for Test Technology RequirementsDesign for Manufacturability Technology RequirementsCorrespondence Between Design for Manufacturability Requirements and SolutionsNear-term Breakthroughs in Design Technology for AMSDesign Technology Improvements and Impact on Designer Productivity

Test and Test EquipmentSummary of Key Test Drivers, Challenges, and OpportunitiesMulti-site Test for Product SegmentsSystem on Chip Test RequirementsLogic Test RequirementsVector MultipliersMemory Test RequirementsMixed-signal Test RequirementsRF Test RequirementsBurn-in RequirementsTest Handler and Prober Difficult ChallengesProber Requirements

2008 FOCUS ITWG TABLES:System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process Integration, Devices, & Structures

Link to file for Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Processes (FEP), Lithography, Interconnect, Factory Integration, and Assembly & Packaging

Link to file for Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulation

Link to the 2008 Update Overview

Link to the 2007 ITRS chapters





Handler RequirementsProbing Difficult ChallengesWafer Probe Technology RequirementsTest Socket Technology Requirements

RF and AMS for WirelessRF and Analog Mixed-Signal CMOS Technology RequirementsRF and Analog Mixed-Signal Bipolar Technology RequirementsOn-Chip Passives Technology RequirementsEmbedded Passives Technology RequirementsPower Amplifier Technology RequirementsBase Station Devices Technology Requirements

RF and Analog Mixed-Signal RFMEMS

Process Integration, Devices, and Structures (PIDS)Process Integration Difficult ChallengesHigh-performance Logic Technology RequirementsLow Standby Power Technology RequirementsLow Operating Power Technology RequirementsDRAM Technology RequirementsNon-volatile Memory Technology RequirementsReliability Difficult ChallengesReliability Technology Requirements


Emerging Research DevicesPlease refer to the ERD summary in the 2008 Update Overview

Emerging Research MaterialsPlease refer to the ERM summary in the 2008 Update Overview

Front End Processes Difficult ChallengesStarting Materials Technology Requirements—Near and Long-term YearsFront End Surface Preparation Technology Requirements—Near and Long-term YearsThermal, Thin Film, Doping and Etching Technology Requirements—Near-term YearsThermal, Thin Film, Doping and Etching Technology Requirements—Long-term YearsDRAM Stacked Capacitor Technology Requirements—Near and Long-term YearsDRAM Trench Capacitor Technology Requirements—Near and Long-term YearsFLASH Non-volatile Memory Technology RequirementsPhase Change Memory (PCM) Technology Requirements—Near and Long-term Years

Millimeter Wave 10 GHz–100 GHz Technology Requirements

FeRAM Technology Requirements—Near and Long-term Years

Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection LithographyLithography Difficult ChallengesLithography Technology Requirements—Near and Long-term YearsResist Requirements—Near and Long-term YearsResist SensitivitiesOptical Mask Requirements—Near and Long-term YearsEUVL Mask Requirements—Near and Long-term YearsImprint Template Requirements—Near and Long-term YearsMaskless Technology Requirements—Near and Long-term Years

Interconnect Difficult Challenges MPU Interconnect Technology Requirements—Near and Long-term YearsDRAM Interconnect Technology Requirements—Near and Long-term YearsInterconnect Surface Preparation Technology Requirements—Near and Long-term YearsOptions for Interconnects Beyond the Metal/Dielectric SystemHigh Density Through Silicon via Draft Specification

Factory Integration Difficult Challenges—Near and Long-term Years Key Focus Areas and Issues for FI Functional Areas Beyond 2007 Factory Operations Technology Requirements—Near and Long-term Years Production Equipment Technology Requirements—Near and Long-term Years Material Handling Systems Technology Requirements—Near and Long-term Years Factory Information and Control Systems Technology Requirements—Near and Long-term Years Facilities Technology Requirements—Near and Long-term Years Crosscut Issues Relating to Factory Integration List of Next Wafer Size Challenges

Assembly and PackagingAssembly and Packaging Difficult Challenges Single-chip Packages Technology Requirements—Near and Long-term YearsChip-to-package Substrate Technology Requirements—Near and Long-term YearsSubstrate to Board Pitch—Near and Long-term YearsWarpage at Peak TemperaturePackage Substrates—Near and Long-term YearsPolymer Package Substrate Design Parameters—Near and Long-term YearsCost Performance Glass-ceramic Substrates (high end FCBGA)Wafer Level Packaging—Near and Long-term Years

Minimum Density of Metallic SWCNTs Needed to Exceed Minimum Cu Wire Conductivity

Key Technical Parameters for Stacked Architectures Using TSVComparison of SoC and SiP ArchitecturePackage Level System IntegrationProcesses for SiPSystem in Package Requirements—Near and Long-term YearsThinned Silicon Wafer Thickness 200 mm/300 mm—Near and Long-term YearsChallenges and Potential Solutions in Thinning Si WafersSiP Failure ModesSome Common Optoelectronic Packages and Their ApplicationsOptical Communications and InterconnectOptoelectronic Packaging Challenges and Potential SolutionsMEMS Packaging MethodsMEMS Packaging ExamplesMaterials ChallengesPackage Substrate Physical Properties Automotive Operating Environment Specifications


CROSSCUT WORKING GROUP TABLES

Environment, Safety, and HealthESH Difficult ChallengesESH Intrinsic Requirements—Near-term YearsESH Intrinsic Requirements—Long-term YearsChemicals and Materials Management Technology RequirementsProcess and Equipment Management Technology Requirements—Near-term YearsProcess and Equipment Management Technology Requirements—Long-term YearsFacilities Energy and Water Optimization Technology RequirementsSustainability and Product Stewardship Technology Requirements

Definitions for the Different Interface PointsYield Enhancement Difficult ChallengesDefect Budget Technology Requirement AssumptionsYield Model and Defect Budget MPU Technology RequirementsYield Model and Defect Budget DRAM/Flash Technology RequirementsDefect Inspection on Patterned Wafer Technology Requirements

Defect Inspection on Unpatterned Wafers: Macro, and Bevel Inspection Technology Requirements

Defect Review and Automated Defect Classification Technology RequirementsTechnology Requirements for Wafer Environmental Contamination Control

Metrology Difficult ChallengesMetrology Technology RequirementsLithography Metrology (Wafer) Technology RequirementsLithography Metrology (Mask) Technology Requirements: OpticalLithography Metrology (Mask) Technology Requirements: EUVFront End Processes Metrology Technology Requirements—Near-term YearsFront End Processes Metrology Technology Requirements—Long-term YearsInterconnect Metrology Technology Requirements—Near and Long-term Years

Modeling and SimulationModeling and Simulation Difficult ChallengesModeling and Simulation Technology Requirements: Capabilities—Near-term YearsModeling and Simulation Technology Requirements: Capabilities—Long-term YearsModeling and Simulation Technology Requirements: Accuracy—Near-term Years





Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection Lithography

Overall Roadmap Technology Characteristics [ORTC]

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Trends GraphicTable 1a&b

Table 1c&d

Table 1e&f

Table 1g&h

Table 1i&j

Table 2a&b

Table 3a&b

Table 4a&b

Table 4c&d

Table 5a&b

Table 6a&b

Table 7a&b

2007 ITRS Chapters

2008INDEX

Overall Roadmap Technology Characteristics [ORTC]

Product Generations and Chip Size Model Technology Trend Targets

DRAM and Flash Production Product Generations and Chip Size Model

DRAM Introduction Product Generations and Chip Size Model

MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model

High-Performance MPU and ASIC Product Generations and Chip Size Model

Lithographic-Field and Wafer Size Trends

Performance of Packaged Chips: Number of Pads and Pins

Performance and Package Chips: Pads, Cost

Performance and Package Chips: Frequency On-chip Wiring Levels

Electrical Defects [**]

Power Supply and Power Dissipation

Cost

2008 Update Trend Graphic, including ITRS 7/15 meetings Final Litho Printed Gate Length ProposalORTCINDEX

2007 ITRS Chapters

2008INDEX

2008 Update Trend Graphic, including ITRS 7/15 meetings Final Litho Printed Gate Length Proposal

Table 1a&bProduct Generations and Chip Size Model Technology Trend Targets

Year of Production 2007 2008 2009 2010 2011 2012 2013 2014

Flash ½ Pitch (nm) (un-contacted Poly)(f) 54 45 40 36 32 28 25 23

DRAM ½ Pitch (nm) (contacted) 65 57 50 45 40 36 32 28


MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 68 59 52 45 40 36 32 28

MPU Printed Gate Length (nm) 42 38 34 30 27 24 21 19

MPU Printed Gate Length (GLpr) (nm) †† 54 47 41 35 31 28 25 22

MPU Physical Gate Length (GLph) (nm) 25 23 20 18 16 14 13 11

MPU Physical Gate Length (GLph) (nm) 32 29 27 24 22 20 18 17

ASIC/Low Operating Power Printed Gate Length (nm) †† 54 48 42 38 34 30 27 24

ASIC/Low Operating Power Printed Gate Length (nm) †† 64 54 47 41 35 31 25 22

ASIC/Low Operating Power Physical Gate Length (nm) 32 28 25 23 20 18 16 14

ASIC/Low Operating Power Physical Gate Length (nm) 38 32 29 27 24 22 18 17

2015

20

25

25

25

17

20

10

15

21

20

13

15

2016 2017 2018 2019 2020 2021 2022

17.9 15.9 14.2 12.6 11.3 10.0 8.9

23 20 18 16 14 13 11

22.5 20.0 17.9 15.9 14.2 12.6 11.3

22.5 20.0 17.9 15.9 14.2 12.6 11.3

15 13 12 11 9.5 8.4 7.5

17.7 15.7 14.0 12.5 11.1 9.9 8.8

8.9 8.0 7.1 6.3 5.6 5.0 4.5

14.0 12.8 11.7 10.7 9.7 8.9 8.1

19 17 15 13 12 11 9.5

17.7 15.7 14.0 12.5 11.1 9.9 8.8

11 10 8.9 8.0 7.1 6.3 5.6

14.0 12.8 11.7 10.7 9.7 8.9 8.1

Table 1c&d DRAM and Flash Production Product Generations and Chip Size Model

Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015

DRAM ½ Pitch (nm) (contacted) 68 59 52 45 40 36 32 28 25

MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 68 59 52 45 40 36 32 28 25

MPU Physical Gate Length (nm) 32 29 27 24 22 20 18 17 15

DRAM Product Table

Cell area factor [a] 6 6 6 6 6 6 6 6 6

0.028 0.021 0.016 0.012 0.0096 0.0077 0.0061 0.0048 0.0038

Cell array area at production (% of chip size) § 56.08% 56.08% 56.08% 56.08% 56.08% 56.08% 56.08% 56.08% 56.08%

Generation at production § 2G 2G 2G 4G 4G 4G 8G 8G 8G

Functions per chip (Gbits) 2.15 2.15 2.15 4.29 4.29 4.29 8.59 8.59 8.59

107 81 61 93 74 59 93 74 59

Gbits/cm2 at production § 2.01 2.65 3.50 4.62 5.82 7.33 9.23 11.63 14.65

Flash Product Table

Flash ½ Pitch (nm) (un-contacted Poly)(f) 53.5 45.0 40.1 35.7 31.8 28.3 25.3 22.5 20.0


0.0115 0.0081 0.0064 0.0051 0.0040 0.0032 0.0026 0.0020 0.0016

Cell array area at production (% of chip size) § 68.35% 68.35% 68.35% 68.35% 68.35% 68.35% 68.35% 68.35% 68.35%

Generation at production § SLC 8G 8G 8G 16G 16G 16G 32G 32G 32G

Generation at production § MLC [2 bits/cell] 16G 16G 16G 32G 32G 32G 64G 64G 64G

Generation at production § MLC [4 bits/cell] 32G 32G 32G 64G 64G 64G 128G 128G 128G

Functions per chip (Gbits) SLC 8.59 8.59 8.59 17.18 17.18 17.18 34.36 34.36 34.36

Functions per chip (Gbits) MLC [2 bits/cell] 17.18 17.18 17.18 34.36 34.36 34.36 68.72 68.72 68.72

Functions per chip (Gbits) MLC [4 bits/cell] 34.36 34.36 34.36 68.72 68.72 68.72 137.44 137.44 137.44

143.96 101.80 80.80 128.26 101.80 80.80 128.26 101.80 80.80

143.96 101.80 80.80 128.26 101.80 80.80 128.26 101.80 80.80

5.97E+09 8.44E+09 1.06E+10 1.34E+10 1.69E+10 2.13E+10 2.68E+10 3.38E+10 4.25E+10

Bits/cm2 at production § MLC [2 bits/cell] 1.19E+10 1.69E+10 2.13E+10 2.68E+10 3.38E+10 4.25E+10 5.36E+10 6.75E+10 8.51E+10

Cell area [Ca = af2] (um2)

Chip size at production (mm2)§


Chip size at production (mm2)§ SLC

Chip size at production (mm2)§ MLC [2 bits/cell & 4 bits/cell]

Bits/cm2 at production § SLC

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

6 6 6 6 6 6 6

0.0030 0.0024 0.0019 0.0015 0.0012 0.00096 0.00076

56.08% 56.08% 56.08% 56.08% 56.08% 56.08% 56.08%

16G 16G 16G 32G 32G 32G 64G

17.18 17.18 17.18 34.36 34.36 34.36 68.72

93 74 59 93 74 59 93

18.46 23.26 29.31 36.93 46.52 58.61 73.85

17.9 15.9 14.2 12.6 11.3 10.0 8.9

4 4 4 4 4 4 4

0.0013 0.0010 0.00080 0.00064 0.00051 0.00040 0.00032

68.35% 68.35% 68.35% 68.35% 68.35% 68.35% 68.35%

64G 64G 64G 128G 128G 128G 256G

128G 128G 128G 256G 256G 256G 512G

256G 256G 256G 512G 512G 512G 1024G

68.72 68.72 68.72 137.44 137.44 137.44 274.88

137.44 137.44 137.44 274.88 274.88 274.88 549.76

274.88 274.88 274.88 549.76 549.76 549.76 1099.51

128.26 101.80 80.80 128.26 101.80 80.80 128.26

128.26 101.80 80.80 128.26 101.80 80.80 128.26

5.36E+10 6.75E+10 8.51E+10 1.07E+11 1.35E+11 1.70E+11 2.14E+11

1.07E+11 1.35E+11 1.70E+11 2.14E+11 2.70E+11 3.40E+11 4.29E+11

Table 1e&f DRAM Introduction Product Generations and Chip Size Model






0.028 0.021 0.016 0.012 0.0096 0.0077 0.0061 0.0048 0.0038

Cell array area at introduction (% of chip size) § 73.52% 73.76% 73.97% 74.16% 74.30% 74.47% 74.61% 74.70% 74.83%

Generation at introduction § 16G 16G 16G 32G 32G 32G 64G 64G 64G

Functions per chip (Gbits) 17.18 17.18 34.36 34.36 34.36 68.72 68.72 68.72 68.72

652 493 745 563 446 706 560 444 351


Chip size at introduction (mm2) §

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

6 6 6 6 6 6 6

0.0030 0.0024 0.0019 0.0015 0.0012 0.00096 0.00076

74.93% 75.00% 75.09% 75.18% 75.27% 75.36% 75.45%

128G 128G 128G 256G 256G 256G 512G

137.44 137.44 137.44 274.88 274.88 274.88 549.76

557 442 350 555 440 349 553

Table 1g&h MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model





SRAM Cell (6-transistor) Area factor ++ 97.5 100.7 104.1 107.8 106.7 105.7 104.8 104.1 103.4

Logic Gate (4-transistor) Area factor ++ 279 292 306 320 320 320 320 320 320

SRAM Cell (6-transistor) Area efficiency ++ 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63 0.63

Logic Gate (4-transistor) Area efficiency ++ 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5

SRAM Cell (6-transistor) Area (um2)++ 0.45 0.35 0.28 0.22 0.17 0.13 0.11 0.084 0.066

SRAM Cell (6-transistor) Area w/overhead (um2)++ 0.73 0.57 0.45 0.35 0.27 0.22 0.17 0.13 0.11

Logic Gate (4-transistor) Area (um2) ++ 1.3 1.0 0.82 0.65 0.51 0.41 0.32 0.26 0.20

Logic Gate (4-transistor) Area w/overhead (um2) ++ 2.6 2.1 1.6 1.3 1.0 0.82 0.65 0.51 0.41

827 1,057 1,348 1,718 2,187 2,781 3,532 4,484 5,687

154 194 245 309 389 490 617 778 980

Generation at introduction * p10c p10c p13c p13c p13c p16c p16c p16c p19c

773 773 1546 1546 1546 3092 3092 3092 6184

280 222 353 280 222 353 280 222 353

276 348 438 552 696 876 1104 1391 1753

Generation at production * p07c p07c p07c p10c p10c p10c p13c p13c p13c

386 386 386 773 773 773 1546 1546 1546

140 111 88 140 111 88 140 111 88

276 348 438 552 696 876 1104 1391 1753

Transistor density SRAM (Mtransistors/cm2)

Transistor density logic (Mtransistors/cm2)

Functions per chip at introduction (million transistors [Mtransistors])

Chip size at introduction (mm2) ‡

Cost performance MPU (Mtransistors/cm2 at introduction) (including on-chip SRAM) ‡

Functions per chip at production (million transistors [Mtransistors])

Chip size at production (mm2) §§

Cost performance MPU (Mtransistors/cm2 at production, including on-chip SRAM) ‡

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

102.8 102.2 101.7 101.3 100.9 100.5 100.1

320 320 320 320 320 320 320

0.63 0.63 0.63 0.63 0.63 0.63 0.63

0.5 0.5 0.5 0.5 0.5 0.5 0.5

0.052 0.041 0.032 0.026 0.020 0.016 0.01

0.083 0.066 0.052 0.041 0.032 0.026 0.020

0.16 0.13 0.10 0.081 0.064 0.051 0.040

0.32 0.26 0.20 0.16 0.13 0.10 0.08

7,208 9,130 11,558 14,625 18,497 23,394 29,588

1,235 1,555 1,960 2,469 3,111 3,920 4,938

p19c p19c p22c p22c p22c p25c p25c

6184 6184 12368 12368 12368 24736 24736

280 222 353 280 222 353 280

2209 2783 3506 4417 5565 7012 8834

p16c p16c p16c p19c p19c p19c p22c

3092 3092 3092 6184 6184 6184 12368

140 111 88 140 111 88 140

2209 2783 3506 4417 5565 7012 8834

Table 1i&j High-Performance MPU and ASIC Product Generations and Chip Size Model





Logic (Low-volume Microprocessor) High-performance ‡

Generation at Introduction p10h p10h p13h p13h p13h p16h p16h p16h p19h

Functions per chip at introduction (million transistors) 2212 2212 4424 4424 4424 8848 8848 8848 17696

620 492 391 620 492 391 620 492 391

Generation at production ** p07h p07h p07h p10h p10h p10h p13h p13h p13h

Functions per chip at production (million transistors) 1106 1106 1106 2212 2212 2212 4424 4424 4424

310 246 195 310 246 195 310 246 195

357 449 566 714 899 1133 1427 1798 2265

ASIC

357 449 566 714 899 1133 1427 1798 2265

858 858 858 858 858 858 858 858 858

3,061 3,857 4,859 6,122 7,713 9,718 12,244 15,427 19,436

Chip size at introduction (mm2)

Chip size at production (mm2) §§

High-performance MPU Mtransistors/cm2 at introduction and production (including on-chip SRAM) ‡

ASIC usable Mtransistors/cm2 (auto layout)

ASIC max chip size at production (mm2) (maximum lithographic field size)

ASIC maximum functions per chip at production (Mtransistors/chip) (fit in maximum lithographic field size)

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

p19h p19h p22h p22h p22h p25h p25h

17696 17696 35391 35391 35391 70782 70782

620 492 391 620 492 391 620

p16h p16h p16h p19h p19h p19h p22h

8848 8848 8848 17696 17696 17696 35391

310 246 195 310 246 195 310

2854 3596 4531 5708 7192 9061 11416

2854 3596 4531 5708 7192 9061 11416

858 858 858 858 858 858 1716

24,488 30,853 38,873 48,977 61,707 77,746 195,906

Table 2a&b Lithographic-Field and Wafer Size Trends



Flash ½ Pitch (nm) (un-contacted Poly)(f) 54 45 40 36 32 28 25 22 20



Lithography Field Size

858 858 858 858 858 858 858 858 858

Maximum Lithography Field Size—length (mm) 33 33 33 33 33 33 33 33 33

Maximum Lithography Field Size—width (mm) 26 26 26 26 26 26 26 26 26

Bulk or epitaxial or SOI wafer 300 300 300 300 300 450 450 450 450

Maximum Lithography Field Size—area (mm2)

Maximum Substrate Diameter (mm)—High-volume Production (>20K parts wafer starts per month)

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

858 858 858 858 858 858 858

33 33 33 33 33 33 33

26 26 26 26 26 26 26

450 450 450 450 450 450 450

Table 3a&bPerformance of Packaged Chips: Number of Pads and Pins






Total pads—MPU unchanged 3,072 3,072 3,072 3,072 3,072 3,072 3,072 3,072 3,072

Signal I/O—MPU (% of total pads) 33.3% 33.3% 33.3% 33.3% 33.3% 33.3% 33.3% 33.3% 33.3%

Power and ground pads—MPU (% of total pads) 66.7% 66.7% 66.7% 66.7% 66.7% 66.7% 66.7% 66.7% 66.7%

Total pads—ASIC High Performance unchanged 4,400 4,400 4,600 4,800 4,800 5,000 5,400 5,400 5,600

50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0%

50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0%

Number of Total Package Pins—Maximum [1]

Microprocessor/controller, cost-performance 600–2140 600–2400 660–2801 660–2783 720- 3061 720–3367 800–3704 800-4075 880–4482

Microprocessor/controller, high-performance 4000 4400 4620 4851 5094 5348 5616 5896 6191

ASIC (high-performance) 4000 4400 4620 4851 5094 5348 5616 5896 6191

Number of Chip I/Os (Number of Total Chip Pads)—Maximum

Signal I/O pads—ASIC high-performance (% of total pads)

Power and ground pads—ASIC high-performance (% of total pads)

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

3,072 3,072 3,072 3,072 3,072 3,072 3,072

33.3% 33.3% 33.3% 33.3% 33.3% 33.3% 33.3%

66.7% 66.7% 66.7% 66.7% 66.7% 66.7% 66.7%

6,000 6,000 6,200 6,200 6,200 6,840 6,840

50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0%

50.0% 50.0% 50.0% 50.0% 50.0% 50.0% 50.0%

880–4930 960-5423 960–5966 1050-6562 1050 - 7218 1155-7940 1155-8337

6501 6826 7167 7525 7902 8297 8712

6501 6826 7167 7525 7902 8297 8712

Table 4a&b Performance and Package Chips: Pads, Cost





MPU Physical Gate Length (nm) 32 29 27 24 22 20 18 17

Pad pitch—ball bond 30 30 25 25 25 20 20 20

25 25 20 20 20 20 20 20

130 130 130 130 120 110 110 100

55 50 45 45 45 40 40 40

60 60 60 55 55 50 45 45

Cost-Per-Pin

.69-1.19 .66-1.13 .63-1.70 .60-1.20 .57-.97 .54-.92 .51-.87 .48 - .83

.27-.50 .25-.48 .24-.46 .23-.44 .22-.42 .21-.40 .20-.38 .20-.36

Chip Pad Pitch (micron)

Pad pitch—Wedge bond

Pad Pitch—Area array flip-chip (cost-performance, high-performance)

Pad Pitch—2-row staggered-pitch (micron)

Pad Pitch—Three-tier-pitch pitch (micron)

Package cost (cents/pin) (Cost per Pin Minimum for Contract Assembly – Cost-performance) — minimum–maximum

Package cost (cents/pin) (Low-cost, hand-held and memory) — minimum–maximum

2015

25

20

25

15

20

20

100

40

45

.46 - .79

.20 -.34

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

20 20 20 20 20 20 20

20 20 20 20 20 20 20

95 95 90 90 85 85 80

35 35 35 35 35 35 35

45 45 45 45 45 45 45

.44 - .75 .42 - .71 .39 - .68 .37 - .64 .35 - .61 .33-.58 0.32-0.55

.20-.32 .20-.30 .20-.29 .20-.27 .20-.26 .19-.25 .19-.25

Table 4c&d Performance and Package Chips: Frequency On-chip Wiring Levels






On-chip local clock [1] 4.700 5.063 5.454 5.875 6.329 6.817 7.344 7.911 8.522

11 12 12 12 12 12 13 13 13

Chip Frequency (MHz)

Maximum number wiring levels [3] [**]

[**] [Note ** : The Interconnect TWG has deleted their "optional levels" from table 80a&b, therefore the ORTC "Maximum number wiring levels - maximum" line is deleted; also the "Maximum number wiring levels - minimum" is now just "Maximum number of wiring levels."

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

9.180 9.889 10.652 11.475 12.361 13.315 14.343

13 14 14 14 14 15 15

[**] [Note ** : The Interconnect TWG has deleted their "optional levels" from table 80a&b, therefore the ORTC "Maximum number wiring levels - maximum" line is deleted; also the "Maximum number wiring levels - minimum" is now just "Maximum number of wiring levels."






2503 2503 2503 2503 2503 2503 2503 2503 2503

2503 2503 2503 2503 2503 2503 2503 2503 2503

3517 2957 2957 2957 2957 2957 2957 2957 2957

2430 2430 2430 2430 2430 2430 2430 2430 2430

1395 1395 1395 1395 1395 1395 1395 1395 1395

# Mask Levels—MPU 33 35 35 35 35 35 37 37 37

# Mask Levels—DRAM 24 24 24 26 26 26 26 26 26

# Mask Levels—Flash [to be added in 2009] ?? ?? ?? ?? ?? ?? ?? ?? ??

Table 5a&b Electrical Defects [**]

Flash Random Defect D 0 at production chip size and 89.5% yield (faults/m 2) §

Flash Random Defect D 0 at production chip size and 89.5% yield (faults/m 2) §

DRAM Random Defect D0 at production chip size and 89.5% yield (faults/m2) §

DRAM Random Defect D0 at production chip size and 89.5% yield (faults/m2) §

MPU Random Defect D0 at production chip size and 83% yield (faults/ m2) §§

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

2503 2503 2503 2503 2503 2503 2503

2503 2503 2503 2503 2503 2503 2503

2957 2957 2957 2957 2957 2957 2957

2430 2430 2430 2430 2430 2430 2430

1395 1395 1395 1395 1395 1395 1395

37 39 39 39 39 39 39

26 26 26 26 26 26 26

?? ?? ?? ?? ?? ?? ??





MPU Physical Gate Length (nm) 32 29 27 24 22 20 18 17

Power Supply Voltage (V)

Vdd (high-performance) 1.1 1.0 1.0 1.0 0.95 0.90 0.90 0.90

Vdd (high-performance) 1.1 1.1 1.1 1.1 1.0 1.0 1.0 1.0

0.80 0.80 0.80 0.70 0.70 0.70 0.60 0.60

0.90 0.80 0.80 0.80 0.77 0.70 0.70 0.65

Allowable Maximum Power [1]

High-performance with heatsink (W) 102 146 143 146 161 158 149 152

310 310 310 310 310 310 310 310

0.33 0.47 0.46 0.47 0.52 0.51 0.48 0.49

Cost-performance (W) 102 146 143 146 161 158 149 152

140 140 140 140 140 140 140 140

0,57 0.86 0.9 0.96 1.13 1.11 1.1 1.17

Battery (W)—(low-cost/hand-held) 3 3 3 3 3 3 3 3

Table 6a&b Power Supply and Power Dissipation

Vdd (Low Operating Power, high Vdd transistors)[WAS]

Vdd (Low Operating Power, high Vdd transistors)

Maximum Affordable Chip Size Target for High-performance MPU Maximum Power Calculation

Maximum High-performance MPU Maximum Power Density for Maximum Power Calculation

Maximum Affordable Chip Size Target for Cost-performance MPU Maximum Power Calculation

Maximum Cost-performance MPU Maximum Power Density for Maximum Power Calculation

2015

25

20

25

15

0.80

1.0

0.60

0.60

143

310

0.46

143

140

1.19

3

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

0.80 0.70 0.70 0.70 0.65 0.65 0.65

0.90 0.90 0.90 0.90 0.80 0.80 0.80

0.50 0.50 0.50 0.50 0.50 0.45 0.45

0.60 0.60 0.60 0.57 0.50 0.50 0.50

130 130 136 133 130 130 130

310 310 310 310 310 310 310

0.42 0.42 0.44 0.43 0.42 0.42 0.42

130 130 136 133 130 130 130

140 140 140 140 140 140 140

1.07 1.12 1.19 1.27 1.24 1.63 1.73

3 3 3 3 3 3 3

Table 7a&b Cost






Affordable Cost per Function ++

DRAM cost/bit at (packaged microcents) at samples/introduction 2.6 1.9 1.3 0.9 0.7 0.5 0.3 0.2 0.2

DRAM cost/bit at (packaged microcents) at production § 0.96 0.68 0.48 0.34 0.24 0.17 0.12 0.08 0.06

22.0 15.6 11.0 7.8 5.5 3.9 2.8 1.9 1.4

13.3 9.4 6.7 4.7 3.3 2.4 1.7 1.2 0.83

12.2 8.6 6.1 4.3 3.0 2.2 1.5 1.1 0.76

Cost-performance MPU (microcents/transistor)(including on-chip SRAM) at introduction §§

Cost-performance MPU (microcents/transistor)(including on-chip SRAM) at production §§

High-performance MPU (microcents/transistor)(including on-chip SRAM) at production §§

2016 2017 2018 2019 2020 2021 2022

22.5 20.0 17.9 15.9 14.2 12.6 11.3

18 16 14 13 11 10 9

22.5 20.0 17.9 15.9 14.2 12.6 11.3

14.0 12.8 11.7 10.7 9.7 8.9 8.1

0.1 0.1 0.1 0.0 0.0 0.0 0.0

0.04 0.03 0.02 0.01 0.01 0.01 0.01

0.97 0.69 0.49 0.34 0.24 0.17 0.12

0.59 0.42 0.29 0.21 0.15 0.10 0.07

0.54 0.38 0.27 0.19 0.13 0.10 0.07

Table SYSD1 Major Product Market Segments and Impact on System DriversMarket Drivers SOC Analog/MS MPU

I. Portable/consumer

1. Size/weight ratio: peak in 2004 Low power paramount Migrating on-chip for voice processing, A/D sampling, and even for some RF transceiver function

Specialized cores to optimize processing per microwatt

2. Battery life: peak in 2004

3. Function: 2×/2 years Need SOC integration (DSP, MPU, I/O cores, etc.)

4. Time-to-market: ASAP

II. Medical

1. Cost: slight downward pressure High-end products only. Reprogrammability possible. Mainly ASSP, especially for patient data storage and telemedicine; more SOC for high-end digital with cores for imaging, real-time diagnostics, etc.

Absolutely necessary for physical measurement and response but may not be integrated on chip

Often used for programmability especially when real-time performance is not important

(~1/2 every 5 years)

2. Time-to-market: >12 months Recent advances in multicore processors have made programmability and real-time performance possible

3. Function: new on-chip functions

4. Form factor often not important

5. Durability/safety

6. Conservation/ ecology

III. Networking and communications

1. Bandwidth: 4/3–4 years Large gate counts Migrating on-chip for MUX/DEMUX circuitry

MPU cores, FPGA cores and some specialized functions

2. Reliability High reliability

3. Time-to-market: ASAP More reprogrammability to accommodate custom functions

MEMS for optical switching.

4. Power: W/m3 of system

IV. Defense

1. Cost: not prime concern Most case leverage existing processors but some requirements may drive towards single-chip designs with programmability



2. Time-to-market: >12 months

3. Function: mostly on SW to ride Recent advances in multicore processors have made programmability and real-time performance possible

technology curve

4. Form factor may be important

5. High durability/safety

V. Office

1. Speed: 2/2 years Large gate counts; high speed Minimal on-chip analog; simple A/D and D/A

MPU cores and some specialized functions

2. Memory density: 2/2 years

3. Power: flat to decreasing, Drives demand for digital functionality Video i/f for automated camera monitoring, video conferencing

Increased industry partnerships on common designs to reduce development costs (requires data sharing and reuse across multiple design systems)

driven by cost and W/m3

4. Form factor: shrinking size Primarily SOC integration of custom off-the-shelf MPU and I/O cores

Integrated high-speed A/D, D/A for monitoring, instrumentation, and range-speed-position resolution

5. Reliability

VI. Automotive

1. Functionality Mainly entertainment systems Cost-driven on-chip A/D and D/A for sensor and actuators

2. Ruggedness (external

environment, noise) Mainly ASSP, but increasing SOC for high end using standard HW platforms with RTOS kernel, embedded software

Signal processing shifting to DSP for voice, visual

3. Reliability and safety

4. Cost Physical measurement (“communicating sensors” for proximity, motion, positioning); MEMS for sensors

A/D—analog to digital ASSP—application-specific standard product D/A—digital to analog DEMUX—demultiplexer

DSP—digital signal processing FPGA—field programmable gate array i/f—interface I/O—input/output HW—hardware

MEMS—microelectromechanical systems MUX—multiplexer RTOS—real-time operating system

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II. Medical

















IV. Defense






technology curve



V. Office









5. Reliability

VI. Automotive

















II. Medical

















IV. Defense






technology curve



V. Office









5. Reliability

VI. Automotive

















II. Medical

















IV. Defense






technology curve



V. Office









5. Reliability

VI. Automotive










Table SYSD2 SOC Consumer Driver Design Productivity Trends

2007 2008 2009

WAS Trend: SoC total Logic Size 1 1.29 1.62

IS (Normalized to 2007) 1 1.24 1.52

Requirement: % of reused design 38% 42% 46%

WAS Requirement: Productivity for new designs 1 1.25 1.54

IS (Normalized to 2007) 1 1.21 1.45

WAS 2 2.51 3.08

IS 2 2.42 2.89

Requirement: Productivity for reused designs (Normalized to productivity for new designs at 2008)

ORTCINDEX

2007 ITRS Chapters

2008INDEX

SOC Consumer Driver Design Productivity Trends

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

2.12 2.64 3.24 4.07 5.29 6.62 8.52 10.33 12.76 16.17 21.14 24.6 34.4

1.93 2.41 2.98 3.74 4.74 5.96 7.54 9.41 11.78 14.87 18.91 23.35 30.26

50% 54% 58% 62% 66% 70% 74% 78% 82% 86% 90% 92% 94%

1.96 2.38 2.84 3.47 4.37 5.31 6.63 7.78 9.3 11.38 14.36 16.4 22.51

1.79 2.17 2.61 3.19 3.92 4.78 5.87 7.09 8.58 10.46 12.84 15.57 19.8

3.92 4.76 5.68 6.94 8.74 10.62 13.26 15.56 18.59 22.75 28.71 32.79 45.02

3.58 4.35 5.22 6.37 7.84 9.56 11.73 14.18 17.16 20.93 25.68 31.13 39.6

Table SYSD3 Projected Mixed-Signal Figures of Merit for Four Circuit Types

Year of Production 2007 2010 2013 2016 2019

RF-CMOS ½ Pitch 65 45 32 22 18

20 28–32 40–50 50–80 60–90

1.4 1.5–1.7 1.8–2 2–2.4 2.4–3

15 30 50–70 90–100 110–130

1.5 2–2.5 2.5–3.5 3–5 4–6

[1] Lower bound is for "high-resolution/thermal noise limited" A/D converters; upper bound is for "low-resolution/speed limited" A/D converters.

FoMLNA (GHz)

FoMVCO (1/J) ×1022

FoMPA (W×GHz2) ×104

FoMADC (GHz/W) ×103 [1]

ORTCINDEX

2007 ITRS Chapters

2008INDEX

2022 Driver

13

70-100 Refer to the RF and AMS

2.7–3.5

120-140

6–10

[1] Lower bound is for "high-resolution/thermal noise limited" A/D converters; upper bound is for "low-resolution/speed limited" A/D converters.

Technologies for Wireless chapter

Table SYSD4a Embedded Memory Requirements

Year of Production 2007 2008 2009

DRAM ½ Pitch (nm) 65 55 50

65 65 65

140F² 140F² 140F²

Array efficiency [2] 0.7 0.7 0.7

Process overhead versus standard CMOS – #added mask layers 2 2 2

1.1 1/1.1 1/1.1

Static power dissipation (mW/Cell) [5] 3E-4/1E-6 3E-4/1E-6 3E-4/1E-6

Dynamic power consumption per cell (mW/MHz) [6] 4.5E-7/7E-7 4E-7/6.5E-7 4E-7/6E-7

Read cycle time (ns) [7] 0.3/1.5 0.3/1.5 0.3/1.5

Write cycle time (ns) [7] 0.3/1.5 0.3/1.5 0.3/1.5

Percentage of MBU on total SER 16% 16% 16%

Soft error rate (FIT/Mb) [8] 1150 1150 1150

Embedded Non-Volatile Memory (code/data), DRAM ½ pitch (nm) 90 90 90

Array efficiency – NOR FLOTOX/ NAND FLOTOX [10] 0.6/0.8 0.6/0.8 0.6/0.8

Process overhead versus standard CMOS – #added mask layers [3] 6–8 6–8 6–8

Read operating voltage (V) 2V 2V 2V

12V/15V 12V/15V 12V/15V

Static power dissipation (mW/cell) [5] 1.00E-06 1.00E-06 1.00E-06

Dynamic power consumption per cell (mW/MHz) [6] 6.00E-09 6.00E-09 6.00E-09

Read cycle time (ns) – NOR FLOTOX / NAND FLOTOX [7] Oct-50 Oct-50 Oct-50

Program time per cell (µs) – NOR FLOTOX / NAND FLOTOX [12] 1.0/1000.0 1.0/1000.0 1.0/1000.0

Erase time per cell (ms) – NOR FLOTOX / NAND FLOTOX [12] 10.0/0.1 10.0/0.1 10.0/0.1

Data retention requirement (years) [12] 10 10 10

Endurance requirement [12] 100000 100000 100000

Embedded DRAM, ½ pitch (nm) 90 90 65

12–30 12–30 12–30

Array efficiency [2] 0.6 0.6 0.6

Process overhead versus standard CMOS – #added mask layers [3] 3–5 3–5 3–5

Read operating voltage (V) 2 2 1.8

Static power dissipation (mW/Cell) [5] 1.00E-11 1.00E-11 1.00E-11

Dynamic power consumption per cell (mW/MHz) [6] 1.00E-07 1.00E-07 1.00E-07

DRAM retention time (ms) [12] 64 64 64

Read/Write cycle time (ns) [7] 0.7 0.7 0.5

Soft error rate (FIT/Mb) [8] 60 60 60

FIT—failures in time FLOTOX—floating gate tunnel oxide MBU—multiple bit upsets NAND—“not AND” logic operation

NOR—“not OR” logic operation

Definitions of Terms for Tables SYSD4a and SYSD4b:

CMOS SRAM High-performance, low standby power (HP/LSTP) DRAM ½ pitch (nm), Feature Size – F

6T bit cell size (F2) [1]

Operating voltage – Vdd (V) [4]

Cell size (F2) – NOR FLOTOX / NAND FLOTOX [9] 10F2/5F2 10F2/5F2 10F2/5F2

Write (program/erase) on chip maximum voltage (V) – NOR/NAND [11]

1T1C bit cell size (F2) [13]

ORTCINDEX

2007 ITRS Chapters

2008INDEX

[1] Size of the standard 6T CMOS SRAM cell as a function of minimum feature size.

[2] Typical array efficiency defined as (core area / memory instance area).

[8] A FIT is a failure in 1 billion hours. This data is presented as FIT per megabit.

[11] Maximum voltage required for operation, typically used in WRITE operation. Data refer to the NVM device requirements table in the PIDS chapter.

[13] Size of the standard cell for embedded trench DRAM cell. Data refers to the DRAM requirements table in the PIDS chapter.

[3] Typical number of extra masks needed over standard CMOS logic process in equivalent technology. This is typically zero; however for some high-performance or highly reliable (noise immune) SRAMs special process options are sometimes applied like additional high—V th pMOS cell transistors and using higher Vdd for better noise margin or zero-Vth access transistors for fast read-out.

[4] Nominal operating voltage refers to the HP and LSTP devices in the logic device requirements table in the PIDS chapter.

[5] Static power dissipation per cell in standby mode. This is measured at I_standby × Vdd. (off-current and Vdd are taken from the HP and LSTP devices in the logic device requirements table in the PIDS Chapter.

[6] This parameter is a strong function of array architecture. However, a parameter for technology can be determined per cell level. Assume full V dd swing on the Wordline (WL) and 0.8 Vdd swing on the Bitline (BL). Determine the WL capacitance per cell (CWL) and BL capacitance per cell (CBL). Then: dynamic power consumption per MHz per cell = V dd × CWL (per cell) × (Vdd) + Vdd × CBL (per cell) × (Vdd) ×106.

[7] Read cycle time is the typical time it takes to complete a READ operation from an address. Write cycle time is the typical time it takes to complete a WRITE operation to an address. Both cycle times depend on memory size and architecture.

[9] Size of the standard 1T FLOTOX cell/size of the standard 2T select gate (SG) cell/size of the standard NAND cell. Cell size is somewhat enhanced compared to stand-alone NVM due to integration issues.

[10] Array efficiency of the standard stacked gate NOR architecture/standard split gate NOR architecture/standard NAND architecture. Data refer to the NVM device requirements table in the PIDS chapter.

[12] Program time per cell is typically the time needed to program data to a cell. Erase time per cell is typically the time needed to erase a cell. Data retention requirement is the duration for which the data must remain non-volatile even under worst-case conditions. Endurance requirement specifies the number of times the cell can be programmed and erased.

2010 2013 2016 2019 2022

45 35 25 18 13

45 35 25 18 13

140F²

0.7 0.7 0.7 0.7 0.7

2 2 2 2 2

1 0.9/1 0.8/0.9 0.7/0.8 0.7/0.8

5E-4/1.2E-6 1E-3/1.5E-6 2E-3/2E-6 3E-3/2.5E-6 5E-3/3E-6

3E-7/5E-7 2.5E-7/4.5E-7 2E-7/4E-7 1.5E-7/3E-7 1E-7/2E-7

0.2/1.2 0.15/0.8 0.1/0.5 0.07/0.3 0.07/0.3

0.2/1.2 0.15/0.8 0.1/0.5 0.07/0.3 0.07/0.3

32% 64% 100% 100% 100%

1200 1250 1300 1350 1400

65 45 35 25 18

0.6/0.8 0.6/0.8 0.6/0.8 0.6/0.8 0.6/0.8

6–8 6–8 6–8 6–8 6–8

1.8V 1.5V 1.3V 1.2V 1.1V

12V/15V 12V/15V 12V/15V 12V/15V 12V/15V

1.00E-06 1.00E-06 1.00E-06 1.00E-06 1.00E-06

6.00E-09 4.00E-09 3.50E-09 3.00E-09 3.00E-09

Jul-35 25-May 3.5/18 2.5/12 10-Feb

1.0/1000.0 1.0/1000.0 1.0/1000.0 1.0/1000.0 1.0/1000.0

10.0/0.1 10.0/0.1 10.0/0.1 10.0/0.1 10.0/0.1

10 10 10 10 10

100000 100000 100000 100000 100000

65 45 35 25 25

12–30 12–30 12–30 12–30 12–30

0.6 0.6 0.6 0.6 0.6

3–5 3–6 3–6 3–6 3–6

1.7 1.6 1.5 1.5 1.5

1.00E-11 1.00E-11 1.00E-11 1.00E-11 1.00E-11

1.50E-07 1.60E-07 1.70E-07 1.70E-07 1.70E-07

64 64 64 64 64

0.4 0.3 0.25 0.2 0.2

60 60 60 60 60

140F2 140F2 140F2 140F2

10F2/5F2 10F2/5F2 10F2/5F2 10F2/5F2 10F2/5F2

[1] Size of the standard 6T CMOS SRAM cell as a function of minimum feature size.

[2] Typical array efficiency defined as (core area / memory instance area).

[8] A FIT is a failure in 1 billion hours. This data is presented as FIT per megabit.

[11] Maximum voltage required for operation, typically used in WRITE operation. Data refer to the NVM device requirements table in the PIDS chapter.

[13] Size of the standard cell for embedded trench DRAM cell. Data refers to the DRAM requirements table in the PIDS chapter.

[3] Typical number of extra masks needed over standard CMOS logic process in equivalent technology. This is typically zero; however for some high-performance or highly reliable (noise pMOS cell transistors and using higher Vdd for better noise margin or zero-Vth access transistors for

PIDS chapter.

are taken from the HP and LSTP devices in the logic device requirements table

[6] This parameter is a strong function of array architecture. However, a parameter for technology can be determined per cell level. Assume full V dd swing on the Wordline (WL) and 0.8 Vdd swing on the Bitline (BL). Determine the WL capacitance per cell (CWL) and BL capacitance per cell (CBL). Then: dynamic power consumption per MHz per cell = V dd × CWL (per cell) ×

[7] Read cycle time is the typical time it takes to complete a READ operation from an address. Write cycle time is the typical time it takes to complete a WRITE operation to an address. Both

[9] Size of the standard 1T FLOTOX cell/size of the standard 2T select gate (SG) cell/size of the standard NAND cell. Cell size is somewhat enhanced compared to stand-alone NVM due to

[10] Array efficiency of the standard stacked gate NOR architecture/standard split gate NOR architecture/standard NAND architecture. Data refer to the NVM device requirements table in

[12] Program time per cell is typically the time needed to program data to a cell. Erase time per cell is typically the time needed to erase a cell. Data retention requirement is the duration for which the data must remain non-volatile even under worst-case conditions. Endurance requirement specifies the number of times the cell can be programmed and erased.

Table DESN1 Overall Design Technology ChallengesChallenges ≥ 32 nm Summary of Issues

Design productivity System level: high level of abstraction (HW/SW) functionality spec, platform based design, multi-processor programmability, system integration, AMS co-design and automation

Verification: executable specification, ESL formal verification, intelligent test bench, coverage-based verification

Logic/circuit/layout: analog circuit synthesis, multi-objective optimization

Power consumption Logic/circuit/layout: dynamic and static (leakage), system and circuit, power optimization

Manufacturability Performance/power variability, device parameter variability, lithography limitations impact on design, mask cost, quality of (process) models

ATE interface test (multi-Gb/s), mixed-signal test, delay BIST, test-volume-reducing DFT

Reliability Logic/circuit/layout: MTTF-aware design, BISR, soft-error correction

Interference Logic/circuit/layout: signal integrity analysis, EMI analysis, thermal analysis

Challenges <32 nm Summary of Issues

Design productivity Complete formal verification of designs, complete verification code reuse, complete deployment of functional coverage

Tools specific for SOI and non-static logic, and emerging devices

Cost-driven design flow

Heterogeneous component integration (optical, mechanical, chemical, bio, etc.)

Power consumption SOI power management

Manufacturability Uncontrollable threshold voltage variability

Advanced analog/mixed signal DFT (digital, structural, radio), “statistical” and yield-improvement DFT

Thermal BIST, system-level BIST

Reliability Autonomic computing, robust design, SW reliability

Interference Interactions between heterogeneous components (optical, mechanical, chemical, bio, etc.)

ATE—automatic test equipment BISR—built-in self repair BIST—built-in self test DFT—design for test

EMI—electromagnetic interference ESL—Electronic System-Level HW/SW—hardware/software MTTF—mean time to failureSOI—silicon on insulator

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Table DESN1 Overall Design Technology ChallengesChallenges ≥ 32 nm Summary of Issues

Design productivity System level: high level of abstraction (HW/SW) functionality spec, platform based design, multi-processor programmability, system integration, AMS co-design and automation

Verification: executable specification, ESL formal verification, intelligent test bench, coverage-based verification

Logic/circuit/layout: analog circuit synthesis, multi-objective optimization

Power consumption Logic/circuit/layout: dynamic and static (leakage), system and circuit, power optimization

Manufacturability Performance/power variability, device parameter variability, lithography limitations impact on design, mask cost, quality of (process) models

ATE interface test (multi-Gb/s), mixed-signal test, delay BIST, test-volume-reducing DFT

Reliability Logic/circuit/layout: MTTF-aware design, BISR, soft-error correction

Interference Logic/circuit/layout: signal integrity analysis, EMI analysis, thermal analysis

Challenges <32 nm Summary of Issues

Design productivity Complete formal verification of designs, complete verification code reuse, complete deployment of functional coverage

Tools specific for SOI and non-static logic, and emerging devices

Cost-driven design flow

Heterogeneous component integration (optical, mechanical, chemical, bio, etc.)

Power consumption SOI power management

Manufacturability Uncontrollable threshold voltage variability

Advanced analog/mixed signal DFT (digital, structural, radio), “statistical” and yield-improvement DFT

Thermal BIST, system-level BIST

Reliability Autonomic computing, robust design, SW reliability

Interference Interactions between heterogeneous components (optical, mechanical, chemical, bio, etc.)

ATE—automatic test equipment BISR—built-in self repair BIST—built-in self test DFT—design for test

EMI—electromagnetic interference ESL—Electronic System-Level HW/SW—hardware/software MTTF—mean time to failureSOI—silicon on insulator

Description of Improvement

In-House place and Route The transfer of the IC Place and Route function from the semiconductor to the design team.

IC Implementation Tool Suite Tightly integrated tool set that goes from RTL Synthesis to GDS II through IC Place and Route.

RTL Functional verification tool suite

Tightly integrated RTL Verification tool suite including all simulators and formal tools needed to complete the verification process.

Transactional Modeling The development of standard SystemC models at the Transaction Level of abstraction.

Very Large Block reuse Blocks that exceed 1M gates

Homogeneous Parallel Processing

Many identical processor cores which allows for performance, power efficiency and high reuse. (SMP)

Concurrent Software Infrastructure

A set of tools that allow concurrent software development and debug.

Heterogeneous parallel processing

Parallel Processing using different application specific processors for each of the separate functions in the system.

Transactional Memory A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing . It functions as an alternative to lock-based synchroniza tion.

System Design Automation True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains.

Executable Specification A design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.

ReBlocks from 75.000 – 1M gates

InA verification tool (cockpit) that takes in an ES-Level description and partitions it into verification blocks, then executes the proper verification tools on the blocks;

TaThe presence in the Design Team of at least one senior engineer who had experience in all phases of the design process.

ReBlocks from 2,500 – 74,999 gates

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Description of Improvement

In-House place and Route The transfer of the IC Place and Route function from the semiconductor to the design team.

IC Implementation Tool Suite Tightly integrated tool set that goes from RTL Synthesis to GDS II through IC Place and Route.

RTL Functional verification tool suite

Tightly integrated RTL Verification tool suite including all simulators and formal tools needed to complete the verification process.

Transactional Modeling The development of standard SystemC models at the Transaction Level of abstraction.

Very Large Block reuse Blocks that exceed 1M gates

Homogeneous Parallel Processing

Many identical processor cores which allows for performance, power efficiency and high reuse. (SMP)

Concurrent Software Infrastructure

A set of tools that allow concurrent software development and debug.

Heterogeneous parallel processing

Parallel Processing using different application specific processors for each of the separate functions in the system.

Transactional Memory A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing . It functions as an alternative to lock-based synchroniza tion.

System Design Automation True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains.

Executable Specification A design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.

ReBlocks from 75.000 – 1M gates

InA verification tool (cockpit) that takes in an ES-Level description and partitions it into verification blocks, then executes the proper verification tools on the blocks;

TaThe presence in the Design Team of at least one senior engineer who had experience in all phases of the design process.

ReBlocks from 2,500 – 74,999 gates

Table DESN2 System-Level Design Requirements


Design Reuse

Design block reuse [1] % of all logic 35% 36%

Platform Based Design

Available platforms [2] Normalized to 100% in the start year [3] 87% 83% 75%

Platforms supported [4] % of platforms fully supported by tools [5]10% 35%

High Level Synthesis

60% 66%

Reconfigurability

SOC reconfigurability [7] % of SOC functionality that is reconfigurable28% 30%

Analog/Mixed Signal

Analog automation [8] % versus digital automation [9] 17% 17% 24%

58% 62%

ADD Embedded Software

ADD Hardware productivity 100% 200.0% 200.0%

ADD Software productivity 100% 100.0% 100.0%

ADD100% 200% 400%

38%

25%

Accuracy of high level estimates (performance, area, power, costs) [6] % versus measurements 63%

28%

Modeling methodology, description languages, simulation environments [10] % vs. digital methodology 60%

SW productivity needed according to forecast from figure DESN3: (2x every year), normalized to 2007

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2010 2011 2012 2013 2014 2015 2016 2017 2018

40% 41% 42% 44% 48% 49% 51% 52%

70% 60% 55% 52% 48% 45% 43% 40% 37%

50% 57% 64% 75% 85% 90% 92% 94%

70% 73% 76% 80% 86% 90% 92% 94%

35% 38% 40% 42% 48% 50% 53% 56%

24% 27% 30% 32% 38% 40% 43% 46%

65% 67% 70% 73% 78% 80% 83% 86%

275.0% 275.0% 275.0% 275.0% 550% 550% 1100% 1100% 1760%

100.0% 100.0% 100% 100% 100% 100% 100% 100% 100%

800% 1600% 3200% 6400% 12800% 25600% 51200% 102400% 204800%

46%

80%

83%

45%

35%

76%

2019 2020 2021 2022

54% 55% 57% 58%

35% 32% 29% 27%

95% 97% 99% 100%

95% 97% 99% 100%

60% 62% 65% 68%

50% 52% 55% 58%

90% 92% 95% 98%

1760% 5280% 5280% 5280%

100% 100% 100% 100%

409600% 819200% 1638400% 3276800%

Table DESN3 Correspondence Between System-Level Design Requirements and SolutionsRequirement Solution Explanation of the Correspondence

Design block reuse System-level component reuse The larger and more complex the components that can be reused, the greater the expected overall design reuse

On-chip network design methods Standardized communication structures and interfaces support reuse: IPs with standardized interfaces can be easily integrated and exchanged, and communication structures reused

Available platforms Multi-fabric implementation planning (AMS, RF, MEMS, …)

Enables integration of different fabrics on same die or in same package (SIP); hence, enables reduced number of platforms

Platforms supported Automated interface synthesis Automated interface synthesis is one building block to an integrated synthesis flow for whole platforms.

Automated HW-SW co-design and verification

Required for integrated, platform-based system development

Accuracy of high level estimates Improved system-level power estimation techniques

System-level power estimation needs to match progress in high-level area and performance estimation

Chip-package co-design methods Packaging effects, e.g., on timing, must be accounted for in higher-level estimations

SOC reconfigurability On-chip network design methods To provide flexible, reconfigurable communication structures

Analog automation Multi-fabric implementation planning (AMS, RF, MEMS, …)

Multi-fabric implementation planning for AMS and RF components are a building block to analog automation

Modeling methodology, description languages, simulation environments

Mixed-Signal/RF verification As in digital design, verification is an increasingly critical and time-consuming activity in the design flow

ADD HW offers multi-cores that have to be exploited by SW

Parallel Processing Due to thermal and power limitations further performance increases have to be realized with multi-core systems.

ADD Reduce SW verification effort Intelligent Testbench SW simulation, formal verification and automated testbenches for SW will reduce the verification effort for embedded software and enhance quality.

ADD Productivity increase required for SW since SW cost >> 50% of total system cost

Concurrent Software Infrastructure A set of tools that allow concurrent software development and debug

ADD Increase SW execution performance Heterogeneous Parallel Processing Parallel Processing using different application specific processors for each of the separate functions in the system

ADD SW Productivity increase required Transactional Memory A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing. It functions as an alternative to lock-based synchronization

ADD Productivity increase required for HW/SW co-design

System Design Automation (SDA) True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains

ADD Reduce verification effort Executable Specification Specifications written in a formal language allow automated verification process starting early in the design process and at high abstraction levels without the need to code several new verification models. This enables a design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.

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Table DESN3 Correspondence Between System-Level Design Requirements and SolutionsRequirement Solution Explanation of the Correspondence

Design block reuse System-level component reuse The larger and more complex the components that can be reused, the greater the expected overall design reuse

On-chip network design methods Standardized communication structures and interfaces support reuse: IPs with standardized interfaces can be easily integrated and exchanged, and communication structures reused

Available platforms Multi-fabric implementation planning (AMS, RF, MEMS, …)

Enables integration of different fabrics on same die or in same package (SIP); hence, enables reduced number of platforms

Platforms supported Automated interface synthesis Automated interface synthesis is one building block to an integrated synthesis flow for whole platforms.

Automated HW-SW co-design and verification

Required for integrated, platform-based system development

Accuracy of high level estimates Improved system-level power estimation techniques

System-level power estimation needs to match progress in high-level area and performance estimation

Chip-package co-design methods Packaging effects, e.g., on timing, must be accounted for in higher-level estimations

SOC reconfigurability On-chip network design methods To provide flexible, reconfigurable communication structures

Analog automation Multi-fabric implementation planning (AMS, RF, MEMS, …)

Multi-fabric implementation planning for AMS and RF components are a building block to analog automation

Modeling methodology, description languages, simulation environments

Mixed-Signal/RF verification As in digital design, verification is an increasingly critical and time-consuming activity in the design flow

ADD HW offers multi-cores that have to be exploited by SW

Parallel Processing Due to thermal and power limitations further performance increases have to be realized with multi-core systems.

ADD Reduce SW verification effort Intelligent Testbench SW simulation, formal verification and automated testbenches for SW will reduce the verification effort for embedded software and enhance quality.

ADD Productivity increase required for SW since SW cost >> 50% of total system cost

Concurrent Software Infrastructure A set of tools that allow concurrent software development and debug

ADD Increase SW execution performance Heterogeneous Parallel Processing Parallel Processing using different application specific processors for each of the separate functions in the system

ADD SW Productivity increase required Transactional Memory A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing. It functions as an alternative to lock-based synchronization

ADD Productivity increase required for HW/SW co-design

System Design Automation (SDA) True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains

ADD Reduce verification effort Executable Specification Specifications written in a formal language allow automated verification process starting early in the design process and at high abstraction levels without the need to code several new verification models. This enables a design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.

Table DESN4 Logical/Circuit/Physical Design Technology Requirements

Year of Production 2007 2008 2009 2010

7% 11% 15% 17%

Parameter uncertainty:%-effect (on signoff delay) 6% 8% 10% 11%

4 5 6 6

Circuit families: # of families in a single design 3 3 4 4

Synthesized analog content: % of total design analog content 15% 16% 17% 18%

Full-chip leakage (normalized to full-chip leakage power dissipation in 2007) 1 1.5 2 2.5

Asynchronous global signaling:% of a design driven by handshake clocking

Simultaneous analysis objectives:# of objectives during optimization

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2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

19% 20% 22% 23% 25% 30% 30% 30% 35% 40% 43% 45%

11% 12% 14% 15% 18% 20% 20% 20% 22% 25% 26% 28%

6 6 7 8 8 8 8 8 8 8 8 8

4 4 4 4 4 4 4 4 4 4 4 4

19% 20% 23% 25% 28% 30% 35% 40% 45% 50% 55% 60%

2.75 3 3.5 4 6 8 8 8 8 8 8 8

Table DESN5 Correspondence Between Logical/Circuit/Physical Requirements and SolutionsRequirement Solution Explanation of the Correspondence

Asynchronous global signaling Automated handshake logic/circuit tools Departure from fully synchronous design paradigm needed for power reduction, latency insensitivity, variation-tolerance

% of a design (SOC)

Parameter uncertainty Synthesis and timing analysis accounting for variability Tools that account for process uncertainty, and resulting parametric uncertainty, will reduce guardbanding and increase chip yields

%-effect (on signoff delay)

Simultaneous analysis objectives Circuit/layout enhancement accounting for variability Optimizations which consider parametric uncertainty

Simultaneous analysis objectives Power management analysis and logic insertion SOI SOC tools Requires budgeting of area/power/timing constraints

Simultaneous analysis objectives Cost-driven implementation flow Cost is an engineering parameter that affects turnaround times. Silicon cost no longer dominant; test and manufacturing costs increase emphasis on adaptive, self-repairing circuits

Circuit families Non-static logic implementation Non-static implementations help improving different chip parameters

# of circuit families in a single design

Synthesized analog content Analog synthesis (circuit/layout) Allows for larger portions of a chip to be analog

Full-chip leakage Macro block/chip leakage analysis Enables accurate leakage predictions

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Table DESN5 Correspondence Between Logical/Circuit/Physical Requirements and SolutionsRequirement Solution Explanation of the Correspondence

Asynchronous global signaling Automated handshake logic/circuit tools Departure from fully synchronous design paradigm needed for power reduction, latency insensitivity, variation-tolerance

% of a design (SOC)

Parameter uncertainty Synthesis and timing analysis accounting for variability Tools that account for process uncertainty, and resulting parametric uncertainty, will reduce guardbanding and increase chip yields

%-effect (on signoff delay)

Simultaneous analysis objectives Circuit/layout enhancement accounting for variability Optimizations which consider parametric uncertainty

Simultaneous analysis objectives Power management analysis and logic insertion SOI SOC tools Requires budgeting of area/power/timing constraints

Simultaneous analysis objectives Cost-driven implementation flow Cost is an engineering parameter that affects turnaround times. Silicon cost no longer dominant; test and manufacturing costs increase emphasis on adaptive, self-repairing circuits

Circuit families Non-static logic implementation Non-static implementations help improving different chip parameters

# of circuit families in a single design

Synthesized analog content Analog synthesis (circuit/layout) Allows for larger portions of a chip to be analog

Full-chip leakage Macro block/chip leakage analysis Enables accurate leakage predictions

Table DESN6 Design Verification Requirements


Productivity

7.9 10.3 13.5 17.6

Methodology

4.7 7.1 9.4 11.8

11.6 13.1 14.7 16.3

Portion of the design specification formalized for verifiability (%) 13.8 17.5 21.3 25

Bugs

8 7 7 7

62 68 74 79

Reuse

73.9 70.8 67.8 64.7

15.5 18.3 21.1 23.8

Functional coverage

46.5 49.7 52.9 56.2

1294 1608 1922 2235

Design size verifiable by 1 engineer-year (in millions of transistors - based on an SOC design and a 10-person engineering team) [1]

Design errors exposed using formal or semi-formal verification (%, versus simulation)

Effort spent on system-level verification: software, hardware and electrical effects (%)

Escape rate: bugs found after first tapeout (per each 100K lines of design code)

Bugs found after system integration until tapeout (per each 100K lines of design code)

Portion of the verification infrastructure (e.g., test beds, coverage, checkers) which is newly developed (versus reused components and acquired IP) (%) [2]

Portion of the verification infrastructure which is acquired from third parties (i.e., verification IP) (%) [2]

Portion of design for which verification quality is evaluated through functional coverage (%)

Coverage goal density (expressed as number of coverage goals for each million transistors of the design) [3]

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2011 2012 2013 2014 2015 2016 2017 2018 2019

23.1 30.3 39.8 52.3 69.6 91.8 121 159.7 210.9

14.1 16.5 18.8 21.2 23.5 25.9 28.2 30.6 32.9

17.8 19.4 20.9 22.5 24.1 25.6 27.2 28.8 30.3

28.8 32.5 36.3 40 43.8 47.5 51.3 55 58.8

6 6 6 6 5 5 5 4 4

85 91 97 103 109 115 121 126 132

61.6 58.6 55.5 52.5 49.4 46.4 43.3 40.2 37.2

26.6 29.4 32.1 34.9 37.6 40.4 43.2 45.9 48.7

59.4 62.6 65.9 69.1 72.4 75.6 78.8 82.1 85.3

2549 2863 3176 3490 3804 4118 4431 4745 5059

2020 2021 2022

278.6 368.5 487.6

35.3 37.6 40

31.9 33.4 35

62.5 66.25 70

4 3 3

138 144 150

34.1 31.1 28

51.5 54.2 57

88.5 91.8 95

5373 5686 6000

Table DESN7 Correspondence Between Design Verification Requirements and SolutionsRequirement Solution Explanation of the Correspondence

Productivity of verification tasks Verification methodology centered on verification IPs and reuse

Verification IPs and reuse reduce the amount of new verification development required in a project

Hierarchical hardware verification Structured methodologies improve design team productivity

Reusable methodologies for functional coverage development

Functional coverage is time-consuming, and specific for each distinct design; development of reusability techniques is critical to boosting productivity

Concurrent verification of hardware and software components during development

Advancing the verification of hardware in parallel with that of software components can significantly shorten time-to-market of a product, in contrast to methodologies that begin software verification only after the first hardware prototype

Formal and semi-formal verification centered methodology

Hierarchical hardware verification methodology Enables the decomposition of the system into smaller blocks which are suitable for formal verification

Design development and structure taking into account verifiability

Design for verifiability organizes a design so as to simplify verification; additional verification-specific hardware structures further simplify design-time verification tasks

Methodologies for system-level verification

Verification methodology centered on verification IPs and reuse

Verification IP components enable an early start on system-level verification

Integrated verification of hardware and embedded software and their interface

Directly provides solutions for effective system-level verification

Portion of design specification formalized for verifiability

Design specification formalized for verifiability Formal languages and methodologies to support the formal specification of a design

Escape rate after tapeout Design structure taking into account verifiability Development of hardware structures (checker-like) which can be used to detect and correct a system entering an escaped erroneous configuration after customer shipment

System integration bug rate Analog and mixed-signal verification Limits the bug rate due to analog effects

Simulation and verification solutions for the detection and correction of soft failures and manufacturing faults

Manufacturing faults occurring in post-silicon are detected at system-level integration; techniques to detect and correct electrical and transient defects reduce the effort required to expose and correct these problems.

Hierarchical verification methodology Supports management of complexity through decomposition

Functional coverage Reusable methodologies for functional coverage development

Reusable functional coverage solutions leverage the coverage development effort and boost quality of results

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Table DESN8 Design for Test Technology Requirements


System Driver: Analog/Mixed-signal/RF

All-digital DFT for analog/mixed-signal/RF circuits and systems. 40 45 50 55

% digital circuits in DFT implementations

40 45 50 55

25 30 35 40

System Drivers: MPU/PE/DSP

DFT coverage of digital blocks or subsystems. % blocks with DFT 70 70 70 75

DFT for delay test of critical paths. % paths covered 55 55 60 60

DFT for fault tolerance in logic blocks. 40 40 45 45

% blocks with fault tolerance

System Drivers: Memories

DFT for yield improvement. 85 90 90 90

General SOC/SIP requirements

DFT support for logic and other non-memory circuit repair. 50 60 60 60

% blocks with repair

35 35 40 40

15 15 10 10

DFT efficacy in test volume reduction. Reduction factor 5× 5× 5× 10×

45 45 50 50

Correlation of DFT results with existing specification-based test methods. % results correlated

Availability of fault/defect models for DFT-oriented test methods. % AMS/RF blocks with accepted fault models

DFT reuse for performance calibration, and measurement purposes. % DFT circuits reused

DFT impact on system performance (noise, power, sensitivity, bandwidth, etc.). % performance impact (aggregate figure of merit)

DFT / ATE interface standard, including DFT control via standard test access protocols. % of test interface standardized

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2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

60 60 60 60 80 85 90 90 100 100 100 100

60 60 60 60 80 85 90 90 100 100 100 100

45 50 55 60 65 70 75 80 85 90 95 100

75 75 80 80 85

60 60 70 70 70 85 90 90 95 95 97.5 100

50 50 55 55 60 80 80 90 90 100 100 100

65 70 80 90 100 100 100

90 95 95 95 95 98 98 98 100 100 100 100

70 70 70 80 80 80 90 90 100 100 105 110

60 60 70 70 70 72.5 75

40 45 45 50 50

10 10 10 10 10 5 5 5 5 5 5 5

10× 10× 20× 20× 20× 20× 50× 50× 50× 50× 50× 50×

60 60 70 70 75 90 80 90 100 100 100 100

Table DESN9 Design for Manufacturability Technology Requirements


Normalized mask cost from public and IDM data 1 1.3 1.7

10% 10% 10%

31% 35% 40%

33% 37% 42%

16% 18% 20%

% CD variability 12% 12% 12%

46% 48% 49%

56% 57% 63%

124% 143% 186%

% Vdd variability: % variability seen in on-chip circuits

% Vth variability: doping variability impact on Vth, (minimum size devices, memory)

% Vth variability: includes all sources

% Vth variability: typical size logic devices, all sources

% circuit performance variability circuit comprising gates and wires

% circuit total power variability circuit comprising gates and wires

% circuit leakage power variability circuit comprising gates and wires

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2010 2011 2012 2013 2014 2015 2016 2017 2018

2.3 3 3.9 5.1 6.6 8.7 11.4 14.9 19.6

10% 10% 10% 10% 10% 10% 10% 10% 10%

40% 40% 58% 58% 81% 81% 81% 81% 112%

42% 42% 58% 58% 81% 81% 81% 81% 112%

20% 20% 26% 26% 36% 36% 36% 36% 50%

12% 12% 12% 12% 12% 12% 12% 12% 12%

51% 60% 63% 63% 63% 63% 63% 65% 66%

68% 72% 76% 80% 84% 88% 92% 96% 102%

229% 255% 281% 287% 294% 331% 368% 381% 395%

2019 2020 2021 2022

25.6 33.6 44.2 57.7

10% 10% 10% 10%

112% 112% 112% 112%

112% 112% 112% 112%

50% 50% 50% 50%

12% 12% 12% 12%

69% 69% 71% 73%

110% 121% 130% 140%

360% 325% 477% 628%

Table DESN10 Correspondence Between Design for Manufacturability Requirements and Solutions Requirement Solution Explanation of the Correspondence

Mask cost Tools that account for mask cost in their algorithms Obvious

RDRs (grid-like layouts, no diagonals, etc.) Better manufacturability and yield, less mask complexity

RET tools aware of circuit metrics (timing, power) More effective optimization, fewer design iterations

Statistical leakage analysis and optimization tools Estimation and control of soaring leakage variability

Post-tapeout RET interacting with synthesis, timing, P&R

By interacting with earlier-in-the-flow EDA tools, can more effectively address litho issues

Model-based physical verification Can address litho issues with precision

Model-based physical synthesis Explicit litho model-based approach moves into the physical synthesis toolset

Manufacturing-friendly design rules (hard rules) Reduces mask, manufacturing cost; addresses printability

% Vdd variability seen at on-chip circuits Tools that account for mask cost in their algorithms Obvious









% Vth variability (doping variability impact) Statistical analysis, opt tools and flows (Vdd, T, Vth) Better estimate of variability impact reduces overdesign

% Vth variability Includes all sources Statistical analysis, opt tools and flows (Vdd, T, Vth) Better estimate of variability impact reduces overdesign

Adaptable and redundant circuits Inherent circuit robustness to variability

Statistical leakage analysis and optimization tools Estimation and control of soaring leakage variability.

% CD variability RET tools aware of circuit metrics (timing, power) More effective optimization, fewer design iterations



Statistical leakage analysis and optimization tools Leakage power variability will soar. Statistical leakage tools are critical to estimate and control it.





Manufacturing-friendly design rules (hard rules) Reduces mask, manufacturing cost; addresses printability Circuit performance variability (gates and wires) Router-friendly standard cells

Routing-friendly rules reduce design, mask, and manufacturing complexity

Adaptable and redundant circuits Inherent circuit robustness to variability Circuit power variability (gates and wires) Adaptable and redundant circuits Inherent circuit robustness to variability







Router-friendly standard cells Routing-friendly rules reduce design, mask, and manufacturing complexity

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Table DESN11 Near-term Breakthroughs in Design Technology for AMS

Field of Breakthrough 2007 State-of-the-Art 2008/09 2010/11 Specification, validation, verification

Established AMS Hardware Description Languages

Multi-language support, AMS extension of HW/SW description languages for full system simulation

Complete specification-driven design flow; some specialized formal verification methods

Architectural design Algorithm-oriented design (e.g., with Matlab/Simulink)

Language-based performance evaluation; closer coupling of architectural, block, and circuit level

Synthesizeable AMS description; power-aware HW/SW partitioning extended to AMS systems

Physical mixed A/D and RF design

Procedural layout generation, module generators for a few block types

Module generators for often re-used blocks, design centering, performance estimation

Synthesis: behavior to layout (at least for the most important building blocks)

Parasitics extraction, automated modeling, accelerated simulation

Electromagnetic immunity simulation works but is too complicated for broad usage

2D/3D model-based order reduction for interconnect systems and substrate effects on chip, thermal package modeling

New fault-tolerant circuit architectures, robustness against technology parameter variations; order reduction for all kinds of parasitics and antennas

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Table DESN11 Near-term Breakthroughs in Design Technology for AMS

Field of Breakthrough 2007 State-of-the-Art 2008/09 2010/11 Specification, validation, verification

Established AMS Hardware Description Languages

Multi-language support, AMS extension of HW/SW description languages for full system simulation

Complete specification-driven design flow; some specialized formal verification methods

Architectural design Algorithm-oriented design (e.g., with Matlab/Simulink)

Language-based performance evaluation; closer coupling of architectural, block, and circuit level

Synthesizeable AMS description; power-aware HW/SW partitioning extended to AMS systems

Physical mixed A/D and RF design

Procedural layout generation, module generators for a few block types

Module generators for often re-used blocks, design centering, performance estimation

Synthesis: behavior to layout (at least for the most important building blocks)

Parasitics extraction, automated modeling, accelerated simulation

Electromagnetic immunity simulation works but is too complicated for broad usage

2D/3D model-based order reduction for interconnect systems and substrate effects on chip, thermal package modeling

New fault-tolerant circuit architectures, robustness against technology parameter variations; order reduction for all kinds of parasitics and antennas

Table DESN12 Design Technology Improvements and Impact on Designer Productivity

DT Improvement Year Productivity

Delta

Productivity (Gates/Design-

Year)

Cost of Component

Affected Description of Improvement

None 1990 4K

In-house place and route 1993 +38.9% 5.55K PD

Integration Automated block placement and routing

Engineer 1995 +63.6% 9.09K Chip/circuit/PD

Verification

Engineer can pursue all required tasks to complete a design block, from RTL to GDSII

Reuse—small blocks 1997 +340% 40K Circuit/PD

Verification Blocks from 2,500–74,999 gates

Reuse—large blocks 1999 +38.9% 56K Chip/circuit/PD

Integration Verification

Blocks from 75,000–1M gates

IC implementation suite 2001 +63.6% 91K Chip/circuit/PD

Integration EDA support

Tightly integrated tool set that goes from RTL synthesis to GDSII through IC place and route

RTL functional verification tool suite

2003 +37.5% 125K SW development

Verification

RTL verification tool (“cockpit”) that takes an ES-level description and partitions it into verifiable blocks, then executes verification tools on the blocks, while tracking and reporting code coverage

Transactional Modeling 2005 +60% 200K SW development

Verification

Level above RTL, including both HW and SW design; it consists of a behavioral (where the system function has not been partitioned) and an architectural level (where HW and SW are identified and handed off to design teams)

Very large block reuse 2007 +200% 600K Chip/circuit/PD

Verification Blocks >1M gates; intellectual-property cores

Homogeneous parallel processing

2009 +100% HW

+100% SW 1200K

Chip/circuit/PD Design and Verification

Many identical cores provide specialized processing around a main processor, which allows for performance, power efficiency, and high reuse

Intelligent test bench 2011 37.5% 1650K Chip/circuit/PD

Verification

Like RTL verification tool suite, but also with automation of the Verification Partitioning step

Concurrent software compiler

2013 200% SW 1650K

Chip and Electronic System

Design and Verification

Enables compilation and SW development in highly parallel processing SOCs

Heterogeneous massive parallel processing

2015 +100% HW +100% SW

3300K System Electronic


Each of the specialized cores around the main processor is not identical from the programming and implementation standpoint

Transactional Memory 2017 +100% HW +100% SW



Automates true electronic system design on- and off-chip for the first time, including heterogeneous technologies (Phase 1)

System-level DA 2019 60% HW 38% SW




Executable specification 2021 200% HW +200% SW




Total +264,000%

ORTCINDEX

2007 ITRS Chapters

2008INDEX



Delta


Year)

Cost of Component


None 1990 4K




Verification












Verification



Verification





2009 +100% HW

+100% SW 1200K




Verification



2013 200% SW 1650K





2015 +100% HW +100% SW
















Total +264,000%



Delta


Year)

Cost of Component


None 1990 4K




Verification












Verification



Verification





2009 +100% HW

+100% SW 1200K




Verification



2013 200% SW 1650K





2015 +100% HW +100% SW
















Total +264,000%



Delta


Year)

Cost of Component


None 1990 4K




Verification












Verification



Verification





2009 +100% HW

+100% SW 1200K




Verification



2013 200% SW 1650K





2015 +100% HW +100% SW
















Total +264,000%

Table TST1 Summary of Key Test Drivers, Challenges, and Opportunities

Key Drivers (not in any particular order)

Device trends

Increasing device interface bandwidth (# of signals and data rates)

Increasing device integration (SoC, SiP, MCP, 3D packaging)

Integration of emerging and non-digital CMOS technologies

Complex package electrical and mechanical characteristics

Device characteristics beyond one sided stimulus/response model

Multiple I/O types and power supplies on same device

Multiple digital I/O types on same device

Increasing test process complexity

Device customization during the test process

“Distributed test” to maintain cost scaling

Feedback data for tuning manufacturing

Dynamic test flows via “Adaptive Test”

Higher order dimensionality of test conditions

Continued economic scaling of test

Physical limits of test parallelism

Managing (logic) test data and feedback data volume

Defining an effective limit for performance difference for HVM ATE versus DUT

Managing interface hardware and (test) socket costs

Trade-off between the cost of test and the cost of quality

Multiple insertions due to system test and BIST

Difficult Challenges (in order of priority)

Test for yield learning Critically essential for fab process and device learning below optical device dimensions

Detecting Systemic Defects Testing for local non-uniformities, not just hard defects

Detecting symptoms and effects of line width variations, finite dopant distributions, systemic process defects

Screening for reliability Implementation challenges and efficacies of burn-in, IDDQ, and Vstress

Erratic, non deterministic, and intermittent device behavior

Potential yield losses

Tester inaccuracies (timing, voltage, current, temperature control, etc)

Over testing (e.g., delay faults on non-functional paths)

Mechanical damage during the testing process

Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise

Some IDDQ-only failures

Faulty repairs of normally repairable circuits

Decisions made on overly aggressive statistical post-processing

Future Opportunities (not in any order)

Test program automation (not ATPG) Automation of generation of entire test programs for ATE

Simulation and modeling Seamless Integration of simulation and modeling of test interface hardware and instrumentation into the device design process

Convergence of test and system reliability solutions

Re-use and fungibility of solutions between test (DFT), device, and system reliability (error detection, reporting, correction)

ATE—automatic test equipment ATPG—automatic test pattern generation BIST—built-in self test HVM—high volume manufacturing MCP—multi-chip packaging MEMs—micro-electromechanical systems

ORTCINDEX

2007 ITRS Chapters

2008INDEX

Table TST1 Summary of Key Test Drivers, Challenges, and Opportunities

Key Drivers (not in any particular order)

Device trends

Increasing device interface bandwidth (# of signals and data rates)

Increasing device integration (SoC, SiP, MCP, 3D packaging)

Integration of emerging and non-digital CMOS technologies

Complex package electrical and mechanical characteristics

Device characteristics beyond one sided stimulus/response model

Multiple I/O types and power supplies on same device

Multiple digital I/O types on same device

Increasing test process complexity

Device customization during the test process

“Distributed test” to maintain cost scaling

Feedback data for tuning manufacturing

Dynamic test flows via “Adaptive Test”

Higher order dimensionality of test conditions

Continued economic scaling of test

Physical limits of test parallelism

Managing (logic) test data and feedback data volume

Defining an effective limit for performance difference for HVM ATE versus DUT

Managing interface hardware and (test) socket costs

Trade-off between the cost of test and the cost of quality

Multiple insertions due to system test and BIST

Difficult Challenges (in order of priority)

Test for yield learning Critically essential for fab process and device learning below optical device dimensions

Detecting Systemic Defects Testing for local non-uniformities, not just hard defects

Detecting symptoms and effects of line width variations, finite dopant distributions, systemic process defects

Screening for reliability Implementation challenges and efficacies of burn-in, IDDQ, and Vstress

Erratic, non deterministic, and intermittent device behavior

Potential yield losses

Tester inaccuracies (timing, voltage, current, temperature control, etc)

Over testing (e.g., delay faults on non-functional paths)

Mechanical damage during the testing process

Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise

Some IDDQ-only failures

Faulty repairs of normally repairable circuits

Decisions made on overly aggressive statistical post-processing

Future Opportunities (not in any order)

Test program automation (not ATPG) Automation of generation of entire test programs for ATE

Simulation and modeling Seamless Integration of simulation and modeling of test interface hardware and instrumentation into the device design process

Convergence of test and system reliability solutions

Re-use and fungibility of solutions between test (DFT), device, and system reliability (error detection, reporting, correction)

ATE—automatic test equipment ATPG—automatic test pattern generation BIST—built-in self test HVM—high volume manufacturing MCP—multi-chip packaging MEMs—micro-electromechanical systems

document.xls

2008_TST2

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

High Performance MPU, ASIC

Wafer test Number of sites 8 16 16 16 16 32 32 32 64 64 64 64 64 64 64 64


Package test Number of sites 4 8 8 8 8 16 16 16 32 32 32 32 32 32 32 32


SoC


Package test Number of sites 4 4 4 4 4 8 8 8 16 16 32 32 32 32 32 32Low Performance - MCU, MPU, ASIC





Mixed-signal & Communications


wafer test Number of sites 8 16 16 32 32 32 32 32 64 64 64 64 64 128 128 128


Packaged Test Number of sites 4 8 8 16 16 16 16 16 32 32 32 32 32 32 32 32Commodity DRAM Memory




Package test Number of sites 256 256 256 512 512 512 1024 1024 1024 1024 1024 1024 1024 1024 1024 1024Commodity Flash Memory

Wafer test Number of sites256 512 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000 1000

Wafer test Number of sites768 768 768 1024 1024 1024 1536 1536 1536 2048 2048 2048 2048 2048 2048 2048

Package test Number of sites512 512 512 1024 1024 1024 1024 1024 2048 2048 2048 2048 2048 2048 2048 2048

Package test Number of sites700 700 700 700 1024 1024 1024 1024 1024 2048 2048 2048 2048 2048 2048 2048

RF




document.xls

2007_TST3

Table TST3 System on Chip Test Requirements

Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

Embedded Cores: Logic

Random Pattern Logic BIST

Area Investment beyond Scan (%) [1] 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1 3.1

Compressed Deterministic Pattern Test

Area Investment beyond Scan (%) [2] 1.1 1.1 1.2 1.3 1.4 1.5 1.6 1.6 1.7 1.8 1.9 2 2.1 2.1 2.1 2.1

SA+T SA+T SA+T +SD +SD +SD +SDX +SDX +SDX +NDF +NDF +NDF +NDF +NDF +NDF +NDF

Ratio of Overall Pattern Count per Gate to Stuck-at Fault Pattern [3] X 5 X 5 X 5 X 15 X 15 X 15 X 30 X 30 X 30 X 60 X 60 X 60 X 120 X 120 X 120 X 240

Estimation & Requirements for SoC Test Pattern (without Core-Parallel Test)

SAF Pattern Count per Chip (k) 11 14 17 22 28 34 43 56 70 90 109 134 170 222 258 361

Overall Pattern Count per Chip (k) 53 68 85 334 416 510 1,283 1,665 2,085 5,370 6,510 8,040 20,370 26,640 30,990 86,700

Ratio of Test Application Time per Chip to 2007's [4] 1.00 1.29 1.62 4.24 5.29 6.48 10.81 14.03 17.57 30.26 36.69 45.31 76.68 100.28 116.66 217.29

1.00 0.96 0.93 2.00 2.00 1.90 2.65 2.65 2.65 3.55 3.55 3.55 4.74 4.74 3.67 5.04

Required Test Data Volume Compression Ratio [6] 30 51 84 202 314 496 746 1,257 1,972 3,269 4,805 7,329 11,761 20,116 35,180 66,721

DFT Methodology for SoC Level Design

DRC DRC DRC +TA +TA +TA +TA +TA +TA +SYN +SYN +SYN +SYN +SYN +SYN +SYN

AH AH AH PA PA PA LA LA LA GA GA GA GA GA GA GA

PA PA PA +NA +NA +NA +NAX +NAX +NAX +NAX +NAX +NAX +NAX +NAX +NAX +NAX

Embedded cores: Memory (SRAM)

RC RC RC RCM RCM RCM M M M M M M M M M M

Area Investment of BIST/BISR/BISD [8] (Kgates/Mbits) 35 35 35 35 35 35 35 35 35 35 35 35 35

Standardized High-Speed Memory Test I/F [9] (S: Some, P: Partially, F: Fully) S S S P P P P P P F F F F F F F

Core Integration

Standardization of I/F for Reusable IP Cores [10] (P: Partial Use, F: Full Use) P P P P P P F F F F F F F F F F

LP LP LP LF LF LF F F F F F F F F F F

AH AH AH L+M L+M L+M +IO +IO +IO +A +A +A +A +A +A +A

F F F PA PA PA PA PA PA FA FA FA FA FA FA FA

SoC Manufacturing

Systematic Hierarchical Diagnosis (L: Logic, M: Memory, I: Interface) L L L +M +M +M +I +I +I +I +I +I +I +I +I +I

C C C +D +D +D +CT +CT +CT +CT +TRF +TRF +TRF +TRF +TRF +TRF

ATE ATE ATE +DFT +DFT +DFT +PFA +PFA +PFA +PFA +PFA +PFA +PFA +PFA +PFA +PFA

SI(B) SI(B) SI(B) +SI(G) +SI(G) +SI(G) +SI(G) +SI(G) +SI(G) +AD +AD +AD +AD +AD +AD +AD

Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Interim solutions are known uManufacturable solutions are NOT known

Definitions for System on Chip Test Requirements Table: [1] Area investment of random pattern logic BIST consists of BIST controller and test points.[2] Area investment of compressed deterministic pattern test consists of controller and test points.[3] This shows the number of pattern count (number of captures), which corresponds to various fault models. [4] This is proportional to the overall pattern count and inversely proportional to internal scan data rate.[5] We set the requirement that test application time per gate should be stable.[6] The size of ATE vector memory is assumed to increase as fast as DRAM bit size increases.[7] Growing number of row & column spares, and both divided and shared spares for segments in the future.[8] The current BISR for two dimensional repair is limited to a few row and column spares.[9] Common interface of test logic embedded in memory hard macro for high-speed testing.[10] IEEE1500 is an example. Standardization of I/F for re-usable IP Cores.

[12] A method to obtain overall test quality measure of SoC considering all cores; logic, memory and analog.

Supported Fault Models by ATPG for Overall Test (SA+T: Stuck-at & Transition, SD: Small Delay, SDX: Extended Small Delay, NDF: New Defect-based Fault Model)

Ratio of Test Application Time per Gate to 2007's = Required Reduction Ratio [5]

DFT method in High Level Design Phase (DRC: DFT Design Rule Check, TA: Testability Analysis and Fault Coverage Estimation, SYN: Test Synthesis)

Application of BISR for Logic Cores (AH: Ad hoc Method, PA: Partially Automated Method, LA: Limited Use of Automated Method, GA: General Use of Automated Method)

DFT/ATPG Approach to Reduce Yield-Loss (PA: Power-Aware DFT/ATPG, NA: Noise Aware DFT/ATPG, NAX: Extended Noise-Aware DFT/ATPG)

Repairing Mechanism of Memory Cells to improve Yield [7] ( RC: BISR/BISD for a few Row & Col R/D, RCM: for more Row & Col R/D, M: for More Sophisticated R/D)

u35 u35 u35

Standardization of DFT-ATE I/F [11] (LP: Limited Use of Partial Information, LF: Limited Use of Full Information, F: General Use of Full Information)

SoC Level Fault Coverage [12] (AH: Adhoc, L: Logic, M: Memory, IO: I/O, A: Analog)

Inter-Core/Core-Interface Test (F: Complemental Functional Test; PA: Partially Automated ; FA: Fully Automated)

Supported Defect Type for Fault Diagnosis (C: Conventional (SAF, TF, BF), D: Delay Fault Model Considering Defective Delay Size, CT: Cross-talk, TRF: Transient Response Fault)

Standardized Diagnosis Interface/Data in the diagnosis flow (ATE: Tester Log, DFT: DFT Method, PFA: Physical Failure Analysis)

Volume Diagnosis Data Base (SI: Collection and Storing Defect Information (B: Bad sample, G: Good sample), AD: Automated SoC Diagnosis)

[11] STIL (Test Interface Language, IEEE1450.x) is an example. I/F should include not only test vectors, but also parametric factors.

document.xls

2007_TST4

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

Device Characteristics

# of Transistors (M) - CPU 386 486 613 772 973 1,226 1,545 1,946 2,452 3,090 3,893 4,905 6,181 7,788 9,812 12,364# of Transistors (M) - Consumer 254 344 450 608 773 926 1,225 1,609 2,031 2,633 3,205 3,973 5,049 6,623 7,714 10,816Chip size at production mm^2 - CPU 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140 140Chip size at production mm^2 - Consumer 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64non differential data rate (GT/s) 2 2 2 2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2 3.2Internal Scan data rate (MHz) 50 50 50 75 75 75 113 113 113 169 169 169 253 253 253 380Single ended External Scan Data rate (Mb/s) 400 400 800 800 800 800 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200Differential External Scan Data rate (Gb/s) 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5Vdd 0.8–1.1 0.8–1.0 0.8–1.0 0.7–1.0 0.7–1.0 0.7–0.9 0.6–0.9 0.6–0.9 0.6–0.8 0.5–0.8 0.5–0.7 0.5–0.7 0.4–0.7 0.4–0.6 0.4–0.6 0.4–0.6

CPU

CPU total cores 4 4 5 6 6 7 8 9 10 11 12 14 16 17 20 22CPU Unique cores 1 1 2 2 2 2 2 4 4 4 4 4 6 6 6 6Percentage of Memory transistors 65% 65% 70% 70% 70% 70% 70% 75% 75% 75% 75% 75% 80% 80% 80% 80%Percentage of random logic transistors 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%Percentage of core transistors 30% 30% 25% 25% 25% 25% 25% 20% 20% 20% 20% 20% 15% 15% 15% 15%Transistors per Flip Flop 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26Supplies per DUT 1–6 1–6 1–6 1–4 1–4 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3Number of patterns for high coverage SAF only 6572 7003 8744 9524 10456 11571 12911 17828 20193 23025 26426 30524 37458 43706 51278 60479Total # of bits scanned in (same as scan out) Gb 4 6 11 14 19 24 32 69 92 123 167 228 353 490 685 965

Maximum power consumption at test (W) 200 200 300 300 300 300 300 300 300 300 300 300 300 300 300 300

Maximum power consumption at test (W) - Server 300 300 300 300 300 300 300 400 400 400 400 400 400 400 400 400

Number of logic gates (M) 34 43 46 58 73 92 116 122 153 193 243 307 309 389 491 618

Consumer

Consumer total cores 32 44 58 79 101 126 161 212 268 348 424 526 669 878 1023 1435Consumer Unique cores 4 6 7 10 13 16 20 27 34 44 53 66 84 110 128 179Percentage of Memory transistors 83% 84% 85% 85% 86% 86% 86% 86% 86% 86% 86% 87% 87% 87% 87% 87%Percentage of random logic transistors 2% 2% 1% 1% 1% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0%Percentage of core transistors 15% 14% 14% 14% 13% 14% 14% 14% 14% 14% 14% 13% 13% 13% 13% 13%Transistors per Flip Flop 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26Supplies per DUT 1–6 1–6 1–6 1–4 1–4 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3 1–3Number of patterns for high coverage SAF only 10,795 13,760 16,875 22,800 27,055 32,410 42,875 56,315 71,085 92,155 112,175 129,123 164,093 215,248 250,705 351,520Total # of bits scanned in (same as scan out) Gb 2 3 3 5 8 7 13 22 36 60 89 118 191 328 445 875

Number of logic gates (M) 11 14 17 23 27 32 43 56 71 92 112 129 164 215 251 352

Table TST5 Vector Multipliers

Vector Multiplier

Fault Type Min MaxBF (Bridging Fault) 1.3 1.3

TF (Transition Fault) 3 5SD (Small Delay) 2 40

ORTCINDEX

2007 ITRS Chapters

2008INDEX

document.xls

2008_TST6

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

DRAM Characteristics

Capacity (Gbits)

R&D 8 8 16 16 16 32 32 32 64 64 64 128 128 128 256 256

Mass production 2 2 4 4 4 8 8 8 16 16 16 32 32 32 64 64

Mass production I/O data rate (Gb/s) 1.1 1.3 1.3 1.6 1.6 2.1 2.7 2.7 3.2 3.2 4.3 5.3 5.4 6.4 6.4 8.5

Performance I/O data rate (Gb/s) 1.9 2.4 2.4 2.9 2.9 3.8 4.8 4.8 5.8 5.8 7.7 9.6 9.6 11.5 11.5 15.4

Mass production I/O width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Mass Production CLK rate (GHz) 0.5 0.7 0.7 0.8 0.8 1.1 1.3 1.3 1.6 1.6 2.1 2.7 2.7 3.2 3.2 4.3

NAND Characteristics

Capacity (Gbits)

R&D 64 64 128 128 128 256 256 256 512 512 512 1024 1024 1024 2048 2048

Mass production 16 16 32 32 32 64 64 64 128 128 128 256 256 256 512 512

Maximum I/O data rate (Gb/s) 0.05 0.05 0.05 0.066 0.066 0.1 0.1 0.1 0.1 0.133 0.133 0.133 0.133 0.266 0.266 0.266


Data width (bits) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Power supply voltage range 1.5–5.5 1.5–3.5 1.5–3.5 1.5–3.5 1.5–3.5 1.5–3.5 1.5–3.5 1.0–3.5 1.0–3.5 1.0–3.5 1.0–3.5 1.0–3.5 1.0–3.5 1.0–3.5 1.0–3.5 1.0–3.5

Power supplies per device 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Maximum current (MA) 35 35 35 35 35 35 35 35 50 50 50 50 50 50 50 50

Tester channels per device 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24

NOR Characteristics

Capacity (Gbits)

R&D 4 4 8 8 8 16 16 16 32 32 32 64 64 64 128 128

Mass production 1 1 2 2 2 4 4 4 8 8 8 16 16 16 32 32


Data width (bits) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

Power supply voltage range 1.0–5.5 1.0–5.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5 0.9–3.5

Power supplies per device 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Maximum current (MA) 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150

Tester channels per test site 72 72 72 72 72 72 72 72 72 72 72 72 72 72

Embedded DRAM

Capacity (Mbits) 256 512 512 512 1024 1024 1024 2048 2048 2048 4096 4096 4096 4096 4096 8192DFT BIST/BISR

Embedded Flash

Capacity (Mbits) 64 128 128 128 256 256 256 512 512 512 1023 1024 1024 1024 2048 2048DFT BIST/BIST/DAT

Embedded SRAM

Capacity (Mbits) 0.5 1 1 1 2 2 2 4 4 4 8 8 8 16 16 16

DFT BIST/BISR

document.xls

2008_TST7

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

Low Frequency Waveform [Note 1]

BW (MHz) 50 75 75 75 100 100 100 100 100 100 100 100 100 100 100 100

BW-max (MHz) 120 120 120 320 320 320 320 320 320 320 320 320 320 320 320 320

BW-center (MHz) [Note 2] 45 45 45 80 80 80 80 80 80 80 80 80 80 80 80 80

Sample rate (MS/s) Moving from Nyquist sample rates to over/under sampling sources/digitizers

Sample rate (MS/s) Nyquist sample rates or higher for sources/digitizers

Resolution (bits) DSP computation to 24 bits, effective number of bits limited by noise floor

Noise floor (dB/RT Hz) -155 -160 -160 -160 -165 -165 -165 -165 -165 -165 -165 -165 -165 -165 -165 -165

Noise floor-Max (dB/RT Hz) [Note 3] -160 -160 -160 -160 -165 -165 -165 -165 -165 -165 -165 -165 -165 -165 -165 -165

Noise floor-mid (dB/RT Hz) [Note 4] -145 -145 -155 -155 -155 -155 -155 -155 -155 -155 -155 -155 -155 -155 -155 -155

Very High Frequency Waveform Source [Note 5]

Level V (pk–pk) 4 4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4

Accuracy (±) 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50%

BW (GHz) 1.6 1.9 2.25 2.7 2.7 3 3 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75

BW (GHz) 2 2 4 4 4 4 5 5 5 5 5 5 5 5 5 5

Sample rate (GS/s) 6.4 7.6 9 10.8 11 12 12 15 15 15 15 15 15 15 15 15

Sample rate (GS/s) 6.4 6.6 10 10 10 10 12 12 12 12 12 12 12 12 12 12

Resolution (bits) AWG/Sine† 8-10 8-10 8-10 8-10 8-10 10-12 10-12 10-12 10-12 10-12 10-12 10-12 10-12 10-12 10-12 10-12

Resolution (bits) AWG/Sine† 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10 8-10


Very High Frequency Waveform Digitizer [Note 6]

Level V (pk–pk) 4 4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4

Accuracy (±) 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50%

BW (GHz) (under sampled) 9.2 10.8 10.8 12.5 12.5 15 15 15 15 15 15 15 15 15 15 15

Sample rate (GS/s) 0.4 0.4 0.4 0.4 0.4 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6

Min resolution (bits) 12 12 12 12 12 14 14 14 14 14 14 14 14 14 14 14


Time Measurement

Jitter measurement (ps RMS) Will be driven by high-speed serial communication ports

Frequency measurement (MHz) Will be driven by high-performance ASIC clock rates

Single shot time capability (ps) Will be driven by high-speed serial communication ports

document.xls

2008_TST8


Leading Edge

Carrier Frequency (GHz) [1] 18 18 22 22 60 77 77 95 95 95 95 95 95 95 95 95

Modulation RF BW (MHz) [2] 80 528 528 528 528 528 528 528 528 528 528 528 1000 1000 1000 1000

High Volume

Carrier Frequency (GHz) 6 8 12 12 22 22 36 36 36 36 36 36 36 36 36 36

Carrier Frequency (GHz) [1] 6 8 12 12 22 22 36 36 36 36 36 36 36 36 36 36

Modulation RF BW (MHz) 20 40 80 528 528 528 528 528 528 528 528 528 528 528 1000 1000

Amplitude Accuracy (dB) <0.8 <0.6 <0.5 <0.5 <0.5 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.125 <0.125 <0.125 <0.125

Amplitude Accuracy (dB) <0.8 <0.6 <0.5 <0.5 <0.5 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.125 <0.125 <0.125 <0.125

ACLR (dB) 65 65 70 72 72 72 75 75 80 80 80 85 85 85 85 85

Number of RF Ports per Device <9 <12 <16 <20 <24 <20 <18 <16 <16 <16 <16 <16 <16 <16 <16 <16

Phase Noise (dBc/Hz @ 100k offset) -125 -130 -135 -140 -142 -145 -148 -150 -150 -150 -152 -152 -152 -152 -152 -152

Phase Noise (dBc/Hz @ 100k offset) -125 -130 -135 -140 -142 -145 -148 -150 -150 -150 -152 -152 -152 -152 -152 -152

Error Vector Magnitude 3G/4G [3] 1-2% 1-2% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5%

OIP3 (dBm) [4] 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30

IIP3 (dBm) [4] 40 50 60 60 60 60 60 60 60 60 60 60 60 60 60 60




document.xls

2007_TST9


Clock input frequency (MHz) 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400 400Off-chip data frequency (MHz) 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75 75Power dissipation (W per DUT) 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600Power Supply Voltage Range (V)

0.5–2.5 0.5–2.5 0.5–2.5 0.5–2.5 0.5-2.5 0.5–2.5 0.5–2.5 0.5–2.5 0.5–2.5 0.5–2.5 0.5–2.5 0.4–2.5 0.4–2.5 0.4–2.5 0.4–2.5 0.4–2.5 Low-end microcontroller 0.7–10.0 0.7–10.0 0.7–10.0 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10 0.5–10

Mixed-signal 0.5–500 0.5–500 0.5–500 0.5–500 0.5–500 0.5–500 0.5–500 0.5–500 0.5–1000 0.5–1000 0.5–1000 0.5–1000 0.5–1000 0.5–1000 0.5–1000 0.5–1000Maximum Number of Signal I/O

High-performance ASIC 384 384 384 384 384 384 384 384 384 384 384 384 384 384 384 384

128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 Commodity memory 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72Maximum Current (A)

High-performance microprocessor 450 450 450 450 450 450 450 450 450 450 450 450 450 450 450 450 High-performance graphics processor 100 150 200 200 200 200 200 200 200 200 200 200 200 200 200 200 Mixed-signal 20 20 20 30 30 30 30 30 30 30 30 30 30 30 30 30Burn-in Socket

Pin count 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 3000 Pitch (mm) 0.3 0.3 0.3 0.2 0.2 0.2 0.2 0.2 0.1 0.1 0.1 0.08 0.08 0.08 0.08 0.08 Power consumption (A/Pin) 3 4 4 5 5 5 5 5 5 6 6 6 6 6 6 6Wafer Level Burn-In

Maximum burn-in temperature (ºC) 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3 175±3Pad Layout – Linear

Minimum pad pitch (μm) 65 65 65 65 65 65 65 65 50 50 50 50 50 50 50 50 Minimum pad size (μm) 50 50 50 50 50 50 50 50 40 40 40 40 40 40 40 40 Maximum number of probes 70k 70k 70k 70k 70k 70k 70k 70k 140k 140k 140k 140k 140k 140k 140k 140kPad Layout – Periphery, Area Array

Minimum pad pitch (μm) *1 100 80 80 80 80 80 80 80 60 60 60 60 60 60 60 60 Minimum pad size (μm) 40 35 35 35 35 30 30 30 25 25 25 25 25 25 25 25 Maximum number of probes 150k 150k 150k 150k 150k 150k 150k 150k 300k 300k 300k 300k 300k 300k 300k 300k

10 10 10 20 20 20 20 20 20 20 20 20 20 20 20 20

32 64 64 64 64 64 64 64 128 128 128 256 256 256 256 256

High-performance ASIC / microprocessor / graphics processor

High-performance microprocessor / graphics processor / mixed-signal

Power consumption (W/DUT – Low-end microcontroller, DFT/BIST SOC *2)

Vector memory depth (M vectors – DFT/BIST SOC *2)

Table TST10 Test Handler and Prober Difficult Challenges

High Power Handler

Temperature control and temperature rise control due to high power densities during test

Continuous lot processing (lot cascading), auto-retest, asynchronous device socketing with low-conversion times Better ESD control as products are more sensitive to ESD and on-die protection circuitry increases cost.

Lower stress socketing, low-cost change kits, higher I/O count for new package technologies

Package heat lids change thermal characteristics of device and hander

Multi-site handling capability for short test time devices (1–7 seconds)

Medium Power Hander

Support for stacked die packaging and thin die packaging

Wide range tri-temperature soak requirements (-45ºC to 150ºC) increases system complexity

Continuous lot processing (lot cascading), auto-retest, low conversion times, asynchronous operation

Shielding issues associated with high frequency testing (>10 GHz)

Low Power Handler

A wide variety of package sizes, thicknesses, and ball pitches requires kitless handlers with thin-die handling capability

Package ball-to-package edge gap decreases from 0.6 mm to 0 mm require new handling and socketing methods

Parallelism at greater than x128 drives thermal control and alignment challenges

Prober

Consistent and low thermal resistance across chuck is required to improve temperature control of device under test

Heat dissipation of >100 Watts at > 85ºC is a configuration gap in the prober industry

Advances in probe card technology require a new optical alignment methodology

ORTCINDEX

2007 ITRS Chapters

2008INDEX

Table TST10 Test Handler and Prober Difficult Challenges

High Power Handler

Temperature control and temperature rise control due to high power densities during test

Continuous lot processing (lot cascading), auto-retest, asynchronous device socketing with low-conversion times Better ESD control as products are more sensitive to ESD and on-die protection circuitry increases cost.

Lower stress socketing, low-cost change kits, higher I/O count for new package technologies

Package heat lids change thermal characteristics of device and hander

Multi-site handling capability for short test time devices (1–7 seconds)

Medium Power Hander

Support for stacked die packaging and thin die packaging

Wide range tri-temperature soak requirements (-45ºC to 150ºC) increases system complexity

Continuous lot processing (lot cascading), auto-retest, low conversion times, asynchronous operation

Shielding issues associated with high frequency testing (>10 GHz)

Low Power Handler

A wide variety of package sizes, thicknesses, and ball pitches requires kitless handlers with thin-die handling capability

Package ball-to-package edge gap decreases from 0.6 mm to 0 mm require new handling and socketing methods

Parallelism at greater than x128 drives thermal control and alignment challenges

Prober

Consistent and low thermal resistance across chuck is required to improve temperature control of device under test

Heat dissipation of >100 Watts at > 85ºC is a configuration gap in the prober industry

Advances in probe card technology require a new optical alignment methodology

document.xls

2007_TST11


Wafer diameter (mm) 300 300 300 300 300 300 300 450 450 450 450 450 450 450 450 450

Wafer thickness (um) 80–775 80–775 80–775 80–775 80–775 80–775 80–775 50–1000 50–1000 50–1000 50–1000 50–1000 50–1000 50–1000 50–1000 50–1000

Maximum I/O pads 3000 4000 4000 5300 5300 5300 5300 5300 5300 5300 5300 5300 5300 5300 5300 5300

Chuck X & Y positioning accuracy (um) 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Chuck Z positioning accuracy (um) 1 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5

Probe-to-pad alignment (µm) 4.5 4.5 4.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5

Maximum chuck force (kg) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100

Set point range (ºC)-30 to +85 -30 to +85 -30 to +85

-45 to -45 to -45 to -45 to -45 to -45 to -45 to -45 to -45 to -45 to -45 to -45 to -45 to

+125 +125 +125 +125 +125 +125 +125 +125 +125 +125 +125 +125 +125

Total power (Watts) 130 130 250 250 250 250 250 250 250 250 250 250 250 250 250 250

60 60 120 120 120 120 120 120 120 120 120 120 120 120 120 120Power density (Watt/cm2)

document.xls

2007_TST12


High, Medium and Low Power

Temperature set point range (ºC) -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175High Power - >10W per DUT

Temperature accuracy at DUT (ºC) ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2Number of pins/device 750 750 800 800 850 850 850 850 850 850 900 900 900 1000 1000 1000Parallel testing: 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2 1-2Throughput (devices per hour) 1.5–2K 1.5–2K 1.5–2K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5K 2–3.5KIndex time (S) 0.3 0.3 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25Sorting Categories 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6Allowable device temperature rise (ºC) 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20Maximum socket load per unit (kg) 24 27 30 30 35 35 35 35 35 35 35 35 35 35 35 35Asynchronous capability Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesPin/land pitch (mm) 1.1 1.1 1 1 0.8 0.6 0.6 0.6 0.6 0.6 0.4 0.4 0.4 0.4 0.4 0.4

Medium Power - 0.5 to 10W per DUT

Temperature accuracy at DUT (ºC) ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2 ± 2Number of pins/device 800 800 850 850 850 850 850 850 900 900 900 1000 1000 1000 1000 1000Parallel testing: 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16 8-16Throughput (devices per hour) 4–6K 4–6K 4–6K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10K 6–10KIndex time (S) 0.3 0.3 0.3 0.3 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25Sorting Categories 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3–6 3-6 3–6 3–6 3–6Allowable device temperature rise (ºC) 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5Maximum socket load per unit (kg) 50 50 35 60 35 60 60 60 65 65 65 75 75 75 75 75Asynchronous capability Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes YesPin/land pitch (mm) 0.3 0.3 0.3 0.3 0.3 0.3 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2

Low Power - < 0.5W per DUT

Temperature accuracy at DUT (ºC) ±2 ±2 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5 ±1.5

Number of pins/device 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250 6–250

Parallel testing: 128-512 128-1024 128-1024 128-1024 128-1024 128-1024 128-1024 128-1024 128-2048 128-2048 128-2048 128-2048 128-2048 128-2048 128-2048 128-2048

Throughput (devices per hour) 8–10K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K 12–20K

Index time (S) 2–5 2–5 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4 2–4Sorting Categories 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9 5–9

4x6 3x5 3x5 3x5 3x5 3x5 3x5 2x3 2x3 2x3 2x3 2x3 2x3 2x3 2x3 2x3

Pin pitch (mm) 0.4–1.0 0.25–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0 0.2–1.0

Ball edge to package edge clearance (mm) 0.25 0.25 0.25 0.25 0.25 0 0 0 0 0 0 0 0 0 0 0

Minimum package thickness (mm) 0.4–1.8 0.3–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8 0.2–1.8

Min. Pkg. Size(mm2)

Table TST13 Probing Difficult Challenges

Geometry

Probe technologies to support peripheral fine pitch probe of 23 µm peripheral staggered pad probes at effective pitches of 20/40, and fine pitch (45 µm) for dual row, non-staggered probing on all four die sides.

Fine pitch vertical probe technologies to support 130 µm pitch area array solder bump and 50 µm pitch staggered pad devices.

Multi-site pad probing technologies with corner pitch capability below 125 µm.

Reduction of pad damage at probe commensurate with pad size reductions (or better).

Alternative probe technology for 75 µm on 150 µm pitch dense array (vertical probe; bumped device).

Increasing probe array planarity requirements in combination with increasing array size.

Parallel test Need a probe technology to handle the complexity of SoC devices while probing more than one

device.

Current probe technologies have I/O limitations for bumped device probes.

Probing at temperature Reduce effects on probes for non-ambient testing -50°C to 150°C; especially for fine-pitch devices.

For effects on Handlers and Probers, see that section.

Product

Probe technologies to direct probe on copper bond pads including various oxidation considerations.

Probe technologies for probing over active circuitry (including flip-chip).

Probe force

Reduce per pin force required for good contact resistance to lower total load for high pin count and multi DUT probe applications. Evaluation and reduction of probe force requirements to eliminate die damage, including interlayer dielectric damage with lo

A chuck motion model is required to minimize probe damage

Probe cleaning

Development of high temperature (85°C–150°C) in situ cleaning mediums/methods, particularly for fine pitch, multi-DUT, and non-traditional probes.

Reduction of cleaning requirements while maintaining electrical performance to increase lifetime.

A self cleaning probe card is required for fine pitch bumped pad devices

Cost and delivery

Fine pitch or high pin count probe cards are too expensive and take too long to build.

Time and cost to repair fine pitch or high pin count probe cards is very high.

The time between chip design completion (“tape-out”) and the availability of wafers to be probed is less than the time required to design and build a probe card in almost every probe technology except traditional cantilever.

Space transformer lead times are too long, thus causing some vertical probe technologies to have lengthy lead-times.

Probe metrology Tools are required that support fine pitch probe characterization and pad damage measurements.

Metrology correlation is needed for post repair test versus on-floor usage.

High power devices Probe technologies will need to incorporate thermal management features capable of handling

device power dissipations approaching 1000 Watts and the higher currents (≥ 1.5 amp) flowing through individual probe points.

Contact resistance Probe technologies that achieve contact resistance <.5 Ohms initially and throughout use are needed.

A method to measure contact resistance is needed. The traditional continuity test is insufficient to monitor contact resistance.

High frequency probing Traditional probe technologies do not have the necessary electrical bandwidth for higher frequency

devices. At the top end are RF devices, requiring up to 40 GHz.

ORTCINDEX

2007 ITRS Chapters

2008INDEX

Table TST13 Probing Difficult Challenges

Geometry

Probe technologies to support peripheral fine pitch probe of 23 µm peripheral staggered pad probes at effective pitches of 20/40, and fine pitch (45 µm) for dual row, non-staggered probing on all four die sides.

Fine pitch vertical probe technologies to support 130 µm pitch area array solder bump and 50 µm pitch staggered pad devices.

Multi-site pad probing technologies with corner pitch capability below 125 µm.

Reduction of pad damage at probe commensurate with pad size reductions (or better).

Alternative probe technology for 75 µm on 150 µm pitch dense array (vertical probe; bumped device).

Increasing probe array planarity requirements in combination with increasing array size.

Parallel test Need a probe technology to handle the complexity of SoC devices while probing more than one

device.

Current probe technologies have I/O limitations for bumped device probes.

Probing at temperature Reduce effects on probes for non-ambient testing -50°C to 150°C; especially for fine-pitch devices.

For effects on Handlers and Probers, see that section.

Product

Probe technologies to direct probe on copper bond pads including various oxidation considerations.

Probe technologies for probing over active circuitry (including flip-chip).

Probe force

Reduce per pin force required for good contact resistance to lower total load for high pin count and multi DUT probe applications. Evaluation and reduction of probe force requirements to eliminate die damage, including interlayer dielectric damage with lo

A chuck motion model is required to minimize probe damage

Probe cleaning

Development of high temperature (85°C–150°C) in situ cleaning mediums/methods, particularly for fine pitch, multi-DUT, and non-traditional probes.

Reduction of cleaning requirements while maintaining electrical performance to increase lifetime.

A self cleaning probe card is required for fine pitch bumped pad devices

Cost and delivery

Fine pitch or high pin count probe cards are too expensive and take too long to build.

Time and cost to repair fine pitch or high pin count probe cards is very high.

The time between chip design completion (“tape-out”) and the availability of wafers to be probed is less than the time required to design and build a probe card in almost every probe technology except traditional cantilever.

Space transformer lead times are too long, thus causing some vertical probe technologies to have lengthy lead-times.

Probe metrology Tools are required that support fine pitch probe characterization and pad damage measurements.

Metrology correlation is needed for post repair test versus on-floor usage.

High power devices Probe technologies will need to incorporate thermal management features capable of handling

device power dissipations approaching 1000 Watts and the higher currents (≥ 1.5 amp) flowing through individual probe points.

Contact resistance Probe technologies that achieve contact resistance <.5 Ohms initially and throughout use are needed.

A method to measure contact resistance is needed. The traditional continuity test is insufficient to monitor contact resistance.

High frequency probing Traditional probe technologies do not have the necessary electrical bandwidth for higher frequency

devices. At the top end are RF devices, requiring up to 40 GHz.

document.xls

2007_TST14

Year of Production 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

DRAM ½ Pitch (nm) (contacted) 65 57 50 45 40 36 32 28 25 22 20 18 16 14

MPU and ASIC ProductsWirebond - inline pad pitch 40 35 35 30 30 25 25 25 25 25 25 25 25 25Bump - array pad pitch 130 130 120 120 120 110 110 100 100 95 95 90 90 85I/O Pad Size (µm) X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X YWirebond 30 55 30 55 30 55 25 45 25 45 20 35 20 35 20 35 15 25 15 25 15 25 15 25 15 25 15 25Bump 65 65 65 65 60 60 60 60 60 60 55 55 55 55 50 50 50 50 45 45 45 45 45 45 45 45 40 40Scrub (% of pad) AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH Offline DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTHWirebond 25 50 25 50 25 50 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40Bump 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30

2050 2400 2400 2400 2400 2400 2400 2400 2400 2400 2400 2400 2400 2400

Number of Probe Points /Touchdown - Asics 5000 6000 7500 7500 7500 9000 9000 9000 9000 9000 9000 9000 9000 9000

Number of Probe Points / Touchdown - MPU 20000 20000 20000 20000 20000 30000 30000 30000 30000 30000 30000 30000 30000 30000

Maximum Current (mA) Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe TipASIC 400 <.001 500 <.001 500 <.001 500 <.001 500 <.001 1000 <.001 1000 <.001 1000 <.001 1000 <.001 1000 <.001 1000 <.001 1000 <.001 1000 <.001 1000 <.001MPU 1000 <.001 1000 <.001 1200 <.001 1200 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001 1500 <.001Maximum Resistance (Ohm) Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series

<0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3

Memory ProductsWirebond - inline pad pitch 75 75 70 70 65 65 60 60 55 55 50 50 50 50I/O Pad Size (µm) X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X YWirebond 65 80 65 80 60 80 60 80 55 80 55 80 55 80 55 80 50 80 50 80 50 80 65 80 65 80 65 80Scrub (% of pad) AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTHWirebond 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50 25 50

100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer 100% of wafer

Number of Probe Points / Touchdown - Memory 20000 20000 25000 25000 30000 30000 30000 30000 30000 30000 30000 30000 30000 30000

Maximum Current (mA) Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip Probe Tip200 <.001 200 <.001 200 <.001 200 <.001 250 <.001 250 <.001 250 <.001 250 <.001 250 <.001 250 <.001 250 <.001 250 <.001 250 <.001 250 <.001

Maximum Resistance (Ohm) Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series<0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3 <0.5 <3

RF and Mixed Signal ProductsWirebond - inline pad pitch 40 35 35 30 30 25 25 25 25 25 25 25 25 25Bump - array pad pitch 130 130 120 120 120 110 110 100 100 95 95 90 90 85I/O Pad Size (µm) X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X Y X YWirebond 30 55 30 55 30 55 25 45 25 45 20 35 20 35 20 35 15 25 15 25 15 25 15 25 15 25 15 25Bump 65 65 65 65 60 60 60 60 60 60 55 55 55 55 50 50 50 50 45 45 45 45 45 45 45 45 40 40Scrub (% of pad) AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH Offline DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTH AREA DEPTHWirebond 25 50 25 50 25 50 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40 20 40Bump 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30

1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600 1600Number of Probe Points /Touchdown 680 680 680 680 680 680 680 680 680 680 680 680 680 680Maximum Resistance (Ohm) Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series Contact Series

<0.5 <3 <0.5 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3 <0.4 <3

Size of Probed Area (mm2)

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage


DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage

DC Leakage


document.xls

2007_TST15

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

TSOP – Flash (NAND) – Contact blade [1]

Commodity NAND Memory

Lead Pitch (mm) 0.4 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3Data rate (MT/s) 50 50 50 66 66 100 100 100 100 133 133 133 133 266 266 266Contact blade

Inductance (nH) 10-15 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10Contact Stroke (mm) 0.3-0.5 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3Contact force (N) 0.2-0.4 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3Contact resistance (m ohm) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30Slit width (mm) 0.22 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17

BGA – DRAM – Spring Probe [2]

Commodity DRAM (Mass production)

Lead Pitch (mm) 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5DRAM RM GT/S 1.1 1.3 1.3 1.6 1.6 2.1 2.7 2.7 3.2 3.2 4.3 5.3 5.4 6.4 6.4 8.5Spring Probe

Inductance (nH) 1.5 1.5 1.5 1 1 1 0.5 0.5 0.3 0.3 0.3 0.2 0.2 0.15 0.15 0.15Contact Stroke (mm) 0.3 0.3 0.3 0.3 0.3 0.3 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2Contact force (N) <0.4 <0.4 <0.4 <0.3 <0.3 <0.3 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2Contact resistance (m ohm) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100

BGA – SoC – Spring Probe (50 ohm) [3]

Logic (High volume microprocessor)

Lead Pitch (mm) 0.8 0.8 0.8 0.65 0.65 0.65 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5 0.5 0.5I/O data (GT/s) 6 6 12 12 12 12 15 15 15 20 20 20 40 40 40 40Spring Probe (50 ohm)

Impedance (ohm) 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50Contact Stroke (mm) 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3Contact force (N) <0.4 <0.4 <0.4 <0.3 <0.3 <0.3 <0.3 <0.3 <0.3 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2Contact resistance (m ohm) 100 70 70 50 50 50 50 50 50 50 50 50 50 50 50 50

BGA – SoC – Conductive Rubber [4] [5]

Logic (High volume microprocessor)

Lead Pitch (mm) 0.8 0.8 0.8 0.65 0.65 0.65 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5 0.5 0.5I/O data (GT/s) 6 6 12 12 12 12 15 15 15 20 20 20 40 40 40 40Spring Probe (50 ohm)

Inductance (nH) 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 <0.1 <0.1 <0.1 <0.1Contact Stroke (mm) 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15Contact force (N) 0.2 0.2 0.2 0.15 0.15 0.5 0.15 0.15 0.15 0.1 0.1 0.1 0.1 0.1 0.1 0.1Contact resistance (m ohm) 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50Thickness (mm) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5




Notes:

[1] For pitches less than 0.3mm contactor molding becomes difficult due to the thin wall thickness between pins.

[2] For higher performance, a shorter probe spring is required which shortens the contact stroke. In 2019, the contact stroke will be 0.2mm so the contact resistance will be unstable.

[3] The spring probe must be coaxial for high-speed test. 20GT/s cannot be supported with finer pitches.

[4] Ball height is expected to change over the roadmap but amount of change is not known.

[5] A contact stroke of 0.15mm was assumed with a 0.5mm rubber thickness. For high ball count devices the contact pressure has been lowered.

Table RFAMS1 RF and Analog Mixed-Signal CMOS Technology Requirements


Performance RF/Analog [1]

Supply voltage (V) [2] 1.2 1.1 1.1 1

2 1.9 1.6 1.5

Gate Length (nm) [2] 53 45 37 32

32 30 30 30

160 140 100 90

6 6 5 5

13 11 9 8

170 200 240 280

200 240 290 340

0.25 0.22 0.2 <0.2

Precision Analog/RF Driver [1]

Supply voltage (V) 2.5 2.5 2.5 1.8

5 5 5 3

Gate Length (nm) [10] 250 250 250 180

220 220 220 160

IS 1000 1000 1000 360

9 9 9 6

40 40 40 50

70 70 70 90

CMOS NFET [1 HP CMOS lag 2 yrs]

1.1 1.1 1.1 1

EOT: Equivalent Oxide Thickness (Å) [13] 12 11 11 9

IS 53 37 32 29

IS 170 240 280 310

IS 200 290 340 380

IS 2.1 1.8 1.7 1.6

IS 4.0 3.5 3.4 3.3

ADD 5.3 4.7 4.5 4.4



Interim solutions are known ¿Manufacturable solutions are NOT known

Notes for Table RFAMS1a and b:

Tox (nm) [2]

gm/gds at 5·Lmin-digital [3]

1/f-noise (µV²·µm²/Hz) [4]

s Vth matching (mV·µm) [5]

Ids (µA/µm) [6]

Peak Ft (GHz) [7]

Peak Fmax (GHz) [8]

NFmin (dB) [9]

Tox (nm) [10]

gm/gds at 10·Lmin-digital [11]

1/f Noise (µV²·µm²/Hz) [4]

s Vth matching (mV·µm) [5]

Peak Ft (GHz) [7]

Peak Fmax (GHz) [8]

Vdd: Power Supply Voltage (V) [13]

Lg: Physical Lgate for High Performance logic (nm) [13]

Peak Ft (GHz) [7]

Peak Fmax (GHz) [8]

NFmin (dB) at 24GHz[14]


NF min (dB) at 94GHz[14]

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[9] This is the minimum transistor noise figure at 5GHz. 0.2dB represents the limitation of commercially available measurement equipment.

[14] This is the minimum transistor noise figure at 24 and 60GHz.

[1] Year of first digital product for a given technology generation as given in overall roadmap technology characteristics (ORTC) tables. Lithographic drivers for key technologies are indicated. Year of first RF and mixed-signal product at the same technology lag the low-standby power roadmap by one year. Beyond Planar CMOS, performance RF/Analog CMOS reflect DG CMOS, Precision Analog/RF driver device color change to yellow reflecting uncertainty on device integration. The supply voltage, Tox, Gate Length and Ids, Ft, Fmax color codes reflected the low-standby power roadmap. Any discrepancies, please refer to those of low-standby power roadmap.

[2] Nominal supply voltage, Vdd, SiO2 equivalent physical CMOS gate dielectric thickness, Tox, and minimum nominal gate length from low-standby power digital roadmap. For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.

[3] Measure for the low frequency amplification of a 5X minimum length, low-standby power CMOS transistor. Using different lengths is an extra degree of freedom in mixed signal designs. Long devices have better Gds amplification (at low frequencies). Operation point taken at 200 mV above the threshold voltage, V th, and at Vds = Vdd/2. The minimum value of 30 exceeds the projected technology capability with continued scaling for the standard logic device. When this occurs, the standard logic device should be replaced with an unique device designed for specifically for superior gain.

[4] Gate-referred 1/f noise spectral density, at a frequency of 1 Hz, normalized to an active gate area of 1 µm2. Operation point taken at 200 mV above the threshold voltage, Vth, and at Vds = Vdd/2.

[5] Matching specification for the NMOS transistor’s threshold voltage, assuming “near neighbor” devices at minimum practical separation. Careful layout and photolithographic uniformity, e.g. by using dummy structures, are required. Statistical dopant fluctuations start limiting further improvement with SiO 2. Matching behavior of high-k gate dielectrics very may be problematic. This parameter determines the lower boundary for the size of transistor in a mixed-signal circuit for a given accuracy and will limit dimensional, performance, and DC power consumption.

[6] Ids for Ft of 50 GHz for a minimum transistor length. Ft of 50 GHz is chosen for being 10X the application frequency for 5 GHz. An application frequency of 5 GHz is chosen as a mid-point for the frequency range of interest (1–10 GHz).

[7] Peak Ft measured from H21 extrapolated from 40 GHz with a 20 dB/dec slope.

[8] Peak Fmax measured from unilateral gain extrapolated from 40 GHz with a 20 dB/dec slope.

[10] This device is required to achieve direct modulation of the PA for applications from 2 to5 GHz and to support precision analog applications. Device with higher voltage tolerance are typically integrated with logic devices to support input-output interfaces. With continued scaling of logic devices alternate device structures may be required to support the required specifications.

[11] Measure for the low frequency amplification of a 10 minimum length, low-standby power CMOS transistor. Using different lengths is an extra degree of freedom in mixed signal designs. Long devices have better Gds amplification (at low frequencies). Operation point taken at 200 mV above the threshold voltage, V th, and at Vds = Vdd/2.

[12] Nominal supply voltage, Vdd, SiO2 equivalent electrical CMOS gate dielectric thickness, EOTelec and minimum nominal gate length from high-performance digital roadmap. For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.

[13] Nominal supply voltage, Vdd, SiO2 equivalent physical CMOS gate dielectric thickness, Tox, and minimum nominal gate length from high performance digital roadmap. For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.

2011 2012 2013 2014 2015 2016 2017 2018 2019

1 1 1 0.95 0.85 0.8 0.8 0.8 0.8

1.4 1.3 1.2 1.1 1.2 1.1 1.1 1 1

28 25 22 20 18 16 14 13 12

30 30 30 30 30 30 30 30 30

80 70 60 50 60 50 50 40 40

5 5 5 5 5 4 4 4 4

7 6 6 5 4 4 3 3 3

320 360 400 440 490 550 630 670 730

390 440 510 560 630 710 820 880 960

<0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2 <0.2

1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.5

3 3 3 3 3 3 3 3 2.6

180 180 180 180 180 180 180 180 130

160 160 160 160 160 160 160 160 110

360 360 360 360 360 360 360 360 270

6 6 6 6 6 6 6 6 5

50 50 50 50 50 50 50 50 70

90 90 90 90 90 90 90 90 120

switch to DG device

1 1 0.95 0.9 0.9 0.9 0.8 0.8 0.7

7.5 6.5 5.5 5 6 6 6 5.5 5.5

27 24 22 20 18 17 15 14 12.8

330 370 400 440 490 520 590 630 680

410 460 510 560 630 670 760 820 900

1.6 1.5 1.4 1.4 1.3 1.3 1.2 1.2 1.1

3.2 3.0 3.0 2.9 2.7 2.7 2.6 2.5 2.4

4.3 4.1 4.0 3.9 3.8 3.7 3.5 3.5 3.4


switch to DG device

[9] This is the minimum transistor noise figure at 5GHz. 0.2dB represents the limitation of commercially available measurement equipment.

[14] This is the minimum transistor noise figure at 24 and 60GHz.

[1] Year of first digital product for a given technology generation as given in overall roadmap technology characteristics (ORTC) tables. Lithographic drivers for key technologies are indicated. Year of first RF and mixed-signal product at the same technology lag the low-standby power roadmap by one year. Beyond Planar CMOS, performance RF/Analog CMOS reflect DG CMOS, Precision Analog/RF driver device color change to yellow reflecting uncertainty on device integration. The supply voltage, Tox, Gate Length and Ids, Ft, Fmax color codes reflected the low-standby power roadmap. Any discrepancies, please refer to those of low-standby power roadmap.

, and minimum nominal gate length from low-standby power digital roadmap. For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.

[3] Measure for the low frequency amplification of a 5X minimum length, low-standby power CMOS transistor. Using different lengths is an extra degree of freedom in mixed signal amplification (at low frequencies). Operation point taken at 200 mV above the threshold voltage, V th, and at Vds = Vdd/2. The minimum value of 30

exceeds the projected technology capability with continued scaling for the standard logic device. When this occurs, the standard logic device should be replaced with an unique device

. Operation point taken at 200 mV above the threshold voltage, Vth, and

[5] Matching specification for the NMOS transistor’s threshold voltage, assuming “near neighbor” devices at minimum practical separation. Careful layout and photolithographic uniformity, e.g. by using dummy structures, are required. Statistical dopant fluctuations start limiting further improvement with SiO 2. Matching behavior of high-k gate dielectrics very may be problematic. This parameter determines the lower boundary for the size of transistor in a mixed-signal circuit for a given accuracy and will limit dimensional, performance, and

of 50 GHz is chosen for being 10X the application frequency for 5 GHz. An application frequency of 5 GHz is chosen as a

[10] This device is required to achieve direct modulation of the PA for applications from 2 to5 GHz and to support precision analog applications. Device with higher voltage tolerance are typically integrated with logic devices to support input-output interfaces. With continued scaling of logic devices alternate device structures may be required to support the required

minimum length, low-standby power CMOS transistor. Using different lengths is an extra degree of freedom in mixed signal amplification (at low frequencies). Operation point taken at 200 mV above the threshold voltage, V th, and at Vds = Vdd/2.

equivalent electrical CMOS gate dielectric thickness, EOTelec and minimum nominal gate length from high-performance digital roadmap. For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.

, and minimum nominal gate length from high performance digital roadmap. For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.

2020 2021 2022

0.75 0.75 0.7

0.9 0.9 0.8

11 10 10

30 30 30

30 30 30

3 4 5

2 2 2

790 870 870

1050 1160 1160

<0.2 <0.2 <0.2

1.5 1.5 1.5

2.6 2.6 2.6

130 130 130

110 110 110

270 270 270 fixed error in scaling relationship

5 5 5

70 70 70

120 120 120

switch to DG device

0.7 0.7 0.65

5.5 5 5

11.7 10.7 9.7 following FEP, PIDS changes

740 810 890

990 1080 1200

1.1 1.0 1.0 matched published data and used more-physical scaling model

2.3 2.3 2.2 matched published data and used more-physical scaling model

3.2 3.1 3.0 added 94GH Nfmin starting in 2013

Table RFAMS2 RF and Analog Mixed-Signal Bipolar Technology Requirements


General Analog NPN Parameters

Emitter width (nm) (HS and HV NPN) 130 120 100 100

2 2 2 1.5

2 2 2 2

High Speed (HS) NPN (Common to mmWave Table)

IS 250 275 300 320

IS 280 305 330 350

Nfmin (dB) at 60GHz 3 2.5 2.2 1.9

BVceo (V) 1.8 1.7 1.65 1.6

13 15 17 18

High Voltage (HV) NPN

90 90 100 100

170 180 190 200

3.1 3.1 2.9 2.9

0.26 0.24 0.2 <0.2

28 22 16 15

Power Amplifier (PA) NPN (Common to PA Table)

IS 30 30 30 35

IS 80 80 80 80

IS Bvceo (V) 7 7 7 7

IS 17 17 17 17




1/f-noise (µV²·µm²/Hz)

s current matching (%·µm)

Peak Ft (GHz)

Peak Fmax (GHz)

Jc at Peak Ft (mA/µm2)

Peak Ft (GHz) [Vcb=1V]

Peak Fmax (GHz)

BVceo

NFmin (dB) at 5GHz

Ic (µA/µm) at 50GHz Ft


Peak Fmax (GHz)

BVcbo (V)

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Year of Production


Emitter width (nm) (HS and HV NPN)


Nfmin (dB) at 60GHz

BVceo (V)



Bvceo (V)



Interim solutions are known

Manufacturable solutions are NOT known



Peak Ft (GHz)

Peak Fmax (GHz)



Peak Fmax (GHz)

BVceo

NFmin (dB) at 5GHz



Peak Fmax (GHz)

BVcbo (V)

2011 2012 2013 2014 2015

100 90 90 90 80

1.5 1.5 1 1 1

2 2 2 2 2

340 360 380 395 415

370 390 410 425 445

1.7 1.5 1.4 1.3 1.2

1.55 1.5 1.45 1.4 1.35

19 21 22 23 24

110 110 120 120 130

210 220 230 240 250

2.8 2.8 2.6 2.6 2.5

<0.2 <0.2 <0.2 <0.2 <0.2

14 13 12 11 10

35 35 40 40 40

80 80 80 80 80

7 7 7 7 7

17 17 17 17 17


Year of Production




Nfmin (dB) at 60GHz

BVceo (V)



Bvceo (V)







Peak Ft (GHz)

Peak Fmax (GHz)



Peak Fmax (GHz)

BVceo

NFmin (dB) at 5GHz



Peak Fmax (GHz)

BVcbo (V)

2016 2017 2018 2019 2020

80 80 70 70 70

1 1 1 1 1

2 2 2 2 2

430 445 455 470 480

460 475 485 500 510

1.1 1 1 0.9 0.9

1.35 1.3 1.3 1.3 1.3

25 26 27 28 29

130 140 140 150 150

260 270 280 290 300

2.5 2.4 2.4 2.4 2.4

<0.2 <0.2 <0.2 <0.2 <0.2

9 8 7 6 5

40 40 40 40 40

80 80 80 80 80

7 7 7 7 7

17 17 17 17 17


Year of Production




Nfmin (dB) at 60GHz

BVceo (V)



Bvceo (V)







Peak Ft (GHz)

Peak Fmax (GHz)



Peak Fmax (GHz)

BVceo

NFmin (dB) at 5GHz



Peak Fmax (GHz)

BVcbo (V)

2021 2022

70 70

1 1

2 2

490 500 updated numbers, drop vcb defintion

520 530 updated numbers and colors0.9 0.8

1.25 1.25

29 30

160 160

310 320

2.3 2.3

<0.2 <0.2

5 5

40 40 updated numbers

80 80 updated numbers7 7 updated numbers

17 17 updated numbers


Year of Production




Nfmin (dB) at 60GHz

BVceo (V)



Bvceo (V)







Peak Ft (GHz)

Peak Fmax (GHz)



Peak Fmax (GHz)

BVceo

NFmin (dB) at 5GHz



Peak Fmax (GHz)

BVcbo (V)

updated numbers, drop vcb defintion

Table RFAMS3 On-Chip Passives Technology Requirements


Analog

MOS Capacitor

7 7 7 11

<1e-9 <1e-9 <1e-9 <2e-6

Resistor

Thin Film BEOL

0.03 0.03 0.05 0.05

Temp. linearity (ppm/ºC) <100 <100 40-80 40-80

0.2 0.2 0.15 0.15

Sheet resistance, Rs (Ohm/sq) 50 50 50 50

P+ Polysilicon

0.1 0.1 0.1 0.1

Temp. linearity (ppm/ºC) <100 <100 40-80 40-80

1.7 1.7 1.7 1.7

Sheet resistance, Rs (Ohm/sq) 200–300 200–300 200–300 200–300

RF

Metal-Insulator-Metal Capacitor

IS 5 5 5 5

IS <100 <100 <100 < 100

IS <1e-8 <1e-8 <1e-8 <1e-8

IS 0.5 0.5 0.5 0.5

IS >50 >50 >50 >50

MOM Capacitor

3.7 5 5.3 6.2

Voltage linearity (ppm/V²) <100 <100 <100 <100

s Matching (% for 1pF) <0.15 <0.15 <0.15 <0.15

Inductor

29 30 32 34

MOS Varactor

Tuning Range [4] >5.5 >5.5 >5.5 >5.5

IS 35 40 40 45

PA

PA III-V Passives

IS Inductors Q (1GHz, 5nH) [5] 15 25 25 25

Capacitor Q [6] >100 >100 >100 >100

1.2 1.2 1.2 2

PA Silicon/SiGe Passives

IS Inductors Q (1GHz, 5nH) [5] 10 14 14 14

Capacitor Q [6] >100 >100 >100 >100

IS 2 2 2 2





Density (fF/µm²) [1]

Leakage (A/cm²) [8]

Parasitic capacitance (fF/µm²)

1s Matching (% µm)

Parasitic capacitance (fF/µm²)

1s Matching (% µm)

Density (fF/µm2) [2]

Voltage linearity (ppm/V²) Leakage (A/cm²) [9]

s Matching (%·µm)

Q (5 GHz for 1pF)

Density (fF/µm²)

Q (5 GHz, 1nH) [3]

Q (5 GHz, 0 V)

RF capacitor density (fF/µm2) [7]

RF capacitor density (fF/µm2) [7]

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[1] This capacitance density corresponds to the highest end of the gate oxide thickness for precision analog device in the CMOS table.

[3] Q at 5 GHz for a single-ended 1nH inductor with a dedicated thick metal (analog metal).

[4] Defined as Cmax/Cmin in C-V curve of the varactor. Varactor align with performance RF device in the CMOS table.

[5] Inductor Q-quality factor of a 5nH inductor at 1 GHz achievable with the technology with a metallization suitable for handling the power requirements of the PA.

[6] Capacitor Q-quality factor of a 10 pF capacitor at 1 GHz achievable with the technology. Capacitor breakdown voltage must be rated for appropriate power amplification function.

[9] Leakage current is defined at room temperature and for the highest end of the supply voltage range for precision analog device in the CMOS table.

[2] No stacking (two capacitors on top of each other) is included. Coloring reflected MIM capacitor meeting all requirements including density, voltage linearity, leakage and matching on copper metallization.

[7] RF capacitor density-capacitor used for all other functions (matching, harmonic filtering, coupling, etc.). Capacitor must have adequate breakdown for the given application. No stacking.

[8] Leakage current is defined at room temperature and for the highest end of the supply voltage range and thickness end of the gate oxide thickness for precision analog device in the CMOS table.

2011 2012 2013 2014 2015 2016 2017 2018 2019

11 11 11 11 11 11 11 11 13

<2e-6 <2e-6 <2e-6 <2e-6 <2e-6 <2e-6 <2e-6 <2e-6 <2e-5

0.05 0.05 0.08 0.08 0.08 0.08 0.08 0.08 0.08

40-80 40-80 30 30 30 30 30 30 20

0.15 0.15 0.1 0.1 0.1 0.1 0.1 0.1 0.08

50 50 50 50 50 50 50 50 50

0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1

40-80 40-80 30 30 30 30 30 30 30

1.7 1.7 1 1 1 1 1 1 0.08

200–300 200–300 200–300 200–300 200–300 200–300 200–300 200–300 200–300

5 5 7 7 7 10 10 10 12

< 100 < 100 < 100 < 100 < 100 < 100 < 100 < 100 < 100

<1e-8 <1e-8 <1e-8 <1e-8 <1e-8 <1e-8 <1e-8 <1e-8 <1e-8

0.5 0.5 0.3 0.3 0.3 0.2 0.2 0.2 0.2

>50 >50 >50 >50 >50 >50 >50 >50 >50

7 6.5 7.5 8.6 9.9 11.4 13.1 15.1 17.4

<100 <100 <100 <100 <100 <100 <100 <100 <100

<0.15 <0.15 <0.1 <0.1 <0.1 <0.1 <0.1 <0.1 <0.08

36 38 40 42 44 46 48 50 52

>5.5 >5.5 >5.5 >5.5 >5.5 >5.5 >5.5 >5.5 >5.5

45 50 50 50 55 55 60 60 65

25 30 30 30 30 30 30 30 30

>100 >100 >100 >100 >100 >100 >100 >100 >100

2 2 2 2 2 2 2 2 2

14 18 18 18 18 18 18 18 18

>100 >100 >100 >100 >100 >100 >100 >100 >100

2 2 2 2 2 2 2 2 2


[1] This capacitance density corresponds to the highest end of the gate oxide thickness for precision analog device in the CMOS table.

[3] Q at 5 GHz for a single-ended 1nH inductor with a dedicated thick metal (analog metal).

[4] Defined as Cmax/Cmin in C-V curve of the varactor. Varactor align with performance RF device in the CMOS table.

[5] Inductor Q-quality factor of a 5nH inductor at 1 GHz achievable with the technology with a metallization suitable for handling the power requirements of the PA.

[6] Capacitor Q-quality factor of a 10 pF capacitor at 1 GHz achievable with the technology. Capacitor breakdown voltage must be rated for appropriate power amplification function.

[9] Leakage current is defined at room temperature and for the highest end of the supply voltage range for precision analog device in the CMOS table.

[2] No stacking (two capacitors on top of each other) is included. Coloring reflected MIM capacitor meeting all requirements including density, voltage linearity, leakage and matching on

[7] RF capacitor density-capacitor used for all other functions (matching, harmonic filtering, coupling, etc.). Capacitor must have adequate breakdown for the given application. No

[8] Leakage current is defined at room temperature and for the highest end of the supply voltage range and thickness end of the gate oxide thickness for precision analog device in the

2020 2021 2022

13 13 13

<2e-5 <2e-5 <2e-5

0.08 0.08 0.08

20 20 20

0.08 0.08 0.08

50 50 50

0.1 0.1 0.1

30 20 20

0.08 0.08 0.08

200–300 200–300 200–300

12 12 12 updated numbers and colors

< 100 < 100 < 100 updated numbers and colors<1e-8 <1e-8 <1e-8 updated numbers and colors

0.2 0.2 0.2 updated numbers and colors>50 >50 >50 updated numbers and colors

20 23 26.4

<100 <100 <100

<0.08 <0.08 <0.08

54 56 58

>5.5 >5.5 >5.5

65 70 70 updated numbers and colors

30 30 30 updated colors>100 >100 >100

2 2 2

18 18 18 updated colors>100 >100 >100

2 2 2 updated numbers and colors, applications do not require the higher cap

updated numbers and colors, applications do not require the higher cap

Table RFAMS4 Embedded Passives Technology Requirements


Resistor [1]

IS Max Sheet resistance, Rs (Ohm/sq) 1K 1K 1K

IS Tolerance (%) [2] <10% <10% <5%

IS Temp. linearity (ppm/ºC) <500 <300 <300

IS Min Sheet resistance, Rs (Ohm/sq) 100 100 100

IS Tolerance (%) [2] <10% <5% <3%

IS Temp. linearity (ppm/ºC) <300 <200 <200

Capacitor [3]

IS Density (nF/cm²) >1 >1 >5

Tolerance (%) [2] <10% <7% <10%

TCC (ppm) <500 <300 <500

Breakdown Voltage (V) >500V >1KV >300V

max Q [4] >25 >30 >25

Self Resonance Freq (GHz) [5] >0.5 >0.5 >0.1

Inductor [3]

Density (nH/mm2) 0.4 0.4 0.8

Tolerance (%) [2] <5% <5% <5%

max Q [6] >40 >40 >40

Self Resonance Freq (GHz) [7] >10 >10 >10





[1] For both thick and thin film process

[2] Untrimmed total tolerance including material and process

[3] For all material and process (lamination, buried, etc.)

[6] Maximum Q for 10nH inductor

[4] Maximum Q for 1cm2 capacitor

[5] SRF for 1cm2 capacitor

[7] SRF for 25mm2 inductor

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2010 2011 2012 2013 2014 2015 2016 2017 2018

10K 100K 100K 500K 500K 500K 500K 500K 500K

<10% <10% <5% <10% <10% <5% <5% <5% <5%

<500 <300 <300 <500 <300 <300 <300 <300 <300

100 10 10 10 10 5 5 5 5

<1% <10% <5% <3% <1% <10% <5% <3% <1%

<200 <300 <200 <200 <200 <300 <200 <200 <200

>5 >5 >5 >10 >10 >10 >100 >100 >100

<7% <7% <5% <10% <7% <5% <10% <7% <5%

<400 <400 <300 <500 <300 <300 <300 <300 <200

>500V >700V >1KV >500V >700V >1KV >500V >500V >700V

>30 >30 >30 >25 >25 >30 >15 >20 >25

>0.1 >0.2 >0.2 >0.05 >0.1 >0.1 >0.001 >0.005 >0.01

0.8 0.8 0.8 2 2 2 2 4 4

<5% <5% <5% <5% <5% <3% <3% <3% <3%

>40 >40 >40 >40 >40 >40 >45 >45 >45

>10 >10 >10 >10 >10 >10 >10 >10 >10


[1] For both thick and thin film process

[2] Untrimmed total tolerance including material and process

[3] For all material and process (lamination, buried, etc.)

[6] Maximum Q for 10nH inductor

2019 2020 2021 2022

500K 500K 500K 500K

<5% <5% <3% <1%

<300 <300 <200 <200

1 1 1 1

<10% <5% <3% <1%

<300 <200 <200 <200

>1000 >1000 >1000 >1000

<10% <10% <7% <5%

<300 <200 <200 <200

>500V >500V >700V >1KV

>10 >15 >20 >25

>0.001 >0.001 >0.001 >0.001

4 4 8 8

<3% <3% <3% <3%

>45 >45 >45 >45

>10 >10 >10 >10

Table RFAMS5 Power Amplifier Technology Requirements


Nominal battery voltage 3.2 3.2 3.2 3.2

IS End-of-life battery voltage 2.85 2.85 2.4 2.4

PA product solutions Radio/Baseband SIP [2]

PA frequency (GHz)

III-V HBT transistor

45 45 55 55

25 25 18 18

Linear efficiency (%) [1] 52 52 55 55

2.5 2.5 2.2 2.2

0.32 0.3 0.28 0.28

III-V HBT integration

Bias Control MESFET

Power management [4] N/A

Switch [5] (by-pass) HEMT

Filter [6] N/A

III-V PHEMT transistor

45 45 75 75

20 20 16 16


4 4 3.5 3.5

0.28 0.25 0.24 0.24

III-V PHEMT integration

Power management [4] N/A

Switch [7] logic integration E/D pHEMT

Filter [6] N/A

Silicon MOSFET transistor

60 60 35 35

45 45 60 60

12 12 10 10


6 6 4.5 4.5

0.08 0.08 0.06 0.06

Silicon MOSFET integration

Power management [4] Yes

MEMS switch [5] NO Stack Above IC

MEMS filter [6] Stack WLP

SiGe HBT transistor [9]

60 60 80 80

IS 17 17 17 17


2.5 2.5 2.2 2.2

0.12 0.12 0.11 0.11

SiGe integration

Power management Yes

Fmax (at Vcc) (GHz)

BVCBO (V)

Area (mm2) [2]

Cost/mm2 (US$) [3]

Fmax (at Vdd) (GHz)

BVDGO (V)

PA Area (mm2) [2]

Cost/mm2 (US$) [3]

Tox (PA) (Å) [8]

Fmax (at Vdd)

BVDSS (V)

PA Area (mm2) [2]

Cost/mm2 (US$) [3]

Fmax (GHz)

BVCBO (V)

PA Area (mm2) [2]

Cost/mm2 (US$) [3]

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MEMS switch [5] NO Stack Above IC

MEMS filter [6] Stack WLP





[1] Linear efficiency—power added efficiency of the final PA stage under personal communication service (PCS) CDMA (IS-95) modulation.

[4] Power management—capability of the technology to provide RF power detection/DC power management for the PA.

[5] Switch—capability of the technology to integrate cost-effectively a stage by-pass switch into the PA active die.

[7] Switch Logic Integration—capability of the technology to integrate cost-effectively a control circuitry with the Tx/Rx antenna switch.

[9] Ideally, the Si requirements and GaAs requirements would be the same, but we use different values to account for the state-of-the-art performance differences between the technologies.

[2] Area—total semiconductor area necessary for the implementation of the quad-band GSM/general packet radio service (GPRS)/ Enhanced Data rates for GSM Evolution (EDGE) PA function, including matching/filtering.

[3] Cost/mm2—approximate commercial foundry cost of the area mentioned in [4].

[6] Filter—capability of the technology to integrate high-quality band selection filters needed for the assumed PA solution; currently performed with surface acoustic wave (SAW) filter technology.

[8] Tox (PA)—thickness of the MOSFET transistor in the RF power amplifier function.

2011 2012 2013 2014 2015 2016 2017 2018 2019

2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4

1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6 1.6

Radio/Baseband SIP [2] Radio/Baseband SIP [2]

55 65 65 65 65 65 65 65 65

18 18 18 18 18 18 18 18 18

55 55 55 55 55 55 55 55 55

2.2 2.2 2.2 2.2 2.2 2.2 2 2 2

0.28 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25

MESFET MESFET

N/A N/A

HEMT HEMT

N/A N/A

75 75 75 75 75 75 75 75 75

16 16 16 16 16 16 16 16 16

58 58 58 58 58 58 58 58 58

3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5

0.24 0.22 0.22 0.22 0.15 0.15 0.15 0.15 0.15

N/A N/A

E/D pHEMT E/D pHEMT

N/A N/A

35 35 35 35 35 35 35 35 35

60 60 60 60 60 60 60 60 60

10 10 10 10 10 10 10 10 10

45 45 45 45 45 45 45 45 45

4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5

0.06 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05

Yes Yes

Above IC Integrated Integrated

WLP Above IC Above IC

80 80 80 80 80 80 80 80 80

17 17 17 17 17 17 17 17 17

52 52 52 52 52 52 52 52 52

2.2 2.2 2.2 2.2 2.2 2.2 2 2 2

0.11 0.11 0.11 0.11 0.11 0.11 0.11 0.11 0.11

Yes Yes

0.8-6

Above IC Integrated Integrated

WLP Above IC Above IC

[1] Linear efficiency—power added efficiency of the final PA stage under personal communication service (PCS) CDMA (IS-95) modulation.

[4] Power management—capability of the technology to provide RF power detection/DC power management for the PA.

[5] Switch—capability of the technology to integrate cost-effectively a stage by-pass switch into the PA active die.

[7] Switch Logic Integration—capability of the technology to integrate cost-effectively a control circuitry with the Tx/Rx antenna switch.

[9] Ideally, the Si requirements and GaAs requirements would be the same, but we use different values to account for the state-of-the-art performance differences between the technologies.

[2] Area—total semiconductor area necessary for the implementation of the quad-band GSM/general packet radio service (GPRS)/ Enhanced Data rates for GSM Evolution (EDGE) PA

[6] Filter—capability of the technology to integrate high-quality band selection filters needed for the assumed PA solution; currently performed with surface acoustic wave (SAW) filter

2020 2021 2022

2.4 2.4 2.4

1.6 1.6 1.6 Delay 2.4V introRadio/Baseband SIP [2]

65 65 65

18 18 18

55 55 55

2 2 2

0.25 0.25 0.25

MESFET

N/A

HEMT

N/A

75 75 75

16 16 16

58 58 58

3.5 3.5 3.5

0.15 0.15 0.15

N/A

E/D pHEMT

N/A

35 35 35

60 60 60

10 10 10

45 45 45

4.5 4.5 4.5

0.05 0.05 0.05

Yes

Integrated

Above IC

80 80 80

17 17 17 updated numbers52 52 52

2 2 2

0.11 0.11 0.11

Yes

Integrated

Above IC

Table RFAMS6 Base Station Devices Technology Requirements


Application frequency (GHz) [1] 0.8–3.5 0.8–3.5 0.8–3.5 0.8–5

0.3 0.2 0.2 0.15

Packaging (C-Ceramic, P-Plastic) C, P C, P C, P Plastic

Si LDMOS

32, 48 32, 48 32, 48

240 300 400 500

1.8 1.8 1.8

55 57 60 55

120 150 200 250

39 40 42 39

GaAs FET

Operating voltage (V) 28 28

Saturated power (Watt) 240 240

Saturated power density (W/mm) 1.5 1.8

Saturated PAE (%) 65 67 70 65

Linear power (Watt) 120 120

Linear PAE (%) 46 47 50 46

GaN FET

Operating voltage (V) 48 48

Saturated power (Watt) 200 300

Saturated power density (W/mm) 4 5

Saturated PAE (%) 60 62 65 60




Note for Table RFAMS6a and b:

[1] Application frequencies affected device saturated PAE scaling.

Cost ($$/Watt)

Operating voltage (V)

Saturated power (Watt)

Saturated power density (W/mm)

Saturated PAE (%)

Linear power (Watt)

Linear PAE (%)

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2011 2012 2013 2014 2015 2016 2017 2018 2019

0.8–5 0.8–5 0.8–5 0.8–8 0.8–8 0.8–8

0.15 0.15 0.1 0.1 0.1 0.1

Plastic Plastic Plastic Plastic Plastic Plastic

32, 48 32, 48

500 500

1.8 1.8

57 60 60

250 250

40 42 42

28 28 28

240 240 240

1.8 1.8 1.8

67 70 70 70 72

120 120 120

47 50 50 50 51

48 48 48

400 500 500 500

5 5 5

62 65 65 65

2020 2021 2022

0.8–8

0.1

Plastic

32, 48

500

1.8

60

250

42

28

240

1.8

72

120

51

48

500

5

65


Device Technology—FET

GaAs PHEMT (low noise)

IS Gate length (nm) 150 150 150 100

IS 110 110 110 150

IS Breakdown (volts) 12 12 12 12

IS 650 650 650 700

IS 0.5 0.5 0.5 0.55

IS 1 1 1 0.8

IS 8.5 8.5 8.5 10.8

IS 2.8 2.8 2.8 2.5

IS 3 3 3 4

GaAs PHEMT (power)


IS 150 150 150 150


IS 700 700 700 700

IS 0.5 0.5 0.5 0.5

IS 650 650 650 650

IS 45 45 45 45

IS 11 11 11 11

GaAs PHEMT (power)


IS 200 200 200 200


IS 800 800 800 800

IS 0.65 0.65 0.65 0.65

IS 550 550 550 550

IS 30 30 30 30

IS 7 7 7 7

IS 350 350 350 350

IS 20 20 20 20

IS 5 5 5 5

InP HEMT (low noise)

Gate length (nm) 100 100 100 70

IS 200 200 200 250


IS 500 500 500 600

IS 1.1 1.1 1.1 1.5

IS 0.5 0.5 0.5 0.4

IS 15 15 15 16

Table RFAMS7 Millimeter Wave 10 GHz–100 GHz Technology Requirements

Ft (GHz)

Imax (mA/mm)

Gm (S/mm)

NFmin (dB) at 26 GHz

Associated Gain at 26 GHz

NFmin (dB) at 94 GHz

Associated Gain at 94 GHz

Fmax (GHz)

Imax (ma/mm)

Gm (S/mm)

Pout at 24 GHz and peak efficiency (mW/mm)

Peak efficiency at 24 GHz (%)

Gain at 24 GHz, at P1dB (dB)

Fmax (GHz)

Imax (ma/mm)

Gm (S/mm)







Ft (GHz)

Imax (ma/mm)

Gm (S/mm)

Fmin (dB) at 24 GHz

Associated Gain (dB) at 24 GHz

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IS 1 1 1 0.8

IS 11 11 11 12

IS 1.5 1.5 1.5 1.3

IS 8 8 8 9

InP HEMT (power)


IS 250 250 250 400


IS 500 500 500 600

IS 1.1 1.1 1.1 1.5

IS 450 450 450

IS 50 50 50

IS 14 14 14

IS 300 300 300 400

IS 40 40 45 50

IS 10 10 10 14

IS 150 150 160 200

IS 30 30 30 40

IS 7 7 7 10

GaAs MHEMT (low noise)—Ka through W-Band


IS 200 200 200 250

IS Channel In content (%) 60 60 60 70

IS Offstate Breakdown (volts) 6 6 6 4

IS 900 900 900 900

IS 1.2 1.2 1.2 1.4

IS 0.5 0.5 0.5 0.4

IS Associated Gain (dB) @ 24GHz 15 15 15 16

IS 1 1 1 0.7


IS 1.5 1.5 1.5 1.2


GaAs MHEMT (Power) -Ka band



IS 200 200 200 250


IS 760 760 760 850

IS 0.85 0.85 0.85 1

IS 800 800 800 850

IS 45 45 45 50

IS 12 12 12 14

GaAs MHEMT (Power)



IS 300 300 300 300

Fmin (dB) at 60 GHz


Fmin (dB) at 94 GHz


Fmax (GHz)

Imax (ma/mm)

Gm (S/mm)










Ft (GHz)

Imax (ma/mm)

Gm (S/mm)

Fmin (dB) at 24 GHz

Fmin (dB) at 60 GHz

Fmin (dB) at 94 GHz

Fmax (GHz)

Imax (ma/mm)

Gm (S/mm)




Fmax (GHz)


IS 900 900 900 900

IS 1.2 1.2 1.2 1.4

IS 500 500 500 550

IS 40 40 40 45

IS 8 8 8 9

IS 225 225 225 300

IS 30 30 30 35

IS 6 6 6 7

GaN HEMT (low noise)

Gate Length (nm) 150 100

120 160

Breakdown (volts) 40 35

1000 1200

0.4 0.5

1.2 1

Associated Gain at 24 GHz 10 12

GaN HEMT (power)

Gate Length (nm) 150

150

Breakdown (volts) 60

1200

0.5

5000

IS 50

10

GaN HEMT (power)

Gate length (nm) 100

200

Breakdown (volts) 40

1200

0.55

4000

30

8

2500

20

6

Device Technology—RF CMOS

CMOS NFET [1 HP CMOS lag 2 yrs]

1.1 1.1 1.1 1

EOT: Equivalent Oxide Thickness (Å) [13] 12 11 11 9

IS 53 37 32 29

IS 170 240 280 310

IS 200 290 340 380

IS 2.1 1.8 1.7 1.6

IS 4.0 3.5 3.4 3.3

Imax (ma/mm)

Gm (S/mm)







Ft (GHz)

Imax (ma/mm)

Gm (S/mm)

Fmin (dB) at 24 GHz

Fmax (GHz)

Imax (ma/mm)

Gm (S/mm)




Fmax (GHz)

Imax (ma/mm)

Gm (S/mm)









Peak Ft (GHz) [7]

Peak Fmax (GHz) [8]



ADD 5.3 4.7 4.5 4.4

Device Technology—HBT

InP HBT

IS Emitter width (nm) 1000 1000 500 500

IS 150 150 320 320

IS 200 200 320 320

IS 8 8 5 5

IS 1 1 5 5

SiGe HBT

Emitter width (nm) 130 120 100 100

250 275 300 320

280 305 330 350

Nfmin (dB) at 60GHz 3 2.5 2.2 1.9

ADD Nfmin (dB) at 94GHz 4.4 3.8 3.2 2.9

1.8 1.7 1.65 1.6

13 15 17 18




NF min (dB) at 94GHz[14]

Peak Ft (GHz)

Peak Fmax (GHz)

BVceo


Peak Ft (GHz)

Peak Fmax (GHz)

BVceo


2011 2012 2013 2014 2015 2016

100 100 100 delayed start of 100 nm until 2010




0.55 0.55 0.55 delayed start of 100 nm until 2010





150 150 150 150 150 150 deleted 100 nm data; extended 150 through 2016




0.5 0.5 0.5 0.5 0.5 0.5 deleted 100 nm data; extended 150 through 2016




70 70 70 70 nm data shifted 2 years out




0.75 0.8 0.8 70 nm data shifted 2 years out







70 50 50 35 35 25 shift 2 yrs. right; color changed for 35 nm data

250 350 350 420 420 500 shift 2 yrs. rigth

3 2.5 2.5 2 2 1.5 shift 2 yrs. right; color changed for 35 nm data

600 550 550 500 500 500 shift 2 yrs. rigth

1.5 1.8 1.8 2 2 2.2 shift 2 yrs. right; color changed for 35 nm data

0.4 0.3 0.3 0.3 0.3 0.25 shift 2 yrs. right; color changed for 35 nm data


0.8 0.6 0.6 0.6 0.6 0.5 shift 2 yrs. right; color changed for 35 nm data


1.3 1.1 1.1 1 1 0.9 shift 2 yrs. right; color changed for 35 nm data


70 70 50 50 50 50 shifted right 1 yr. and color changed for first 2 years @ 50 nm


3 3 2.5 2.5 2.5 2.5 shifted right 1 yr. and color changed for first 2 years @ 50 nm


1.5 1.5 1.7 1.7 1.7 1.7 shifted right 1 yr. and color changed for first 2 years @ 50 nm

shifted right one year



400 400 shifted right one year



200 200 200 200 200 200 shifted right one year



70 70 50 50 50 35 no change in data but shifted one year to the right



4 4 3 3 3 2.5 no change in data but shifted one year to the right


1.4 1.4 1.5 1.5 1.5 1.8 no change in data but shifted one year to the right





1.2 1.2 1 1 1 0.8 no change in data but shifted one year to the right







1 1 1.2 1.2 1.2 1.2 no change in data but shifted one year to the right
















100 70 70 50 50 50

160 200 200 240 240 240

35 30 30 25 25 25

1300 1400 1400 1400 1400 1400

0.55 0.6 0.6 0.65 0.65 0.65

1 0.8 0.8 0.6 0.6 0.6

12 13 13 14 14 14

150 150 150 150 150 150

150 150 150 150 150 150

80 80 80 80 80 80

1200 1400 1400 1400 1400 1400

0.5 0.6 0.6 0.6 0.6 0.6

6000 7000 8000 8000 8000 8000

50 50 50 50 50 50 data changed

10 12 12 12 12 12

100 70 70 70 50 50

200 240 240 240 280 280

60 40 60 60 40 40

1200 1500 1500 1500 1500 1500

0.55 0.65 0.65 0.65 0.65 0.65

4500 5000 5000 5000 4500 4500

30 35 35 35 40 40

8.5 9 9.5 9.5 10 10

3000 3500 4000 4000 3500 3500

25 30 30 30 35 35

6.5 7 7.5 7.5 8 8

1 1 0.95 0.9 0.9 0.9

7.5 6.5 5.5 5 6 6

27 24 22 20 18 17 following FEP, PIDS changes

330 370 400 440 490 520

410 460 510 560 630 670

1.6 1.5 1.4 1.4 1.3 1.3 matched published data and used more-physical scaling model

3.2 3.0 3.0 2.9 2.7 2.7 matched published data and used more-physical scaling model

4.3 4.1 4.0 3.9 3.8 3.7 added 94GH Nfmin starting in 2013






100 90 90 90 80 80

340 360 380 395 415 430

370 390 410 425 445 460

1.7 1.5 1.4 1.3 1.2 1.1

2.6 2.3 2.1 2.0 1.8 1.7

1.55 1.5 1.45 1.4 1.35 1.35

19 21 22 23 24 25

deleted 100 nm data; extended 150 through 2016








shift 2 yrs. right; color changed for 35 nm data









shifted right 1 yr. and color changed for first 2 years @ 50 nm





no change in data but shifted one year to the right

































matched published data and used more-physical scaling model

matched published data and used more-physical scaling model






Table RFAMS8 RF and Analog Mixed-Signal RFMEMS


Design Tools

BAW (0) Separate tools (1) IRFM, (2) CM (3) DF

Resonator (0) Separate tools (1) IRFM, (2) CM (3) DF

Switch—capacitive contact (0) Separate tools, (2) CM (1) IRFM

Switch—metal contact (0) Separate tools, (2) CM (1) IRFM

All MEMS devices (4) MEMS TCAD (4) MEMS TCAD

Packaging

BAW Die stacking. Wafer level package. Micro cavity package (CWS).

Resonator Stacked die

Switch—capacitive contact Above IC integration with CWS

Switch—metal contact Above IC integration with CWS

Performance Driver

BAW

Resonator Real Time Clock (32 kHz)

Switch—capacitive contact t Cellular Frontend (Tuning): 20:1 tuning ratio, 40V actuation

Switch—metal contact

Cost Driver

BAW Die size / package

Resonator MEMS processing cost Packaging

Switch—capacitive contact Processing cost. Die size / microcavity package. Test.

Switch—metal contact Process cost. Reliability / size / microcavity package. Test.

NOTES:Design Tools (0) Separate Tools - Mechanical and RF simulation tools not integrated. Manual integration with package and IC.Design Tools (1) IRFM - integrated RF and mechanical 3D simulation toolsDesign Tools (2) CM - physically based compact models i.e. simplified versions of IRFMDesign Tools (3) DF - Design flow e.g. circuit level simulation, that includes IRFM Design Tools (4) MEMS TCAD-like 3D process sequence simulation tool to simulate deposition, roughness, thermal, underetch, etc…Packaging CWS = cap wafer seal (die to wafer, or wafer to wafer)Packaging TFS = thin film seal (e.g. a thin film "pinch-off" technique)

F= 900MHz to 2.5GHz. size and cost ; TCF=-20

ppm/K; K2*Q=100

F= 900MHz to 5GHz. Testability improved. TCF= -5ppm; K2*Q=150

Clock oscillator (10-100MHz) multi-frequency per die.

Cellular Frontend (Tuning, T/R): Insertion loss <0.3dB, lifetime >1e10 cycles

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2010 2011 2012 2013

(3) DF DF + MEMS TCAD

(3) DF

(3) DF

(3) DF

Wafer level package. Micro cavity package (CWS). Above IC integration and TFS

Integration into IC and TFS

Above IC integration with CWS Embedded integration into IC and TFS

Above IC integration with CWS Embedded integration into IC and TFS

Nano resonator for filter function (800MHz–2.5GHz)

Cellular Frontend (Tuning): 20:1 tuning ratio, 40V actuation Cellular Frontend (Tuning): 30:1 tuning ratio, low-voltage actuation

Die size / package Integration with semiconductor die

Integration with semiconductor die

Processing cost. Die size / microcavity package. Test. Integration with semiconductor die

Process cost. Reliability / size / microcavity package. Test. Integration with semiconductor die

Design Tools (0) Separate Tools - Mechanical and RF simulation tools not integrated. Manual integration with package and IC.

Design Tools (4) MEMS TCAD-like 3D process sequence simulation tool to simulate deposition, roughness, thermal, underetch, etc…

Coupled Resonator Filter (CRF) ≥ increase functionality (e.g., impedance match).

F= 900MHz to 10GHz. Built In Self Test (BIST) structure. Tunable filter? TCF= -1ppm; K2*Q=200

Clock oscillator (10-100MHz) multi-frequency per die.



Table PIDS1 Process Integration Difficult Challenges—Near-term YearsDifficult Challenges ≥ 22 nm Summary of Issues

Scaling planar bulk CMOS will face significant challenges due to the high channel doping required, band-to-band tunneling across the junction and gate-induced drain leakage (GIDL), random doping variations, and difficulty in adequately controlling short channel effects. Also, keeping parasitics, such as series source/drain resistance with very shallow extensions and fringing capacitance, within tolerable limits will be significant issues.

Implementation into manufacturing of new structures such as ultra-thin body fully depleted silicon-on-insulator (SOI) and multiple-gate (e.g., FinFET) MOSFETs is expected at some point. This implementation will be challenging, with numerous new and difficult issues. A particularly challenging issue is the control of the thickness and its variability for these ultra-thin MOSFETs, as well as control of parasitic series source/drain resistance for very thin regions.

2. With scaling, difficulties in inducing adequate strain for enhanced mobility.

With scaling, it is critically important to maintain (or even increase) the current significantly enhanced CMOS channel mobility attained by applying strain to the channel. However, the strain due to current process-induced strain techniques tends to decrease with scaling.

Multiple major changes are projected over the next seven years, such as.:

Material: high-κ gate dielectric, metal gate electrodes, lead-free solder

Process: elevated S/D (selective epi) and advanced annealing and doping techniques

Structure: ultra-thin body (UTB) fully depleted (FD) SOI, multiple-gate MOSFETs, multi-chip package modules

It will be an important challenge to ensure the reliability of all these new materials, processes, and structures in a timely manner.

DRAM main issues with scaling—adequate storage capacitance for devices with reduced feature size, including difficulties in implementing high-κ storage dielectrics; access device design; holding the overall leakage to acceptably low levels; and deploying low sheet resistance materials for bit and word lines to ensure desired speed for scaled DRAMs.

SRAM—Difficulties with maintaining adequate noise margin and controlling key instabilities and soft error rate with scaling. Also, difficult lithography and etch issues with scaling.

Flash—Non-scalability of tunnel dielectric and interpoly dielectric. Dielectric material properties and dimensional control are key issues.

FeRAM—Continued scaling of stack capacitor is quite challenging. Eventually, continued scaling in 1T1C configuration. Sensitivity to IC processing temperatures and conditions.

MRAM—Magnetic material properties and dimensional control. Sensitivity to IC processing temperatures and conditions

Difficult Challenges<22 nm Summary of Issues

Advanced non-classical CMOS (e.g., multiple-gate MOSFETs) with ultra-thin, lightly doped body will be needed to scale MOSFETs to 10 nm gate length and below effectively. Control of parasitic resistance and capacitance will be critical.

To attain adequate drive current for the highly scaled MOSFETs, quasi-ballistic operation with enhanced thermal velocity and injection at the source end appears to be needed. Eventually, nanowires, carbon nanotubes, or other high transport channel materials (e.g., germanium or III-V thin channels on silicon) may be needed.

7. Dealing with fluctuations and statistical process variations in sub-11 nm gate length MOSFETs

Fundamental issues of statistical fluctuations for sub-10 nm gate length MOSFETs are not completely understood, including the impact of quantum effects, line edge roughness, and width variation.

Dense, fast, low operating voltage non-volatile memory will become highly desirable

Increasing difficulty is expected in scaling DRAMs, especially scaling down the dielectric equivalent oxide thickness and attaining the very low leakage currents and power dissipation that will be required.

All of the existing forms of nonvolatile memory face limitations based on material properties. Success will hinge on finding and developing alternative materials and/or development of alternative emerging technologies.

See Emerging Research Devices section for more detail.

Eventually, it is projected that the performance of copper/low-κ interconnect will become inadequate to meet the speed and power dissipation goals of highly scaled ICs.

Solutions (optical, microwave/RF, etc.) are currently unclear.

For detail, refer to ITRS Interconnect chapter.

Will drive major changes in process, materials, device physics, design, etc.

Performance, power dissipation, etc., of non-CMOS devices need to extend well beyond CMOS limits.

Non-CMOS devices need to integrate physically or functionally into a CMOS platform. Such integration may be difficult.

See Emerging Research Devices sections for more discussion and detail.

6. Implementation of advanced, non-classical CMOS with enhanced drive current and acceptable control of short channel effects for highly scaled MOSFETs

8. Identifying, selecting, and implementing new memory structures

9. Identifying, selecting, and implementing novel interconnect schemes

10. Eventually, identification, selection, and implementation of advanced, non-CMOS devices and architectures for advanced information processing

1. Scaling of MOSFETs to the 22 nm technology generation

3. Timely assurance for the reliability of multiple and rapid material, process, and structural changes

4. Scaling of DRAM and SRAM to the 22 nm technology generation

5. Scaling high-density non-volatile memory to the 22 nm technology generation

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Table PIDS2 High-performance Logic Technology Requirements

Year of Production 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

59 52 45 40 36 32 28 25 22 20 18 16 14 13 11

WAS 22 20 18 16 14 13 11 10 9 8 7 6 5.5 5 4.5

IS 29 27 24 22 20 18 17 15 14 12.8 11.7 10.7 9.7 8.9 8.1

EOT: Equivalent Oxide Thickness [2]

IS Extended planar bulk (Å) 12 10 9.5 8.8 7.5 6.5 6 5.3 5

IS UTB FD (Å) 7 6.5 6.8 5.5 5 5 5

IS DG (Å) 7.7 7 6 6 6 5.9 5.5 5.5

Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3]

IS Extended Planar Bulk (Å) 7.4 3.3 3.2 3.1 2.9 2.8 2.75 2.65 2.6

IS UTB FD (Å) 4 4 4 4 4 4 4

IS DG (Å) 4 4 4 4 4 4 4 4

IS Extended Planar Bulk (Å) 19.4 13.3 12.7 11.9 10.4 9.3 8.75 7.95 7.6

IS UTB FD (Å) 11 10.5 9.8 9.5 9 9 9

IS DG (Å) 11.5 11 10 10 10 9.9 9.5 9.5

IS 450 650 830 900 1000 1100 1200 1300 1400

IS 1100 1200 1300 1400 1500 1700 1900

IS 1300 1400 1500 1700 1900 2100 2200 2500

IS Extended Planar Bulk (V) 1.1 1.1 1.07 1 1 1 0.975 0.925 0.9

IS UTB FD and DG (V) 1 1 0.95 0.9 0.9 0.9 0.9 0.8 0.8 0.7

IS Extended Planar Bulk (mV) 225 196 175 168 94 103 102 107 112

IS UTB FD (mV) 103 96 88 87 94 97 99

IS DG (mV) 110 105 104 106 109 111 110 109

IS Extended Planar Bulk (µA/µm) 0.13 0.17 0.46 0.71 0.7 0.64 0.69 0.71 0.68

IS UTB FD (µA/µm) 0.33 0.43 0.57 0.62 0.56 0.55 0.57

IS DG (µA/µm) 0.27 0.34 0.37 0.38 0.38 0.4 0.44 0.48

IS Extended Planar Bulk (µA/µm) 1006 1317 1370 1333 1639 1807 1816 1793 1762

IS UTB FD (µA/µm) 1948 1970 1970 1944 2123 2197 2181

IS DG (µA/µm) 1930 1943 2220 2309 2344 2395 2627 2533

IS 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8

IS Extended Planar Bulk 1.07 1.11 1.1 1.09 1.08 1.08 1.09 1.09 1.08

Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion).

MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted)



EOTelec: Electrical Equivalent Oxide Thickness in inversion [4]

Jg,limit: Maximum gate leakage current density [5]

Extended Planar Bulk (A/cm2)

UTB FD (A/cm2)

DG (A/cm2)


Vt,sat: Saturation Threshold Voltage [7]

Isd,leak: Source/Drain Subthreshold Off-State Leakage Current [8]

Id,sat: NMOS Drive Current [9]

Mobility enhancement factor due to strain [10]

Id,sat enhancement factor due to strain [11]

ORTCINDEX

2007 ITRS Chapters

IS UTB FD 1.07 1.07 1.06 1.06 1.06 1.05 1.05

IS DG 1.04 1.04 1.04 1.03 1.03 1.03 1.03 1.03

Effective Ballistic Enhancement Factor, Kbal [12]

IS Extended Planar Bulk 1 1 1 1 1 1 1 1 1

IS UTB FD 1.05 1.08 1.13 1.16 1.2 1.23 1.25

IS DG 1.21 1.25 1.32 1.35 1.42 1.57 1.67 1.87

IS Extended Planar Bulk (Ω-µm) 200 200 200 200 200 180 180 180 180

IS UTB FD (Ω-µm) 180 180 180 180 170 160 160

IS DG (Ω-µm) 180 180 170 160 160 160 160 150

IS Extended Planar Bulk (fF/µm) 0.515 0.700 0.652 0.637 0.663 0.670 0.671 0.652 0.633

IS UTB FD (F/µm) 0.565 0.559 0.530 0.508 0.490 0.449 0.410

IS DG (F/µm) 0.450 0.439 0.441 0.404 0.370 0.340 0.327 0.291

IS Extended Planar Bulk (fF/µm) 0.721 0.875 0.818 0.794 0.843 0.840 0.838 0.814 0.793

IS UTB FD (F/µm) 0.808 0.765 0.700 0.678 0.650 0.609 0.570

IS DG (F/µm) 0.640 0.629 0.621 0.583 0.550 0.520 0.507 0.481

τ =CV/I: NMOSFET intrinsic delay (ps) [16]

IS Extended Planar Bulk (ps) 0.79 0.73 0.64 0.60 0.51 0.46 0.45 0.42 0.4

IS UTB FD (ps) 0.41 0.39 0.34 0.31 0.28 0.25 0.22

IS DG (ps) 0.32 0.29 0.26 0.23 0.2 0.17 0.15 0.13

1/τ: NMOSFET intrinsic switching speed (GHz) [17]

IS Extended Planar Bulk (GHz) 1268 1368 1565 1679 1961 2174 2250 2413 2500

IS UTB FD (GHz) 2439 2610 3002 3226 3649 4076 4472

IS DG (GHz) 3195 3448 3938 4441 5000 5890 6667 7692




Rsd: Effective Parasitic series source/drain resistance [13]

Cg,ideal: Ideal NMOS Device Gate Capacitance [14]

Cg,total: Total gate capacitance for calculation of CV/I [15]

Table PIDS3a and b Low Standby Power Technology Requirements

Year in Production 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

59 52 45 40 36 32 28 25 22 20 18 16 14 13 11

29 27 24 22 20 18 17 15 14 12.8 11.7 10.7 9.7 8.9 8.1

IS Extended Planar Bulk and DG (nm) 38 32 29 27 22 18 17 15 14.0 12.8 11.7 10.7 9.7 8.9 8.1

IS UTB FD (nm) 20 18 17 16 15


Extended planar bulk (Å) 16 15 14 13 12 11

IS UTB FD (Å) 12 11 10 9 8

IS DG (Å) 11 11 10 10 9 9 8 8


IS Extended planar bulk (Å) 6.0 3.4 3.3 3.2 3.1 3.1

IS UTB FD (Å) 4 4 4 4 4

IS DG (Å) 4 4 4 4 4 4 4 4

IS Extended planar bulk (Å) 22 18.4 17.3 16.2 15.1 14.1

IS UTB FD (Å) 16 15 14 13 12

IS DG (Å) 15 15 14 14 13 13 12 12

81 94 110 120 140 150

IS UTB FD (A/cm2) 150 170 180 190 200

IS DG (A/cm2) 190 210 230 250 270 300 330 380

Extended Planar Bulk (V) 1.1 1 1 1 1 0.95

IS UTB FD (V) 0.9 0.9 0.85 0.8 0.8

IS DG (V) 0.8 0.8 0.8 0.8 0.75 0.75 0.7 0.7

Extended Planar Bulk (mV) 567 535 535 544 552 547

IS UTB FD (mV) 399 401 404 404 405

IS DG (mV) 366 366 371 365 374 378 369 376

Extended Planar Bulk (pA/µm) 30.3 30.5 30.7 30.2 30.2 30.3

IS UTB FD (µA/µm) 30.9 31.7 30.2 31.0 32.7

IS DG (µA/µm) 26.5 29.7 25.5 33.8 26.2 23.9 33.8 28.9

IS Extended Planar Bulk (µA/µm) 499 501 528 542 560 519

IS UTB FD (µA/µm) 669 744 786 771 838

IS DG (µA/µm) 702 738 839 889 895 935 934 946


Extended Planar Bulk 1.8 1.8 1.8 1.8 1.8 1.8

IS UTB FD and DG 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8

Extended Planar Bulk 1.17 1.16 1.17 1.17 1.16 1.17




Lg: Physical gate length for LSTP [1]



Extended Planar Bulk (mA/cm2)






ORTCINDEX

2007 ITRS Chapters

IS UTB FD 1.07 1.07 1.07 1.08 1.07

IS DG 1.05 1.04 1.04 1.04 1.04 1.04 1.04 1.04

Effective Ballistic Enhancement Factor [12]

Extended Planar Bulk 1 1 1 1 1 1

IS UTB FD 1 1 1.1 1.15 1.18

IS DG 1.1 1.15 1.22 1.27 1.4 1.45 1.5 1.55

Extended Planar Bulk (Ω-µm) 180 180 180 180 180 180

IS UTB FD (Ω-µm) 200 180 160 150 150

IS DG (Ω-µm) 200 200 180 180 170 160 140 140

IS Extended Planar Bulk (fF/µm) 0.581 0.601 0.558 0.532 0.502 0.490

IS UTB FD (F/µm) 0.431 0.414 0.419 0.425 0.431

IS DG (F/µm) 0.368 0.322 0.320 0.296 0.292 0.265 0.259 0.230


IS UTB FD (F/µm) 0.671 0.654 0.639 0.625 0.631

IS DG (F/µm) 0.608 0.562 0.560 0.526 0.502 0.465 0.449 0.420

τ =CV/I: NMOSFET intrinsic delay (ps) [16]

Extended Planar Bulk (ps) 1.74 1.64 1.46 1.35 1.24 1.23

IS UTB FD (ps) 0.9 0.79 0.69 0.65 0.6

IS DG (ps) 0.69 0.61 0.53 0.47 0.42 0.37 0.34 0.31


Extended Planar Bulk (GHz) 575 610 685 741 806 813

IS UTB FD (GHz) 1111 1266 1449 1538 1667

IS DG (GHz) 1449 1639 1887 2128 2381 2703 2941 3226







Table PIDS3c and d Low Operating Power Technology Requirements

Year in Production 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022

59 52 45 40 36 32 28 25 22 20 18 16 14 13 11

IS 29 27 24 22 20 18 17 15 14 12.8 11.7 10.7 9.7 8.9 8.1

WAS 28 25 22 20 18 16 14 13 11 10 9 8 7 6.5 6

IS 32 29 27 24 22 18 17 15 14 12.8 11.7 10.7 9.7 8.9 8.1


IS Extended planar bulk (Å) 12 11 10 10 9 8

IS UTB FD (Å) 9 8.5 8 8 8 7.3

IS DG (Å) 8.5 8 8 8 7.5 7 7 7



IS UTB FD (Å) 4 4 4 4 4 4

IS DG (Å) 4 4 4 4 4 4 4 4


IS UTB FD (Å) 13 12.5 12 12 11.9 11.4

IS DG (Å) 12.5 12 12 12 11.7 11 11 11

IS 78 86 95 100 110 140

IS 140 150 170 180 200 220

IS 170 180 200 220 230 260 280 310

IS Extended Planar Bulk (V) 0.8 0.8 0.8 0.77 0.7 0.7

IS UTB FD (V) 0.7 0.65 0.6 0.6 0.59 0.54

IS DG (V) 0.6 0.6 0.6 0.6 0.57 0.5 0.5 0.5

IS Extended Planar Bulk (mV) 310 313 322 336 259 249

IS UTB FD (mV) 209 202 199 202 201 193

IS DG (mV) 202 201 202 202 198 190 194 190

IS Extended Planar Bulk (nA/µm) 9.08 7.78 7.89 12.1 18.3 35.7

IS UTB FD (µA/µm) 11.9 16.1 19.4 18.6 21.5 31.0

IS DG (µA/µm) 9.66 10.7 11.2 12.4 15.9 21.4 20.0 24.9

IS Extended Planar Bulk (µA/µm) 541 634 651 600 682 760

IS UTB FD (µA/µm) 788 768 755 763 801 749

IS DG (µA/µm) 790 826 895 908 884 821 855 895




Lg: Physical gate length for LOP (nm) [1]

Lg: Physical gate length for LOP (nm) [1]



Extended Planar Bulk (A/ cm2)

UTB FD (A/ cm2)

DG (A/ cm2)





ORTCINDEX

2007 ITRS Chapters

2008INDEX

1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8

IS Extended Planar Bulk 1.15 1.15 1.15 1.15 1.11 1.09

IS UTB FD 1.07 1.07 1.07 1.06 1.06 1.06

IS DG 1.05 1.05 1.04 1.04 1.04 1.04 1.04 1.04

Effective Ballistic Enhancement Factor [12]

IS Extended Planar Bulk 1 1 1 1 1 1

IS UTB FD 1 1.05 1.1 1.1 1.16 1.21

IS DG 1.17 1.18 1.25 1.26 1.29 1.37 1.43 1.45

IS Extended Planar Bulk (Ω-µm) 190 190 190 190 190 190

IS UTB FD (Ω-µm) 190 185 175 170 165 162

IS DG (Ω-µm) 180 180 170 170 166 154 149 141


IS UTB FD (F/µm) 0.478 0.469 0.431 0.402 0.368 0.335

IS DG (F/µm) 0.414 0.402 0.368 0.336 0.315 0.304 0.279 0.254


IS UTB FD (F/µm) 0.688 0.674 0.631 0.602 0.550 0.529

IS DG (F/µm) 0.654 0.643 0.608 0.576 0.546 0.511 0.478 0.445

τ = CV/I: NMOSFET intrinsic delay (ps) [16]

IS Extended Planar Bulk (ps) 1.17 1.10 1.07 1.01 0.83 0.69

IS UTB FD (ps) 0.61 0.57 0.5 0.47 0.41 0.38

IS DG (ps) 0.5 0.47 0.41 0.38 0.35 0.31 0.28 0.24


IS Extended Planar Bulk (GHz) 857 912 939 988 1205 1449

IS UTB FD (GHz) 1639 1763 2008 2128 2473 2660

IS DG (GHz) 2008 2128 2473 2660 2882 3259 3631 4107









Table PIDS4 DRAM Technology Requirements

Year in Production 2007 2008 2009 2010

DRAM ½ Pitch (nm) [1] 68 58 50 45

0.0277 0.0202 0.015 0.0122

1.2 0.9 0.8 0.6

DRAM storage node cell capacitor voltage (V) [4] 0.65 0.65 0.6 0.6

Equivalent Electric field of capacitor dielectric, (MV/cm) [5] 5.7 7.2 7.5 10

DRAM cell FET structure [6] RCAT RCAT RCAT FinFET

5 5 4.5 4

Maximum Wordline (WL) level (V) [8] 3 2.8 2.7 2.7

Negative Wordline (WL) use [9] yes yes yes yes

Equivalent Electric field of cell FET device dielectric (MV/cm) [10] 6 5.6 6 6.75

Cell Size Factor: a [11] 6 6 6 6

Array Area Efficiency [12] 0.56 0.56 0.56 0.56

Minimum DRAM retention time (ms) [13] 64 64 64 64

DRAM soft error rate (fits) [14] 1000 1000 1000 1000

1.3 1.2 1.1 1.1

Support nMOS EOT [nm] [16] 3.2 3 2.6 2.6

Support PMOS Gate Electrode [17] P+Poly/W P+Poly/W P+Poly/W P+Poly/W

Support Gate Oxide [18] SiON SiON SiON SiON

100 90 75 75

500 465 470 450

0.4 0.4 0.38 0.37

220 210 220 210

-0.45 -0.4 -0.38 -0.38

Notes for Table PIDS4a and b:

[4] The DRAM storage node capacitor voltage must be low enough that the resulting electric field in the dielectric (see Note [5]) is within acceptable limits.

DRAM cell size (µm2) [2]

DRAM storage node cell capacitor dielectric: equivalent oxide thickness EOT (nm) [3]

DRAM cell FET dielectric: equivalent oxide thickness, EOT (nm) [7]

Vint (support FET voltage) [V] [15]

Support min. Lgate for NMOS FET, physical [nm] [19]

Support Isat-n [µA/µm] (25C, Vg=Vd=Vint) [20]

Support min. Vtn (25C, Gm,max, Vd=55mV) [21]

Support Isat-p [µA/µm] (25C, Vg=Vd=-Vint) [22]

Support min. Vtp (25C, Gm,max, Vd=55mV) [23]

[1] From ORTC (Overall Roadmap Technology Characteristics) Table 1a and b. These DRAM half pitch numbers are the same as those in the 2006 ITRS due to no further speed up in the pace of DRAM half pitch scaling during 2006.

[2] The DRAM cell size is driven by the values for DRAM capacity (bits per chip) and chip size, as discussed in more detail in the Front End Process chapter. The capacity and chip size numbers are based on the ORTC Tables 1a and 1b. Since the DRAM capacity and chip size numbers are quite aggressive, the cell size must also be scaled aggressively. The difficulty will lie in reducing the value of the cell size factor “a”, where “a” equals (cell size /F2) and F is the DRAM half pitch. The required values of “a” are 6 for 68 nm and beyond.

[3] Storage node cell dielectric EOT is defined as (dielectric physical thickness / [κ/3.9]), where κ is the relative dielectric constant of the storage node cell dielectric and 3.9 is the relative dielectric constant of thermal SiO2. The value of EOT is driven by the values for DRAM capacity (bits per chip) and chip size, as discussed in more detail in the Front End Process chapter. The capacity and the chip size numbers used by FEP are from the ORTC Tables 1a and 1b. Since the values of DRAM capacity and chip size from FEP are quite aggressive, the EOT must also be scaled very aggressively. Up to 2009, the dielectric material is based on Al2O3 or HfO2, and hence the color is white. Beyond 2009, breakthroughs such as MIM structure with higher κ insulator material of epsilon more than 40 and physical thickness of less than 9nm are needed, so the color is yellow. Finally, for 2012 and beyond, there are no known solutions with demonstrated credibility, and hence the color is red. The actual EOT required for each year also depends on other factors such as cell height and/or 3D structure, film leakage current and contact formation.

ORTCINDEX

2007 ITRS Chapters

2008INDEX

[14] This is a typical FIT rate and depends on cycle time and the quality of cell capacitor and sensing circuits.

[17] Support PMOS FET Gate electrode material migrates from P+Poly/W to TiN.

[18] DRAM support MOS FET dielectric material migrates from SiON to HfSiON in order to leakage current to meet.

[5] The equivalent electric field in the capacitor dielectric is (DRAM storage node capacitor voltage / DRAM storage node dielectric equivalent oxide thickness, EOT). The equivalent field is the electric field if the dielectric is silicon dioxide; if the dielectric is high-k, the actual electric field is [equivalent field]/[k/3.9]. Note the sharp increase in the equivalent field with scaling. The color turns yellow in 2009, when the field is 7.5 MV/cm, and red in 2012, when the field becomes 13.75 MV/cm..

[6] DRAM cell MOSFET structure migrates from RCAT (recessed channel array transistor) to FinFET. RCAT is a technology to improve retention time characteristics by introducing recessed channel structure. FinFET is used to increase the drive current in the limited cell FET area and also to improve retention time characteristics.

[7] DRAM cell FET dielectric EOT is defined as (dielectric physical thickness / [κ/3.9]), where κ is the relative dielectric constant of the DRAM cell FET dielectric and 3.9 is the relative dielectric constant of thermal SiO2. The EOT values here are large, mainly because of the high word line voltage levels (see Note 8) and the need to keep the electric field in the dielectric within tolerable limits (see Note 9)

[8] Maximum word line level is the (highly boosted) gate voltage for cell FET devices. The high gate voltage is required to get enough device drive current with high threshold voltage due to back gate voltage at the operating condition.

[9] Negative word line is used to suppress sub-threshold leakage current of cell transistor even in the case of lower level of V t value of cell FET. The low Vt is preferable to get higher drive current of cell FET.

[10] The equivalent electric field in the cell FET device dielectric is (maximum word line level / DRAM cell FET dielectric equivalent oxide thickness, EOT). The equivalent field is the electric field if the dielectric is silicon dioxide; if the dielectric is high-k, the actual field is [equivalent field]/[k/3.9].

[11] Cell size factor = a = (DRAM cell size/F2), where F is the DRAM ½ pitch. The required values of a are 6 for 2007 and beyond. In contrast, the 2005 version of the DRAM table has a = 8 in 2005, 2006 and 2007.

[12] Array area efficiency is the ratio of cell array area to total chip area. Hence, array area efficiency = 1 / (1 + [peripheral circuit area]/NaF2), where N is the DRAM capacity (number of bits per chip), F is the DRAM ½ pitch, and a is the cell size factor (see Note 9). For a = 8, array area efficiency is estimated to be 0.63, so when a is decreased to 6 from 2007, the array area efficiency of 0.56 is made in conjunction with a = 6, assuming the same relative peripheral circuit area.

[13] Retention time is defined at 85ºC, and is the minimum time during which the data from memory can still be sensed correctly without refreshing a row bit line. The 64 ms specified here is the value needed for PC applications. The retention time depends on the combined interaction of device leakage current, signal strength, and signal sensing circuit sensitivity, and also depends on operational frequency and temperature.

[15] Vint is the nominal power supply voltage for DRAM support FET in peripheral circuit area. It has been chosen to maintain sufficient voltage over-drive in order to meet the required saturation current drive values while still maintaining reasonable vertical gate dielectric electric field strengths.

[16] DRAM support MOS FET dielectric EOT is defined as (dielectric physical thickness / [κ/3.9]), where κ is the relative dielectric constant of the DRAM cell FET dielectric and 3.9 is the relative dielectric constant of thermal SiO2.

[19] Physical support min. Lgate for NMOS FET is the final, as-etched length of the bottom of the gate electrode.

[20] Support Isat-n (the saturation drive current for support NMOS FET) is defined as the NMOSFET drain current per micron device width with the gate bias and the drain bias set equal to V int

(see Note [15]) and the source and substrate biases set to zero at 25°C, namely Vg=Vd=Vint).

[21] Support min Vtn is the saturation threshold voltage measured at 25°C, Gm max,Vd=55mV.

[22] Support Isat-p (the saturation drive current for support PMOS FET) is defined as the PMOSFET drain current per micron device width with the gate bias and the drain bias set equal to -

Vint (see Note [15]) and the source and substrate biases set to zero at 25°C ,namely, Vg=Vd=-Vint).

[23] Support min Vtp is the saturation threshold voltage measured at 25°C, Gm max,Vd=55mV.

2011 2012 2013 2014 2015 2016 2017 2018 2019

40 36 32 30 25 22 20 18 16

0.0096 0.0078 0.0061 0.0054 0.0038 0.0029 0.0024 0.0019 0.00154

0.5 0.4 0.3 0.3 0.3 0.3 0.3 0.3 0.25

0.55 0.55 0.5 0.5 0.45 0.45 0.4 0.4 0.35

11 13.8 16.7 16.7 15 15 13.3 13.3 14

FinFET FinFET FinFET FinFET FinFET FinFET FinFET FinFET FinFET

4 4 4 4 4 3.5 3.5 3.5 3.5

2.7 2.7 2.6 2.6 2.4 2.3 2.3 2.3 2

yes yes yes yes yes yes yes yes yes

6.75 6.75 6.5 6.5 6 6.57 6.57 6.57 5.71

6 6 6 6 6 6 6 6 6

0.56 0.56 0.56 0.56 0.56 0.56 0.56 0.56 0.56

64 64 64 64 64 64 64 64 64

1000 1000 1000 1000 1000 1000 1000 1000 1000

1.1 1.1 1.1 1 0.9 0.9 0.9 0.9 0.9

2.5 2.2 2 1.8 1.6 1.5 1.4 1.4 1.3

P+Poly/W P+Poly/W P+Poly/W TiN TiN TiN TiN TiN TiN

SiON SiON HfSiON HfSiON HfSiON HfSiON HfSiON HfSiON HfSiON

65 60 50 48 40 35 31 28 25

410 430 450 440 480 550 550 550

0.37 0.33 0.33 0.31 0.31 0.31 0.31 0.31 0.31

165 170 175 170 190 215 215 215 215

-0.38 -0.34 -0.34 -0.32 -0.32 -0.32 -0.32 -0.32 -0.32


[4] The DRAM storage node capacitor voltage must be low enough that the resulting electric field in the dielectric (see Note [5]) is within acceptable limits.

445

[1] From ORTC (Overall Roadmap Technology Characteristics) Table 1a and b. These DRAM half pitch numbers are the same as those in the 2006 ITRS due to no further speed up in the pace

[2] The DRAM cell size is driven by the values for DRAM capacity (bits per chip) and chip size, as discussed in more detail in the Front End Process chapter. The capacity and chip size numbers are based on the ORTC Tables 1a and 1b. Since the DRAM capacity and chip size numbers are quite aggressive, the cell size must also be scaled aggressively. The difficulty will lie in

) and F is the DRAM half pitch. The required values of “a” are 6 for 68 nm and beyond.

[3] Storage node cell dielectric EOT is defined as (dielectric physical thickness / [κ/3.9]), where κ is the relative dielectric constant of the storage node cell dielectric and 3.9 is the relative . The value of EOT is driven by the values for DRAM capacity (bits per chip) and chip size, as discussed in more detail in the Front End Process chapter. The

capacity and the chip size numbers used by FEP are from the ORTC Tables 1a and 1b. Since the values of DRAM capacity and chip size from FEP are quite aggressive, the EOT must also be , and hence the color is white. Beyond 2009, breakthroughs such as MIM structure with higher κ insulator

material of epsilon more than 40 and physical thickness of less than 9nm are needed, so the color is yellow. Finally, for 2012 and beyond, there are no known solutions with demonstrated credibility, and hence the color is red. The actual EOT required for each year also depends on other factors such as cell height and/or 3D structure, film leakage current and contact formation.

[14] This is a typical FIT rate and depends on cycle time and the quality of cell capacitor and sensing circuits.

[17] Support PMOS FET Gate electrode material migrates from P+Poly/W to TiN.

[18] DRAM support MOS FET dielectric material migrates from SiON to HfSiON in order to leakage current to meet.

[5] The equivalent electric field in the capacitor dielectric is (DRAM storage node capacitor voltage / DRAM storage node dielectric equivalent oxide thickness, EOT). The equivalent field is the actual electric field is [equivalent field]/[k/3.9]. Note the sharp increase in the equivalent field with scaling.

The color turns yellow in 2009, when the field is 7.5 MV/cm, and red in 2012, when the field becomes 13.75 MV/cm..

[6] DRAM cell MOSFET structure migrates from RCAT (recessed channel array transistor) to FinFET. RCAT is a technology to improve retention time characteristics by introducing recessed channel structure. FinFET is used to increase the drive current in the limited cell FET area and also to improve retention time characteristics.

[7] DRAM cell FET dielectric EOT is defined as (dielectric physical thickness / [κ/3.9]), where κ is the relative dielectric constant of the DRAM cell FET dielectric and 3.9 is the relative . The EOT values here are large, mainly because of the high word line voltage levels (see Note 8) and the need to keep the electric field in the dielectric within

[8] Maximum word line level is the (highly boosted) gate voltage for cell FET devices. The high gate voltage is required to get enough device drive current with high threshold voltage due to

[9] Negative word line is used to suppress sub-threshold leakage current of cell transistor even in the case of lower level of V t value of cell FET. The low Vt is preferable to get higher drive

[10] The equivalent electric field in the cell FET device dielectric is (maximum word line level / DRAM cell FET dielectric equivalent oxide thickness, EOT). The equivalent field is the electric

), where F is the DRAM ½ pitch. The required values of a are 6 for 2007 and beyond. In contrast, the 2005 version of the DRAM table has a = 8 in

[12] Array area efficiency is the ratio of cell array area to total chip area. Hence, array area efficiency = 1 / (1 + [peripheral circuit area]/NaF2), where N is the DRAM capacity (number of bits per chip), F is the DRAM ½ pitch, and a is the cell size factor (see Note 9). For a = 8, array area efficiency is estimated to be 0.63, so when a is decreased to 6 from 2007, the array area

[13] Retention time is defined at 85ºC, and is the minimum time during which the data from memory can still be sensed correctly without refreshing a row bit line. The 64 ms specified here is the value needed for PC applications. The retention time depends on the combined interaction of device leakage current, signal strength, and signal sensing circuit sensitivity, and also depends

is the nominal power supply voltage for DRAM support FET in peripheral circuit area. It has been chosen to maintain sufficient voltage over-drive in order to meet the required

[16] DRAM support MOS FET dielectric EOT is defined as (dielectric physical thickness / [κ/3.9]), where κ is the relative dielectric constant of the DRAM cell FET dielectric and 3.9 is the

(the saturation drive current for support NMOS FET) is defined as the NMOSFET drain current per micron device width with the gate bias and the drain bias set equal to V int

[22] Support Isat-p (the saturation drive current for support PMOS FET) is defined as the PMOSFET drain current per micron device width with the gate bias and the drain bias set equal to -

2020 2021 2022

14 13 12

0.00118 0.00101 0.00086

0.2 0.15 0.12

0.35 0.35 0.35

17.5 23.3 29.2

FinFET FinFET FinFET

3.5 3.5 3.5

2 2 2

yes yes yes

5.71 5.71 5.71

6 6 6

0.56 0.56 0.56

64 64 64

1000 1000 1000

0.9 0.7 0.7

1.3 1.3 1.2

TiN TiN TiN

HfSiON HfSiON HfSiON

23 21 19

550 550 550

0.31 0.31 0.31

215 215 215

-0.32 -0.32 -0.32

Table PIDS5 Non-Volatile Memory Technology Requirements

Near-term


DRAM ½ Pitch (nm) (contacted) 65 57 50 45

67 60 54 48

NAND Flash poly 1/2 Pitch (nm) 51 45 40 36

NAND Flash

51 45 40 36

32 32 64 64

Cell type (FG, CT, 3D, etc.) [3] FG FG FG FG/CT

3D NAND number of memory layers 1 1 1 1

A. Floating Gate NAND Flash

4.0/2.0 4.0/2.0 4.0/1.3 4.0/1.0

Tunnel oxide thickness (nm) [5] 6-7 6-7 6-7 6-7

Interpoly dielectric material [6] ONO ONO ONO ONO

Interpoly dielectric thickness (nm) 10-13 10-13 10-13 10-13

Gate coupling ratio (GCR) [7] 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7

Control gate material [8] n-Poly n-Poly n-Poly n-Poly

Highest W/E voltage (V) [9] 17-19 17-19 15-17 15-17

Endurance (erase/write cycles) [10] 1E+05 1E+05 1E+05 1E+05

Nonvolatile data retention (years) [11] 10-20 10-20 10-20 10-20

2 2 3 4

4.0/1.0

Tunnel dielectric material [14] SiO2 or ONO

Tunnel dielectric thickness EOT (nm) 3-4

Blocking dielectric material [15] SiO2 or Al2O3

Blocking dielectric thickness EOT (nm) 6–8

Charge trapping layer material [16] SiN

Charge trapping layer thickness (nm) [17] 5–7

Gate material [18]

Highest W/E voltage (V) 15-17

MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

NAND Flash technology node – F (nm) [1]

Number of word lines in one NAND string [2]

Cell size – area factor a in multiples of F2 SLC/MLC [4]

Maximum number of bits per cell (MLC) [12]

B. Charge trapping NAND Flash (MANOS or Barrier Engineering) [13]

Cell size – area factor a in multiples of F2 SLC/MLC

p-Poly/Metal

ORTCINDEX

2007 ITRS Chapters

2008INDEX

Endurance (erase/write cycles) [19] 1E+05

Nonvolatile data retention (years) [20] 10-20

Maximum number of bits per cell (MLC) 4

NOR Flash

65 57 50 45

A. Floating gate NOR Flash

9-11 9-11 9-11 9-11

Gate length Lg, physical (nm) [26] 130 120 100 90

Tunnel oxide thickness (nm) [27] 8–9 8–9 8–9 8

Interpoly dielectric material [28] ONO ONO ONO ONO

Interpoly dielectric thickness EOT (nm) 13-15 13-15 13-15 13-15

Gate coupling ratio [29] 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7

Highest W/E voltage (V) [30] 7-9 7-9 7-9 7-9

Iread (µA) [31] 25-34 23-31 21-27 20-26

Endurance (erase/write cycles) [32] 1.00E+05 1.00E+05 1.00E+05 1.00E+06

Nonvolatile data retention (years) [33] 10–20 10–20 10–20 10–20

2 2 2 2

CC CC CC CC

SONOS/NROM technology node, F (nm) 65 57 50 45

6-7 6-7 6-7 6-7

3.3/1.6 3.3/1.6 3.3/1.6 3.3/1.6

Gate length Lg, physical (nm) [38] 0.14 0.13 0.12 0.11

Tunnel oxide thickness (nm) [39] 5 5 5 4.5

5-7 5-7 5-7 4-6

7–9 7–9 7–9 6–8

Highest W/E voltage (V) 7-9 7-9 7-9 6-8

Iread (µA) [31] 25-34 23-31 21-27 20-26

Endurance (erase/write cycles) [32] 1.00E+05 1.00E+05 1.00E+05 1.00E+06

Nonvolatile data retention (years) [33] 10–20 10–20 10–20 10–20

4 4 4 4

Non-charge-storage NVM

A. FeRAM (Ferroelectric RAM)

NOR Flash technology node – F (nm) [21]

Cell size – area factor a in multiples of F2 [22], [23], [24], [25]

Maximum number of bits per cell (MLC) [34]

Array architecture (with cell contact (CC) or virtual ground (VG))[ 35]

B. Charge trapping NOR Flash (SONOS/NROM) [36]

SONOS/NROM cell size - area factor a in multiples of F2

Cell size (per bit) – area factor a in multiples of F2 (SLC/MLC) [37]

Charge trapping layer thickness (nm) [40]

Blocking (top) dielectric thickness EOT (nm) [41]

Maximum number of bits per cell (physical 2-bit/cell + MLC) [37]

WAS FeRAM technology node – F (nm) [42] 180 180 180 130

IS FeRAM technology node – F (nm) [42] 180 180 180 150

22 22 22 20

FeRAM cell size ( µm2) 0.713 0.713 0.713 0.450

FeRAM cell structure [44] 2T2C 1T1C 1T1C 1T1C

FeRAM capacitor structure [45] stack stack stack stack

WAS FeRAM capacitor footprint (µm2) [46] 0.330 0.330 0.330 0.200

IS FeRAM capacitor footprint (µm2) [46] 0.330 0.330 0.330 0.20

FeRAM capacitor active area (µm2) [47] 0.330 0.330 0.330 0.20

1.00 1.00 1.00 1.00

Ferro capacitor voltage (V) [49] 1.50 1.50 1.50 1.20

13.5 13.5 13.5 20

1.0E+14 ### ### ###

10 Years 10 Years 10 Years 10 Years

B. MRAM (Magnetic RAM)

MRAM technology node F (nm) [52] 90 65 65 45

20 22 19 20

MRAM typical cell size (µm2) 0.16 0.09 0.08 0.041

MRAM switching field (Oe) [53] 35 35 35 35

MRAM write energy (pJ/bit) [54] 70 35 35 25

MRAM active area per cell (µm2) [55] 0.05 0.025 0.025 0.013

2 1.1 1 0.8

MRAM magnetoresistance ratio(%) [57] 70 70 70 70

MRAM nonvolatile data retention (years) >10 >10 >10 >10

>3e16 >3e16 >3e16 >3e16

>10 >10 >10 >10

C. PCRAM (Phase-Change RAM)

PCRAM technology node F (nm) [58] 72 58 46 40

4.8 4.0 4.0 4.0

15.0 14.0 12.0 11.0

24883 13456 8464 6400

77760 47096 25392 17600

FeRAM cell size – area factor a inmultiples of F2 [43]

FeRAM cap active area/footprint ratio [48]

FeRAM minimum switching chargedensity (µC/cm2) [50]

FeRAM endurance (read/write cycles) [51]

FeRAM nonvolatile data retention(years)

MRAM cell size area factor a in multiples of F2

MRAM resistance-area product (Kohm-(µm2) [56]

MRAM write endurance (read/write cycles)

MRAM endurance – tunnel junction reliability (years at bias) [58]

PCRAM cell size area factor a in multiples of F2 (BJT access device) [59]

PCRAM cell size area factor a in multiples of F2 (nMOSFET access device) [60]

PCRAM typical cell size (nm2) (BJT access device) [61]

PCRAM typical cell size (nm2) (nMOSFET access device) [62]

1 1 2 2

24883 13456 4232 3200

77760 47096 12696 8800

PCRAM storage element CD (nm) [66] 45 36 30 25

373,000 195,000 112,000 64,000

PCRAM reset current (µA) [68] 235 170 130 100

PCRAM set resistance (Kohm) [69] 3.54 4.57 5.68 7.08

1.50E+07 1.50E+07 1.50E+07 1.50E+07

PCRAM BJT emitter area (nm2) [71] 4072 2642 1662 1257

1.5 1.5 1.8 1.8

239 171 108 82

>10 >10 >10 >10

1.0E+08 1.0E+08 1.0E+10 1.0E+10



Interim solutions are known ¿



[1] NAND Flash has surpassed CMOS and DRAM technology since 2005. This entry provides the F value for designs in the indicated time period.

PCRAM number of bits per cell (MLC) [63]

PCRAM typical cell area per bit size (µm2) (BJT access device) [64]

PCRAM typical cell area per bit size (µm2) (nMOSFET access device) [65]

PCRAM phase change volume (nm3) [67]

PCRAM BJT current density (A/cm2) [70]

PCRAM nMOSFET apparent current density for reset (µA/nm) [72]

PCRAM nMOSFET apparent device width (nm) [73]

PCRAM nonvolatile data retention (years) [74]

PCRAM write endurance (read/write cycles) [75]

[2] NAND Flash architecture consists of bit line strings of a number of storage devices. Long bit line strings reduce the overhead for bit line transistors and increase the packing density, however, at the expense of higher overall resistance and consequently lower read current. The number of word lines in a bit line string has increased from 16 to 32 nm.

[3] Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping devices (CT). (Ref: K. Kim, "Technology for sub 50nm DRAM and NAND Flash manufacturing,” in Tech. Digest International Electron Devices Meeting, pp. 539-543, 2005.) The statistical fluctuation limit of storing too few electrons imposes new challenges to data retention (Ref: G. Molas, et al., "Impact of few electron phenomena on floating gate memory reliability,” Tech. Digest 2004 International Electron Devices Meeting, pp. 877-880, 2004.) and 3D integration of multiple layers of devices may be required to continue the scaling. (Refs: S.H. Lee et al., "Three dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30nm node,” Tech. Digest 2006 International Electron Devices Meeting, pp. 37-40, 2006. E-K. Lai, et al., "A multi-layer stackable thin-film transistor (TFT) NAND-type Flash memory,” Tech. Digest 2006 International Electron Devices Meeting, pp. 41-44, 2006.)

[4] The area factor “a” = cell area per bit/F2, so this entry presents the expected range for Flash cell area in multiples of the implementation technology F 2. It is possible to store more than 1 bit of information in a Flash cell but increasing the logic levels from (1, 0) to (11, 10, 00, 01), etc. by using multi-level cell (MLC). Therefore, the area factor includes both single-level cell (SLC) and multi-level cell (MLC) devices.

[9] Low write and erase voltage is desirable but EOT for tunnel oxide and IPD must be decreased to allow lower W/E voltage without compromising W/E speed.

[11] Data retention is controlled by both tunnel oxide integrity and statistical distribution of the number of stored electrons. Both thinner tunnel oxide and fewer number of stored electrons in the long term contribute to the shorter retention forecast.

[18] High work function metal gate is the best to prevent gate injection. However, p-type polysilicon may become an interim solution because of its easy processing, low cost, and reasonably good performance.

[5] The scaling of tunnel oxide for NAND Flash faces the same challenge as that for NOR Flash. However, the use of error code correction (ECC) in NAND tolerates tunnel oxide defects to a higher level than that for NOR, thus allowing tunnel oxide of 6–7 nm. Currently there are no known solutions to scale tunnel oxide significantly below 6 nm.

[6] ONO has been used as the interpoly dielectric (IPD) up to now and will continue in the near future. However, below 40 nm the spacing between floating gates becomes too narrow to fill effectively with ONO and word line polysilicon, and the loss of sidewall control gate to floating gate coupling will severely degrade the gate coupling ratio (GCR) and the device becomes inoperable. Since it is impossible to create additional space, higher dielectric constant IPD or charge trapping (CT) device must be used. Here the path of migrating to high-κ IPD is shown. It is shown in red color since engineering solutions have not been demonstrated yet.

[7] Gate coupling ratio (GCR) is defined as (control gate to floating gate capacitance)/(total floating gate capacitance). GCR represents the fraction of voltage drop across the tunnel oxide and must be higher than 0.6 for the device to function during write and erase operations. High GCR is normally achieved by wrapping the control gate around the sidewalls of the floating gate. This requires tall floating gate and the cross talk along the bit line direction with neighboring cells is a challenge for MLC operation. At below 40 nm , the spacing between floating gates may become too narrow for the IPD and control gate to wrap around and maintaining sufficiently high GCR is a difficult challenge. Planar device with high-κ IPD is a potential solution.

[8] n-type polysilicon (and polycide) gate has been used for the control gate so far and will continue in the near future. The introduction of high-κ IPD, with a lower barrier height to Si, will cause severe gate injection during erase operation and high work function material such as p-type polysilicon or metal gate may have to be adopted.

[10] Write and erase cycling endurance reflects the tunnel oxide damage caused by repeated passing of charges under high electric field. Scaling does not worsen the oxide damage, however, larger array strains the ECC capability and the tolerance for defects is thus reduced. High-κ IPD may also trap charge and cause degradation. Current projection is gradually reduced cycling endurance for future technology. Note that this is not suitable for certain applications, e.g., solid-state drive storage that requires high cycling endurance.

[12] Multi-level cell (MLC) with 4 logic levels (2-bit/cell) is commonly used for NAND Flash today and devices with 8 logic levels (3-bit/cell) and 16 logic levels (4-bit/cell) are being developed. 8-bit/cell MLC device requires 256 logic levels and so far seems beyond reach of current technology, thus no forecast is made for 8-bit/cell MLC even in the long-term years.

[13] MANOS (Metal-Al2O3-Nitride-Oxide-Si) devices use a relatively thin tunnel oxide, a SiN trapping layer for charge storage, Al 2O3 to increase voltage drop across the tunnel oxide and high work function metal gate to stop gate injection. (Ref: C.H. Lee, et al., "A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-giga bit Flash memories,” Tech. Digest 2003 International Electron Devices Meeting, pp. 613-616, 2003.) Barrier engineering uses composite tunneling barriers to allow easy erase operation by substrate hole tunneling, yet prevents low field hole direct tunneling during retention. (Ref: H.T. Lue, et al., "BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability,” Tech. Digest 2005 International Electron Devices Meeting, pp. 555-558, 2005.) Without floating gate GCR and cross talk issues, these two CT approaches promise to help NAND scaling below 30 nm.

[14] Tunnel dielectric for MANOS type device is a relatively thin silicon oxide (3-4nm). Tunnel dielectric for barrier engineered (BE) device may be a composite ONO (e.g., 2 nm/2 nm/2 nm) or other composites such as OAO.

[15] For MANOS device Al2O3 is the preferred blocking oxide since it has a high barrier height. Other composite blocking layers such as AN, ANO, or AHO are also potential candidates. For BE device the blocking oxide may be SiO 2, although Al2O3 and other composite layers may also be used.

[16] SiN is the most common and best known charge trapping layer with relatively deep electron traps that provide good data retention. Other exotic high-κ material with even deeper traps may be used in the long term years. (Ref: A. Chin, et al., "Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention,” Tech. Digest 2005 International Electron Devices Meeting, pp. 165-168, 2005.) Note that for CT device the charge loss mechanism may be mainly substrate hole tunneling in low field and thus deeper traps do not necessarily improve data retention except for high temperature applications.

[17] Trapping efficiency in SiN seems thickness dependent. (Ref: H.T. Lue, et al., Proc. 2007 International Reliability Physics Symposium, 2007). Therefore, thinner SiN or other high-κ trapping layers forecasted for long-term years may suffer from reduced programming efficiency.

[19] The mechanism for endurance degradation for CT devices is not well understood yet. Unlike floating gate device, CT devices are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. Published endurance data seem to indicate similar endurance as floating gate device.

[20] The mechanism for data retention loss for BE device seems understood. (Ref: H.T. Lue, et al., "Reliability model of bandgap engineered SONOS (BE-SONOS),” Tech. Digest 2006 International Electron Devices Meeting, pp. 495-498, 2006.) Data retention mechanism for MANOS device is still not well understood. Published data suggest that data retention is comparable to floating gate devices under certain conditions.

[21] NOR Flash traditionally falls behind CMOS and DRAM but has caught up in recent years and is now on par with DRAM.

[29] The gate coupling ratio (GCR) is the (control gate to floating gate capacitance)/(total floating gate capacitance). GCR must be greater than about 0.6 for proper device operation.

[32] E/W endurance requirements vary with the specifics of an application, but 1E5 cycles have been accepted as the historical minimum acceptable level for a useful NOR product.

[22] High-κ interpoly dielectric is projected at 32 nm and beyond to achieve gate coupling ratio of >0.6 but this offers only limited help to the area factor. (Ref: 2005 Symposium on VLSI Technology, 11B-3, E. S. Cho, et al.,” Hf-silicate Inter-Poly Dielectric Technology for sub 70 nm Body Tied FinFET Flash Memory,” pp. 208-209.)

[23] Although virtual ground (VG) array may significantly decrease the cell size in the near term years (Ref: 2005 Symposium on VLSI Technology, 11B-1, R. Koval, et al. "Flash ETOX Virtual Ground Architecture: A Future Scaling Direction,” pp. 204-205.), this effect has not been included in the current table because VG is radically different from the conventional array and large development effort is needed to implement it and so far there is no industrial consensus to take up this endeavor.

[24] Although non-planar devices (such as FinFET) are being developed for future Flash scaling, their impact has not been included in the current table. The dilemma of filling ONO and control and floating gates in the narrow gap between adjacent vertical devices has not been completely resolved yet.

[25] Both the cell size and the gate length for NOR Flash have been more aggressively scaled recently with an area factor of approximately 10F2. (Refs: 2005 ISSCC, "A 90 nm 512Mb 166 MHz Multilevel Cell Flash Memory with 1.5MBytes/s Programming,” pp. 54-55. 2003 Symposium on VLSI Technology, "Highly Manufacturable 90nm NOR Flash Technology with 0.081µm2 Cell Size,” pp. 91-92. 2004 Symposium on VLSI Technology, "A 70nm NOR Flash Technology with 0.049µm2 Cell Size,” pp. 238-239.)

[26] NOR Flash uses channel hot electron programming which requires steep junction profile to generate, with the consequence of difficulties in controlling the short channel effect, but yet the NOR architecture is vulnerable to device leakage. Since the tunnel oxide thickness cannot be scaled, controlling the short channel effect imposes a very difficult challenge for scaling. The gate length generally is substantially larger than F in recent years. Despite this difficulty, the area factor has been maintained at 10F 2 in recent years (see note 25).

[27] Tunnel oxides must be thick enough to assure retention but thin enough to allow ease of erase/write. This difficult trade-off problem hinders scaling. Tunnel oxides less than 7 nm pose fundamental problems for retention reliability.

[28] ONO has been used as the interpoly dielectric up to now and most likely in the near future. However, at 32 nm and beyond high-κ IPD may be necessary to maintain GCR at 0.6 or above. Currently, the GCR is achieved by wrapping the control gate over the sidewalls of the floating gate thus increasing the control gate to floating gate capacitor area. At 32 nm or below, the gap between adjacent gloating gates becomes too narrow for the ONO and control gate to fill in and this semi-vertical structure will cease to function.

[30] This is the highest voltage relative to ground seen in the cell array, usually supplied by on-chip charge pumping circuits. Low voltage is desired to reduce the charge pumping circuit overhead and simplify processing. The introduction of high-κ IPD will help to reduce the erase voltage.

[31] In principle the read current decreases with scaling at a rate W/(L*Cox) to prevent voltage overdrive (read disturb). Since access time depends critically on the read current and is an important performance parameter for NOR Flash the read current decreases slower than W/(L*Cox) to maintain performance. This may cause read disturb issues in long term years.

[33] Retention is a defect related parameter rather than an intrinsic device characteristic. Improvement in defect control and accumulation of device history is expected to eventually allow specification of 20 years retention. Also, it should become possible to accept a reduced retention specification as a tradeoff for increased E/W endurance.

[34] Cell read out distinguishes between four levels of charge storage to provide two storage bits (Multilevel cell MLC). Progression to 8 or 16 levels is potentially possible but maintaining reasonable V t, read speed and array efficiency beyond 2-bit/cell are challenging. Unlike NAND Flash where density is a key competitive advantage, performance and reliability tend to hold higher importance than density for NOR Flash, thus the pressure to higher level MLC is not as strong as for NAND Flash.

[35] Virtual ground array uses junction isolation and buried diffusion for bit line, thus requires no STI isolation or bit line contact in the cell. In principle the area factor for VG array can be as small as 4F 2, compared to ~ 10F2 for an array with cell STI isolation and contact. The scaling of buried diffusion is a difficult challenge and junction isolation produces more leakage paths and complicates the design. Large R&D effort is needed to implement VG array and overcome its shortcomings to take advantage of its smaller cell size.

[36] Charge trapping device for NOR application uses mainly a SONOS structure and thus often is confused with the conventional SONOS device. Conventional SONOS is more suitable for a NAND array. The device is programmed by Fowler-Nordheim tunneling of electrons from the substrate and the charge is stored in the SiN layer of SONOS. Since the electrons are stored in deep SiN traps it is difficult to de-trap by Fowler-Nordheim tunneling. Instead, a very thin (2–3 nm) tunnel oxide is used to allow substrate hole tunneling into the SiN to erase the device. However, such thin tunnel oxide also allows direct tunneling of holes from the substrate even under weak electric field produced by the stored electrons and good data retention is difficult to achieve. NROM is a device proposed to solve the SONOS problem in a NOR array15. Using channel hot electron to program the cell, electrons are stored in the SiN layer near the edge of S/D junctions. To erase, band-to-band tunneling generated hot holes are injected into the SiN. A relatively thick (4–5 nm) tunnel oxide is adopted and this solves the data retention issue. NROM also has the advantage of storing two bits of information in one device (source side and drain side) and it applies a reverse read method to distinguish the different states. NROM is built on a virtual ground array architecture and has a relatively small cell size. It is used not only for NOR Flash, but also for some data storage applications even though it is not a NAND structure.

[37] CT NOR SLC Flash stores one bit on the source side and one bit on the drain side, or 2-bit/cell. The MLC Flash stores 2 bits on the source side and two bits on the drain side, thus 4-bit/cell.

[39] Because electrons are trapped in deep levels in SiN, the tunnel oxide can be scaled more aggressively than for floating gate device.

[40] Reducing the thickness of charge trapping SiN will reduce the EOT but will degrade trapping efficiency.

[41] Interpoly dielectric must be thick enough to assure retention.

[42] This entry is the critical dimension “F” within the FeRAM cell for stand-alone memory devices (not embedded devices).

[45] The geometry of the capacitor is a key factor in determining cell size. Stacked planar films are expected to be replaced by more efficient 3D structures.

[47] This is the actual effective area of the capacitor. It is larger than the footprint for 3D capacitor because of the utilization of area in the third dimension.

[48] This ratio of the effective area to the footprint gives a measure of the impact of utilization of the third dimension.

[52] MRAM devices are expected to lag the CMOS current technology up until 45 nm half pitch in 2010. This entry provides the F value for designs in the indicated time period.

[53] The MRAM switching field is the magnetic intensity H required to change the direction of magnetization of the cell.

[55] MRAM active bit area is the area of the magnetic material stack within the cell. It represents the “A” in the R*A product.

[38] Although physically storing two bits in the same device, the gate length scaling is not limited by left-right bit interference. The scaling is limited by the same factors for floating gate device - junction breakdown voltage and short channel effect. 4-bit/cell MLC device window, on the other hand, is affected by left-right bit interference and the Lg scaling for MLC may be more gradual than SLC.

[43] This is the area factor “a” = cell size/F2. FeRAM cell size is presented in terms of F2 multiples of the FeRAM implementation technology.

[44] FeRAM cell structures have migrated to one transistor, one capacitor (1T1C) formats. (Refs. J.H. Park, et al., "Fully Logic Compatible (1.6V Vcc, 2 Additional FRAM Masks) Highly Reliable Sub 10F 2 Embedded FRAM with Advanced Direct Via Technology and Robust 100 nm thick MOCVD PZT Technology", 2004 IEDM, 23.7.1, pp. 591-594. Y. M. Kang et al., "Sub-1.2V Operational, 0.15µm/12F 2 Cell FRAM Technologies for Next Generation SoC Applications", 2005 Symposium on VLSI Technology, 6B-4, pp. 102-103.) Other alternative configurations are under investigation such as Chain-FeRAM. (Refs. H. Kanaya et al., "A 0.602µm2 Nestled Chain Cell Structure Formed by One Mask Etching Process for 64Mbit FeRAM,” 2004 Symposium for VLSI Technology, pp. 150-151. N. Nagel et al., "New Highly Scalable 3 Dimensional Chain FeRAM Cell with Vertical Capacitor,” 2004 Symposium on VLSI Technology, pp. 146-147.)

[46] This is the footprint of the capacitor in micrometers squared. It is this area that constitutes the capacitor area contribution to the cell size. For 2005–2006 ~19F 2, for 2007 - 2009 ~16F2, and for 2010–2020 ~10F2 (3D capacitor) are assumed.

[49] This is the operating voltage (Vop) applied to the capacitor. Low voltage operation is a difficult key design issue. Generally the ferroelectric film thickness needs to be decreased in order to reduce the V op, with great technological challenges. (Ref. D. C. Yoo et al., "Highly Reliable 50nm-thick PZT Capacitor and Low Voltage FRAM Device Using Ir/SrRuO2/MOCVD PZT Capacitor Technology", 2005 Symposium on VLSI Technology, 6B-3, pp. 100-101.)

[50] The minimum switching charge density in µC/cm2 is a useful design parameter. It is equal to the cell minimum switching charge divided by the capacitor actual effective area. The capacitor voltage is taken as V op.

[51] FeRAM is a destructive read-out technology, so every read is accompanied by a write to restore the data. Endurance cycles are taken as the sum of all read and all write cycles. For FeRAM to compete with DRAM and SRAM the cycle endurance should be about 1E15. Testing time is a serious concern. Note that operation at 100 MHz for 3 years would accumulate 1E16 cycles.

[54] MRAM switching energy per bit is calculated as (write current * power supply voltage * write time). It is preferred to use the median value of switching energy measured on a multi-megabit array. A good estimate of power drain is (switching energy * number of writes per second).

[56] MRAM resistance-area product (i.e., the R*A product) is an intrinsic property of the magnetic material stack that provides a convenient basis for comparing cells of different sizes. The R*A product can be computed by measuring the effective low state resistance (R low) of the magnetic tunnel junction and multiply it by the active bit area of the magnetic stack.

[58]This is the critical dimension, F.

[61] The expected “typical” PCRAM cell size with BJT access device is presented in micrometers squared.

[62] The expected “typical” PCRAM cell size with nMOSFET access device is presented in micrometers squared.

[63] PCRAM is capable of MLC multi-bit/cell operation since the resistance ratio between amorphous and crystalline state is typically 100–1,000. This entry is the expected number of MLC bits per cell.

[64] The expected cell size per MLC bit for the PCRAM with BJT cell. It is the physical cell size divided by the number of MLC bits per cell.

[65] The expected cell size per MLC bit for the PCRAM with nMOSFET cell. It is the physical cell size divided by the number of MLC bits per cell.

[66] PCRAM phase change element must be substantially smaller than the technology F to have efficiency reset operation with reasonable current. This entry is the expected dimension for the phase change element in nanometers.

[67] PCRAM phase change volume is a key factor for device design and peak power requirement. This entry is the expected phase change volume in nanometer cubed.

[68] This entry is the expected reset current for PCRAM in microamperes.

[69] The set resistance is a key design factor for PCRAM read speed.

[71] This entry is the expected BJT emitter area that can provide the needed reset current, assuming the BJT current density is met.

[73] This entry is the expected nMOSFET gate width that can provide the needed reset current, assuming the MOSFET output current density is met.

[57] MRAM magnetoresistive ratio is calculated as 100*(Rhigh – Rlow)/Rlow. This ratio summarizes the difference between a logic ONE and a logic ZERO, and as such it represents the intrinsic capability of the magnetic stack. The magnetic tunnel junction resistance values are to be measured at low currents.

[59] The area factor “a” = cell area/F2. This entry is the expected PCRAM cell area in multiples of the implementation technology F2. PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. Both BJT and nMOSFET access device cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit.

[60] The area factor “a” = cell area/F2. This entry is the expected PCRAM cell area in multiples of the implementation technology F2. PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. An nMOSFET transistor has larger cell size in the near term years, but offers simple process and low voltage operation. Both BJT and nMOSFET access device cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit.

[70] This entry is the expected current density output from the BJT access device required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger area BJT (which causes larger cell size) and higher output current (which requires higher operation voltage).

[72] This entry is the expected current density output from the nMOSFET access device required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger width nMOSFET (which causes larger cell size) and higher output current (which requires higher operation voltage or less reliable device).

[74] This entry is the expected PCRAM data retention that will allow it to be used as a nonvolatile memory. Data retention mechanism for PCRAM is not yet thoroughly studied. Recent published data indicate >10 years of retention at elevated temperatures. (Refs. S. J. Ahn et al., "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond,” 2004 IEDM, 37.2, pp. 907-910. A. L. Lacaita et al., "Electrothermal and Phase Change Dynamics in Chalcogenide-Based Materials,” 2004 IEDM, 37.3, pp. 911-914.)

[75] This entry is the expected PCRAM W/E cycling endurance. Recent published data indicate cycling endurance from 1E+9 to 1E+13. (Refs. S.J. Ahn et al., "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond,” 2004 IEDM, 37.2, pp. 907-910. S. Lai et al., "Current Status of Phase Change Memory and Its Future,” 2003 IEDM, pp. 255-258.)

Near-term Long-term

2011 2012 2013 2014 2015 2016 2017

40 35 32 28 25 22 20

42 38 34 30 27 24 21

32 28 25 22 20 19 18

32 28 25 22 20 19 18

64 64 64 64 64 64 64

CT CT CT-3D CT-3D CT-3D CT-3D CT-3D

1 1 2 2 2 2 2

4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0

6-7 6-7 6-7 6-7 6-7 4 4

ONO High-K High-K High-K High-K High-K High-K

10-13 9-10 9-10 9-10 9-10 9-10 9-10

0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7

n-Poly Metal Metal Metal

15-17 15-17 15-17 15-17 15-17 15-17 15-17

1E+05 1E+05 1E+05 1E+05 1E+05 1E+04 1E+04

10-20 10-20 10-20 10-20 10-20 5-10 5-10

4 4 4 4 4 4 4

4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0

SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO

3-4 3-4 3-4 3-4 3-4 3-4 3-4

SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3

6–8 6–8 6–8 6–8 6–8 6–8 6–8

SiN SiN SiN SiN SiN SiN / High-K SiN / High-K

5–7 5–7 5–7 5–7 4–6 4–6 4–6

Metal Metal Metal

15-17 15-17 15-17 15-17 15-17 15-17 15-17

Poly/metal

Poly/metal

Poly/metal

p-Poly/Metal

p-Poly/Metal

p-Poly/Metal

p-Poly/Metal

1E+05 1E+05 1E+05 1E+05 1E+05 1E+04 1E+04

10-20 10-20 10-20 10-20 10-20 5-10 5-10

4 4 4 4 4 4 4

40 35 32 28 25 22 20

9-11 9-11 9-11 9-11 9-11 10-13 10-13

80 70 64 56 50 44 40

8 8 8 7 - 8 7 - 8 7 - 8 7 - 8

ONO ONO High-K High-K High-K High-K High-K

13-15 13-15 8-10 8-10 8-10 8-10 8-10

0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7 0.6–0.7

7-9 7-9 6-8 6-8 6-8 6-8 6-8

19-25 17-22 15-20 14-19 13-18 12–17 11–16

1.00E+06 1.00E+06 1.00E+06 1.00E+06 1.00E+06 1.00E+07 1.00E+07

10–20 10–20 20 20 20 20 20

2 2 2 2 2 2 2

CC CC CC/VG CC/VG CC/VG CC/VG CC/VG

40 35 32 28 25 22 20

7-8 7-8 7-8 7-8 8-9 8-9 8-9

3.7/1.9 3.7/1.9 3.7/1.9 3.7/1.9 4.3/2.2 4.3/2.2 4.3/2.2

0.11 0.1 0.1 0.09 0.09 0.08 0.08

4.5 4.5 4 4 4 4 4

4-6 4-6 4-6 4-6 4-5 4-5 4-5

6–8 6–8 6–8 6–8 5–7 5–7 5–7

6-8 6-8 6-8 5–7 5–7 5–7 5–7

19-25 17-22 15-20 14-19 13-18 12–17 11–16

1.00E+06 1.00E+06 1.00E+06 1.00E+06 1.00E+06 1.00E+06 1.00E+06

10–20 10–20 10–20 10–20 10–20 10–20 10–20

4 4 4 4 6 6 6

130 130 90 90 90 90 90

150 150 130 130 130 90 90

20 20 16 16 16 14 14

0.450 0.450 0.270 0.270 0.270 0.113 0.113

1T1C 1T1C 1T1C 1T1C 1T1C 1T1C 1T1C

stack stack stack stack stack 3D 3D

0.200 0.200 0.106 0.106 0.106 0.041 0.041

0.20 0.20 0.106 0.106 0.106 0.041 0.041

0.20 0.20 0.106 0.106 0.106 0.100 0.100

1.00 1.00 1.00 1.00 1.00 2.46 2.46

1.20 1.20 1.20 1.20 1.20 1.00 1.00

20 20 34.0 34.0 34.0 30 30

### ### ### ### ### >1.0E16 >1.0E16

10 Years 10 Years 10 Years 10 Years 10 Years 10 Years 10 Years

45 45 32 32 32 22 22

18 18 19 17 17 18 16

0.036 0.036 0.019 0.017 0.017 0.009 0.0077

35 35 35 35 35 35 35

25 25 20 20 20 20 20

0.013 0.013 0.009 0.009 0.009 0.007 0.007

0.8 0.8 0.6 0.6 0.6 0.6 0.6

70 70 70 70 70 70 70

>10 >10 >10 >10 >10 >10 >10

>3e16 >3e16 >3e16 >3e16 >3e16 >3e16 >3e16

>10 >10 >10 >10 >10 >10 >10

35 32 28 25 22 20 18

4.0 4.0 4.0 4.0 4.0 4.0 4.0

10.0 8.9 8.8 8.4 7.4 7.3 7.3

4900 4096 3136 2500 1936 1600 1296

12250 9114 6899 5250 3582 2920 2365

2 4 4 4 4 4 4

2450 1024 784 625 484 400 324

6125 2278 1725 1313 895 730 591

22 20 18 16 14 13 12

43,000 33,000 25,000 18,000 12,000 9,000 6,700

80 70 62 52 43 37 32

8.29 9.21 10.20 11.66 13.56 15.17 17.18

1.50E+07 1.50E+07 1.50E+07 1.60E+07 1.70E+07 1.90E+07 2.00E+07

962 804 616 491 380 314 254

1.8 2.1 2.1 2.1 2.4 2.4 2.4

68 51 43 36 26 23 21

>10 >10 >10 >10 >10 >10 >10

1.0E+10 1.0E+12 1.0E+12 1.0E+12 1.0E+15 1.0E+15 1.0E+15


[2] NAND Flash architecture consists of bit line strings of a number of storage devices. Long bit line strings reduce the overhead for bit line transistors and increase the packing density, however, at the expense of higher overall resistance and consequently lower read

[3] Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping devices (CT). (Ref: K. Kim, "Technology for sub 50nm DRAM and NAND Flash manufacturing,” in Tech. Digest International Electron Devices Meeting, pp. 539-543, 2005.) The statistical fluctuation limit of storing too few electrons imposes new challenges to data retention (Ref: G. Molas, et al., "Impact of few electron phenomena on floating gate memory reliability,” Tech. Digest 2004 International Electron Devices Meeting, pp. 877-880, 2004.) and 3D integration of multiple layers of devices may be required to continue the scaling. (Refs: S.H. Lee et al., "Three dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30nm node,” Tech. Digest 2006 International Electron Devices Meeting, pp. 37-40, 2006. E-K. Lai, et al., "A multi-layer stackable thin-film transistor (TFT) NAND-type Flash memory,” Tech. Digest 2006 International Electron Devices Meeting, pp. 41-44, 2006.)

, so this entry presents the expected range for Flash cell area in multiples of the implementation technology F 2. It is possible to store more than 1 bit of information in a Flash cell but increasing the logic levels from (1, 0) to (11, 10, 00, 01), etc. by using multi-level cell (MLC). Therefore, the area factor includes both single-level cell (SLC) and multi-level cell (MLC) devices.




[5] The scaling of tunnel oxide for NAND Flash faces the same challenge as that for NOR Flash. However, the use of error code correction (ECC) in NAND tolerates tunnel oxide defects to a higher level than that for NOR, thus allowing tunnel oxide of 6–7 nm. Currently

[6] ONO has been used as the interpoly dielectric (IPD) up to now and will continue in the near future. However, below 40 nm the spacing between floating gates becomes too narrow to fill effectively with ONO and word line polysilicon, and the loss of sidewall control gate to floating gate coupling will severely degrade the gate coupling ratio (GCR) and the device becomes inoperable. Since it is impossible to create additional space, higher dielectric constant IPD or charge trapping (CT) device must be used. Here the path of migrating to high-κ IPD is shown. It is shown in red color since engineering solutions have not been demonstrated yet.

[7] Gate coupling ratio (GCR) is defined as (control gate to floating gate capacitance)/(total floating gate capacitance). GCR represents the fraction of voltage drop across the tunnel oxide and must be higher than 0.6 for the device to function during write and erase operations. High GCR is normally achieved by wrapping the control gate around the sidewalls of the floating gate. This requires tall floating gate and the cross talk along the bit line direction with neighboring cells is a challenge for MLC operation. At below 40 nm , the spacing between floating gates may become too narrow for the IPD and control gate to wrap around and maintaining sufficiently high GCR is a difficult challenge. Planar device with high-κ IPD is a potential solution.

[8] n-type polysilicon (and polycide) gate has been used for the control gate so far and will continue in the near future. The introduction of high-κ IPD, with a lower barrier height to Si, will cause severe gate injection during erase operation and high work function


[12] Multi-level cell (MLC) with 4 logic levels (2-bit/cell) is commonly used for NAND Flash today and devices with 8 logic levels (3-bit/cell) and 16 logic levels (4-bit/cell) are being developed. 8-bit/cell MLC device requires 256 logic levels and so far seems beyond reach

[13] MANOS (Metal-Al2O3-Nitride-Oxide-Si) devices use a relatively thin tunnel oxide, a SiN trapping layer for charge storage, Al 2O3 to increase voltage drop across the tunnel oxide and high work function metal gate to stop gate injection. (Ref: C.H. Lee, et al., "A novel with TaN metal gate for multi-giga bit Flash memories,” Tech. Digest 2003 International Electron Devices Meeting, pp. 613-616, 2003.) Barrier engineering uses composite tunneling barriers to allow easy erase operation by substrate

hole tunneling, yet prevents low field hole direct tunneling during retention. (Ref: H.T. Lue, et al., "BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability,” Tech. Digest 2005 International Electron Devices Meeting, pp. 555-558, 2005.) Without floating gate GCR and cross talk issues, these two CT approaches promise to help NAND scaling below 30 nm.

[14] Tunnel dielectric for MANOS type device is a relatively thin silicon oxide (3-4nm). Tunnel dielectric for barrier engineered (BE) device may be a composite ONO (e.g., 2 nm/2 nm/2 nm) or other composites such as OAO.

is the preferred blocking oxide since it has a high barrier height. Other composite blocking layers such as AN, ANO, or AHO are also potential candidates. For BE device the blocking oxide may be SiO 2, although Al2O3 and other composite

[16] SiN is the most common and best known charge trapping layer with relatively deep electron traps that provide good data retention. Other exotic high-κ material with even deeper traps may be used in the long term years. (Ref: A. Chin, et al., "Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention,” Tech. Digest 2005 International Electron Devices Meeting, pp. 165-168, 2005.) Note that for CT device the charge loss mechanism may be mainly substrate hole tunneling in low field and thus deeper traps do not

[17] Trapping efficiency in SiN seems thickness dependent. (Ref: H.T. Lue, et al., Proc. 2007 International Reliability Physics Symposium, 2007). Therefore, thinner SiN or other high-κ trapping layers forecasted for long-term years may suffer from reduced programming

[19] The mechanism for endurance degradation for CT devices is not well understood yet. Unlike floating gate device, CT devices are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. Published endurance data seem to indicate similar endurance as floating gate device.

[20] The mechanism for data retention loss for BE device seems understood. (Ref: H.T. Lue, et al., "Reliability model of bandgap engineered SONOS (BE-SONOS),” Tech. Digest 2006 International Electron Devices Meeting, pp. 495-498, 2006.) Data retention mechanism for MANOS device is still not well understood. Published data suggest that data retention is comparable to floating gate devices under certain conditions.




[22] High-κ interpoly dielectric is projected at 32 nm and beyond to achieve gate coupling ratio of >0.6 but this offers only limited help to the area factor. (Ref: 2005 Symposium on VLSI Technology, 11B-3, E. S. Cho, et al.,” Hf-silicate Inter-Poly Dielectric Technology

[23] Although virtual ground (VG) array may significantly decrease the cell size in the near term years (Ref: 2005 Symposium on VLSI Technology, 11B-1, R. Koval, et al. "Flash ETOX Virtual Ground Architecture: A Future Scaling Direction,” pp. 204-205.), this effect has not been included in the current table because VG is radically different from the conventional array and large development effort is needed to implement it and so far there is no industrial consensus to take up this endeavor.

[24] Although non-planar devices (such as FinFET) are being developed for future Flash scaling, their impact has not been included in the current table. The dilemma of filling ONO and control and floating gates in the narrow gap between adjacent vertical devices has

[25] Both the cell size and the gate length for NOR Flash have been more aggressively scaled recently with an area factor of approximately 10F2. (Refs: 2005 ISSCC, "A 90 nm 512Mb 166 MHz Multilevel Cell Flash Memory with 1.5MBytes/s Programming,” pp. 54-55. 2003 Symposium on VLSI Technology, "Highly Manufacturable 90nm NOR Flash Technology with 0.081µm2 Cell Size,” pp. 91-92. 2004 Symposium on VLSI Technology, "A 70nm NOR Flash Technology with 0.049µm2 Cell Size,” pp. 238-239.)

[26] NOR Flash uses channel hot electron programming which requires steep junction profile to generate, with the consequence of difficulties in controlling the short channel effect, but yet the NOR architecture is vulnerable to device leakage. Since the tunnel oxide thickness cannot be scaled, controlling the short channel effect imposes a very difficult challenge for scaling. The gate length generally is substantially larger than F in recent years. Despite this difficulty, the area factor has been maintained at 10F 2 in recent years (see

[27] Tunnel oxides must be thick enough to assure retention but thin enough to allow ease of erase/write. This difficult trade-off problem hinders scaling. Tunnel oxides less than 7 nm pose fundamental problems for retention reliability.


[30] This is the highest voltage relative to ground seen in the cell array, usually supplied by on-chip charge pumping circuits. Low voltage is desired to reduce the charge pumping circuit overhead and simplify processing. The introduction of high-κ IPD will help to reduce

[31] In principle the read current decreases with scaling at a rate W/(L*Cox) to prevent voltage overdrive (read disturb). Since access time depends critically on the read current and is an important performance parameter for NOR Flash the read current decreases slower

[33] Retention is a defect related parameter rather than an intrinsic device characteristic. Improvement in defect control and accumulation of device history is expected to eventually allow specification of 20 years retention. Also, it should become possible to accept a

[34] Cell read out distinguishes between four levels of charge storage to provide two storage bits (Multilevel cell MLC). Progression to 8 or 16 levels is potentially possible but maintaining reasonable V t, read speed and array efficiency beyond 2-bit/cell are challenging. Unlike NAND Flash where density is a key competitive advantage, performance and reliability tend to hold higher importance than density for NOR Flash, thus the pressure to higher level MLC is not as strong as for NAND Flash.

[35] Virtual ground array uses junction isolation and buried diffusion for bit line, thus requires no STI isolation or bit line contact in the cell. In principle the area factor for VG array can be as small as 4F 2, compared to ~ 10F2 for an array with cell STI isolation and contact. The scaling of buried diffusion is a difficult challenge and junction isolation produces more leakage paths and complicates the design. Large R&D effort is needed to implement VG array and overcome its shortcomings to take advantage of its smaller cell size.

[36] Charge trapping device for NOR application uses mainly a SONOS structure and thus often is confused with the conventional SONOS device. Conventional SONOS is more suitable for a NAND array. The device is programmed by Fowler-Nordheim tunneling of electrons from the substrate and the charge is stored in the SiN layer of SONOS. Since the electrons are stored in deep SiN traps it is difficult to de-trap by Fowler-Nordheim tunneling. Instead, a very thin (2–3 nm) tunnel oxide is used to allow substrate hole tunneling into the SiN to erase the device. However, such thin tunnel oxide also allows direct tunneling of holes from the substrate even under weak electric field produced by the stored electrons and good data retention is difficult to achieve. NROM is a device proposed to solve the

. Using channel hot electron to program the cell, electrons are stored in the SiN layer near the edge of S/D junctions. To erase, band-to-band tunneling generated hot holes are injected into the SiN. A relatively thick (4–5 nm) tunnel oxide is adopted and this solves the data retention issue. NROM also has the advantage of storing two bits of information in one device (source side and drain side) and it applies a reverse read method to distinguish the different states. NROM is built on a virtual ground array architecture and has a relatively small cell size. It is used not only for NOR Flash, but also for some data storage applications even though it is not a NAND structure.












[38] Although physically storing two bits in the same device, the gate length scaling is not limited by left-right bit interference. The scaling is limited by the same factors for floating gate device - junction breakdown voltage and short channel effect. 4-bit/cell MLC device scaling for MLC may be more gradual than SLC.

multiples of the FeRAM implementation technology.

[44] FeRAM cell structures have migrated to one transistor, one capacitor (1T1C) formats. (Refs. J.H. Park, et al., "Fully Logic Compatible (1.6V Vcc, 2 Additional FRAM Masks) Highly Reliable Sub 10F 2 Embedded FRAM with Advanced Direct Via Technology and Robust 100 nm thick MOCVD PZT Technology", 2004 IEDM, 23.7.1, pp. 591-594. Y. M. Kang et al., "Sub-1.2V Operational, 0.15µm/12F 2 Cell FRAM Technologies for Next Generation SoC Applications", 2005 Symposium on VLSI Technology, 6B-4, pp. 102-103.) Other alternative configurations are under investigation such as Chain-FeRAM. (Refs. H. Kanaya et al., "A 0.602µm2 Nestled Chain Cell Structure Formed by One Mask Etching Process for 64Mbit FeRAM,” 2004 Symposium for VLSI Technology, pp. 150-151. N. Nagel et al., "New Highly Scalable 3 Dimensional Chain FeRAM Cell with Vertical Capacitor,” 2004 Symposium on VLSI Technology, pp. 146-147.)

[46] This is the footprint of the capacitor in micrometers squared. It is this area that constitutes the capacitor area contribution to the cell size. For 2005–2006 ~19F 2, for 2007 - 2009 ~16F2, and for 2010–2020 ~10F2 (3D capacitor) are assumed.

) applied to the capacitor. Low voltage operation is a difficult key design issue. Generally the ferroelectric film thickness needs to be decreased in order to reduce the V op, with great technological challenges. (Ref. D. C. Yoo et al., /MOCVD PZT Capacitor Technology", 2005 Symposium on VLSI Technology, 6B-3, pp. 100-101.)

is a useful design parameter. It is equal to the cell minimum switching charge divided by the capacitor actual effective area. The capacitor voltage is taken as V op.

[51] FeRAM is a destructive read-out technology, so every read is accompanied by a write to restore the data. Endurance cycles are taken as the sum of all read and all write cycles. For FeRAM to compete with DRAM and SRAM the cycle endurance should be about 1E15. Testing time is a serious concern. Note that operation at 100 MHz for 3 years would accumulate 1E16 cycles.

[54] MRAM switching energy per bit is calculated as (write current * power supply voltage * write time). It is preferred to use the median value of switching energy measured on a multi-megabit array. A good estimate of power drain is (switching energy * number of

[56] MRAM resistance-area product (i.e., the R*A product) is an intrinsic property of the magnetic material stack that provides a convenient basis for comparing cells of different sizes. The R*A product can be computed by measuring the effective low state resistance (R low)













. This ratio summarizes the difference between a logic ONE and a logic ZERO, and as such it represents the intrinsic capability of the magnetic stack. The magnetic tunnel junction resistance values

. This entry is the expected PCRAM cell area in multiples of the implementation technology F2. PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. Both BJT and nMOSFET access device cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit.

. This entry is the expected PCRAM cell area in multiples of the implementation technology F2. PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. An nMOSFET transistor has larger cell size in the near term years, but offers simple process and low voltage operation. Both BJT and nMOSFET access device cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit.

[70] This entry is the expected current density output from the BJT access device required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger area BJT (which causes larger cell size) and higher output current (which requires

[72] This entry is the expected current density output from the nMOSFET access device required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger width nMOSFET (which causes larger cell size) and higher output current


[75] This entry is the expected PCRAM W/E cycling endurance. Recent published data indicate cycling endurance from 1E+9 to 1E+13. (Refs. S.J. Ahn et al., "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond,” 2004 IEDM, 37.2, pp. 907-910. S. Lai et al., "Current Status of Phase Change Memory and Its Future,” 2003 IEDM, pp. 255-258.)

Long-term

2018 2019 2020 2021 2022

18 16 14 12 10

19 17 15 13 11

16 14 13 11 10

16 14 13 11 10

64 64 64 64 64

CT-3D CT-3D CT-3D CT-3D CT-3D

4 4 4 4 4

4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0

4 4 4 4 4

High-K High-K High-K High-K High-K

9-10 9-10 9-10 9-10 9-10

0.6–0.7 0.6-0.7 0.6-0.7 0.6-0.7 0.6-0.7

Metal Metal Metal Metal Metal

15-17 15-17 15-17 15-17 15-17

1E+04 1E+04 1E+04 1E+04 1E+04

5-10 5-10 5-10 5-10 5-10

4 4 4 4 4

4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0 4.0/1.0

SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO SiO2 or ONO

3-4 3-4 3-4 3-4 3-4

SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3

6–8 6–8 6–8 6–8 6–8

SiN / High-K SiN / High-K SiN / High-K SiN / High-K SiN / High-K

4–6 4–6 4–6 3-4 3-4

Metal Metal Metal Metal Metal

15-17 15-17 15-17 15-17 15-17

1E+04 1E+04 1E+04 1E+04 1E+04

5-10 5-10 5-10 5-10 5-10

4 4 4 4 4

18 16 14 12 10

10-13 10-13 10-13 10-13 10-13

36 32 28 24 20

7 - 8 7 - 8 7 - 8 7 - 8 7 - 8

High-K High-K High-K High-K High-K

7-9 6-8 6-8 6-8 6-8

0.6–0.7 0.6-0.7 0.6-0.7 0.6-0.7 0.6-0.7

6-8 6-8 6-8 6-8 6-8

10–15 9-14 8-13 7-12 6-10

1.00E+07 1.00E+07 1.00E+07 1.00E+07 1.00E+07

20 20 20 20 20

2 2 2 2 2

CC/VG CC/VG CC/VG CC/VG CC/VG

18 16 14 12 10

8-9 9-10 9-10 9-10 9-10

4.3/2.2 4.8/2.4 4.8/2.4 4.8/2.4 4.8/2.4

0.07 0.07 0.07 0.06 0.06

4 3.5 3.5 3.5 3.5

4-5 4 4 4 4

5–7 5–7 5–7 5–7 5–7

5–7 5–7 5–7 4-6 4-6

10–15 9-14 8-13 7-12 6-10

1.00E+06 1.00E+06 1.00E+06 1.00E+06 1.00E+06

10–20 10–20 10–20 10–20 10–20

6 6 6 6 6

90 65 65 65 65

90 65 65 65 65

14 12 12 12 12

0.113 0.051 0.051 0.051 0.051

1T1C 1T1C 1T1C 1T1C 1T1C

3D 3D 3D 3D 3D

0.041 0.016 0.016 0.016 0.016

0.041 0.016 0.016 0.016 0.016

0.100 0.069 0.069 0.069 0.069

2.46 4.25 4.25 4.25 4.25

1.00 0.70 0.70 0.70 0.70

30 30 30 30 30

>1.0E16 >1.0E16 >1.0E16 >1.0E16 >1.0E16

10 Years 10 Years 10 Years 10 Years 10 Years

22 16 16 16 16

16 17 16 17 16

0.0077 0.0044 0.0041 0.0044 0.0041

35 35 35 35 35

20 20 20 20 20

0.007 0.005 0.005 0.005 0.005

0.6 0.6 0.6 0.6 0.6

70 70 70 70 70

>10 >10 >10 >10 >10

>3e16 >3e16 >3e16 >3e16 >3e16

>10 >10 >10 >10 >10

16 14 12 10 8

4.0 4.0 4.0 4.0 4.0

6.0 6.0 6.0 5.5 5.5

1024 784 576 480 340

1536 1176 864 650 450

4 4 4 4 4

256 196 144 120 85

384 294 216 162 112

10 9 8 8 7

4,700 3,200 2,000 1,300 900

27 22 18 15 13

19.74 23.11 27.72 31.00 35.00

2.10E+07 2.20E+07 2.40E+07 2.50E+07 2.70E+07

201 154 113 91 73

2.88 2.88 2.88 2.88 2.88

16 14 12 10 9

>10 >10 >10 >10 >10

1.0E+15 1.0E+15 1.0E+15 1.0E+15 1.0E+15


[2] NAND Flash architecture consists of bit line strings of a number of storage devices. Long bit line strings reduce the overhead for bit line transistors and increase the packing density, however, at the expense of higher overall resistance and consequently lower read

[3] Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping devices (CT). (Ref: K. Kim, "Technology for sub 50nm DRAM and NAND Flash manufacturing,” in Tech. Digest International Electron Devices Meeting, pp. 539-543, 2005.) The statistical fluctuation limit of storing too few electrons imposes new challenges to data retention (Ref: G. Molas, et al., "Impact of few electron phenomena on floating gate memory reliability,” Tech. Digest 2004 International Electron Devices Meeting, pp. 877-880, 2004.) and 3D integration of multiple layers of devices may be required to continue the scaling. (Refs: S.H. Lee et al., "Three dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30nm node,” Tech. Digest 2006 International Electron Devices Meeting, pp. 37-40, 2006. E-K. Lai, et al., "A multi-layer stackable thin-film transistor

. It is possible to store more than 1 bit of information in a Flash cell but increasing the logic levels from (1, 0) to




[5] The scaling of tunnel oxide for NAND Flash faces the same challenge as that for NOR Flash. However, the use of error code correction (ECC) in NAND tolerates tunnel oxide defects to a higher level than that for NOR, thus allowing tunnel oxide of 6–7 nm. Currently

[6] ONO has been used as the interpoly dielectric (IPD) up to now and will continue in the near future. However, below 40 nm the spacing between floating gates becomes too narrow to fill effectively with ONO and word line polysilicon, and the loss of sidewall control gate to floating gate coupling will severely degrade the gate coupling ratio (GCR) and the device becomes inoperable. Since it is impossible to create additional space, higher dielectric constant IPD or charge trapping (CT) device must be used. Here the path of migrating

[7] Gate coupling ratio (GCR) is defined as (control gate to floating gate capacitance)/(total floating gate capacitance). GCR represents the fraction of voltage drop across the tunnel oxide and must be higher than 0.6 for the device to function during write and erase operations. High GCR is normally achieved by wrapping the control gate around the sidewalls of the floating gate. This requires tall floating gate and the cross talk along the bit line direction with neighboring cells is a challenge for MLC operation. At below 40 nm , the

[8] n-type polysilicon (and polycide) gate has been used for the control gate so far and will continue in the near future. The introduction of high-κ IPD, with a lower barrier height to Si, will cause severe gate injection during erase operation and high work function


[12] Multi-level cell (MLC) with 4 logic levels (2-bit/cell) is commonly used for NAND Flash today and devices with 8 logic levels (3-bit/cell) and 16 logic levels (4-bit/cell) are being developed. 8-bit/cell MLC device requires 256 logic levels and so far seems beyond reach

to increase voltage drop across the tunnel oxide and high work function metal gate to stop gate injection. (Ref: C.H. Lee, et al., "A novel with TaN metal gate for multi-giga bit Flash memories,” Tech. Digest 2003 International Electron Devices Meeting, pp. 613-616, 2003.) Barrier engineering uses composite tunneling barriers to allow easy erase operation by substrate

hole tunneling, yet prevents low field hole direct tunneling during retention. (Ref: H.T. Lue, et al., "BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability,” Tech. Digest 2005 International Electron Devices Meeting, pp. 555-558, 2005.)

, although Al2O3 and other composite

[16] SiN is the most common and best known charge trapping layer with relatively deep electron traps that provide good data retention. Other exotic high-κ material with even deeper traps may be used in the long term years. (Ref: A. Chin, et al., "Low voltage high speed SiO2/AlGaN/AlLaO3/TaN memory with good retention,” Tech. Digest 2005 International Electron Devices Meeting, pp. 165-168, 2005.) Note that for CT device the charge loss mechanism may be mainly substrate hole tunneling in low field and thus deeper traps do not

[17] Trapping efficiency in SiN seems thickness dependent. (Ref: H.T. Lue, et al., Proc. 2007 International Reliability Physics Symposium, 2007). Therefore, thinner SiN or other high-κ trapping layers forecasted for long-term years may suffer from reduced programming

[19] The mechanism for endurance degradation for CT devices is not well understood yet. Unlike floating gate device, CT devices are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to

[20] The mechanism for data retention loss for BE device seems understood. (Ref: H.T. Lue, et al., "Reliability model of bandgap engineered SONOS (BE-SONOS),” Tech. Digest 2006 International Electron Devices Meeting, pp. 495-498, 2006.) Data retention mechanism




[22] High-κ interpoly dielectric is projected at 32 nm and beyond to achieve gate coupling ratio of >0.6 but this offers only limited help to the area factor. (Ref: 2005 Symposium on VLSI Technology, 11B-3, E. S. Cho, et al.,” Hf-silicate Inter-Poly Dielectric Technology

[23] Although virtual ground (VG) array may significantly decrease the cell size in the near term years (Ref: 2005 Symposium on VLSI Technology, 11B-1, R. Koval, et al. "Flash ETOX Virtual Ground Architecture: A Future Scaling Direction,” pp. 204-205.), this effect

[24] Although non-planar devices (such as FinFET) are being developed for future Flash scaling, their impact has not been included in the current table. The dilemma of filling ONO and control and floating gates in the narrow gap between adjacent vertical devices has

[25] Both the cell size and the gate length for NOR Flash have been more aggressively scaled recently with an area factor of approximately 10F2. (Refs: 2005 ISSCC, "A 90 nm 512Mb 166 MHz Multilevel Cell Flash Memory with 1.5MBytes/s Programming,” pp. 54-55. Cell Size,” pp. 91-92. 2004 Symposium on VLSI Technology, "A 70nm NOR Flash Technology with 0.049µm2 Cell Size,” pp. 238-239.)

[26] NOR Flash uses channel hot electron programming which requires steep junction profile to generate, with the consequence of difficulties in controlling the short channel effect, but yet the NOR architecture is vulnerable to device leakage. Since the tunnel oxide thickness cannot be scaled, controlling the short channel effect imposes a very difficult challenge for scaling. The gate length generally is substantially larger than F in recent years. Despite this difficulty, the area factor has been maintained at 10F 2 in recent years (see


[30] This is the highest voltage relative to ground seen in the cell array, usually supplied by on-chip charge pumping circuits. Low voltage is desired to reduce the charge pumping circuit overhead and simplify processing. The introduction of high-κ IPD will help to reduce

[31] In principle the read current decreases with scaling at a rate W/(L*Cox) to prevent voltage overdrive (read disturb). Since access time depends critically on the read current and is an important performance parameter for NOR Flash the read current decreases slower

[33] Retention is a defect related parameter rather than an intrinsic device characteristic. Improvement in defect control and accumulation of device history is expected to eventually allow specification of 20 years retention. Also, it should become possible to accept a

, read speed and array efficiency beyond 2-bit/cell are challenging.

for an array with cell STI isolation and contact. The scaling of buried diffusion is a difficult challenge and junction isolation produces more leakage paths and complicates the design. Large R&D effort is needed to implement VG array and overcome its shortcomings to take advantage of its smaller cell size.

[36] Charge trapping device for NOR application uses mainly a SONOS structure and thus often is confused with the conventional SONOS device. Conventional SONOS is more suitable for a NAND array. The device is programmed by Fowler-Nordheim tunneling of electrons from the substrate and the charge is stored in the SiN layer of SONOS. Since the electrons are stored in deep SiN traps it is difficult to de-trap by Fowler-Nordheim tunneling. Instead, a very thin (2–3 nm) tunnel oxide is used to allow substrate hole tunneling into the SiN to erase the device. However, such thin tunnel oxide also allows direct tunneling of holes from the substrate even under weak electric field produced by the stored electrons and good data retention is difficult to achieve. NROM is a device proposed to solve the

. Using channel hot electron to program the cell, electrons are stored in the SiN layer near the edge of S/D junctions. To erase, band-to-band tunneling generated hot holes are injected into the SiN. A relatively thick (4–5 nm) tunnel oxide is adopted and this solves the data retention issue. NROM also has the advantage of storing two bits of information in one device (source side and drain side) and it applies a reverse read method to distinguish the different states. NROM is built












[38] Although physically storing two bits in the same device, the gate length scaling is not limited by left-right bit interference. The scaling is limited by the same factors for floating gate device - junction breakdown voltage and short channel effect. 4-bit/cell MLC device

Embedded FRAM with Advanced Direct Via Technology and Cell FRAM Technologies for Next Generation SoC Applications", 2005 Symposium on VLSI Technology, 6B-4, pp. 102-103.) Other

Nestled Chain Cell Structure Formed by One Mask Etching Process for 64Mbit FeRAM,” 2004 Symposium for VLSI Technology, pp. 150-151. N. Nagel et al.,

(3D capacitor) are assumed.

, with great technological challenges. (Ref. D. C. Yoo et al.,

[51] FeRAM is a destructive read-out technology, so every read is accompanied by a write to restore the data. Endurance cycles are taken as the sum of all read and all write cycles. For FeRAM to compete with DRAM and SRAM the cycle endurance should be about

[54] MRAM switching energy per bit is calculated as (write current * power supply voltage * write time). It is preferred to use the median value of switching energy measured on a multi-megabit array. A good estimate of power drain is (switching energy * number of

[56] MRAM resistance-area product (i.e., the R*A product) is an intrinsic property of the magnetic material stack that provides a convenient basis for comparing cells of different sizes. The R*A product can be computed by measuring the effective low state resistance (R low)













. This ratio summarizes the difference between a logic ONE and a logic ZERO, and as such it represents the intrinsic capability of the magnetic stack. The magnetic tunnel junction resistance values

. PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. Both BJT and nMOSFET access device cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit.

. PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. An nMOSFET transistor has larger cell size in the near term years, but offers simple process and low voltage operation. Both BJT and nMOSFET access device

[70] This entry is the expected current density output from the BJT access device required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger area BJT (which causes larger cell size) and higher output current (which requires

[72] This entry is the expected current density output from the nMOSFET access device required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger width nMOSFET (which causes larger cell size) and higher output current


[75] This entry is the expected PCRAM W/E cycling endurance. Recent published data indicate cycling endurance from 1E+9 to 1E+13. (Refs. S.J. Ahn et al., "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond,” 2004 IEDM, 37.2, pp. 907-

Table PIDS6 Reliability Difficult Challenges

Difficult Challenges ≥ 22 nm Summary of Issues

Transistor Reliability Time dependent dielectric breakdown

Negative bias temperature instability

Threshold voltage shifts due to traps, carrier injection, program or erase

Mobility degradation due to mechanical stress relaxation or interface state density change

New or changed failure mechanisms (TDDB, PBTI, NBTI< moisture absorption, etc.) resulting from high κ/metal gate

Interconnect Reliability Copper electromigration and stress voiding in scaled interconnects (lines and vias)

Electrical breakdown of interconnect dielectrics, especially low κ and ultra low κ

Moisture absorption/transport due to voids in porous low κ dielectrics

Cu (ionic) migration through cracked or thin barrier metals

Packaging Reliability New failure mechanisms associated with Pb-free solders and new mold compounds

Electromigration in package traces, vias, and bumps

Impact of multichip modules and stacked dies on failure rate

Solder ball electromigration, for example in CSP and flip chip

Radioactive contaminants in packaging materials

Reliability in Extreme and/or Critical Applications

Automotive (define mission profile for HOT underhood versus passenger and substantial cycling)

Military (rugged versus shock and dust, highly diverse environmental requirements)

Space, i.e., radiation hard

Aeronautical (singe event effects tolerant and large, fast temperature swings)

Medical (corrosive, hermeticity, and safety)

Impact of Variability on Reliability Statistic variation growing larger and defect size is comparable to feature size: Distribution of dopant atoms; subtle ultra-thin gate oxide defects; line edge roughness and other litho "fidelity" issues; surface scattering

How to cope with cost-effective screens and qualifications that capture some "good" units

Design for Reliability in face of large percentage process variability

How to use yield to drive reliability


Reliability of novel devices, structures, materials and applications

ITRS proposes many new materials and structures, yet currently very little known about failure mechanisms

Need to have reliability characterization in place well in advance of application to develop appropriate reliability requirements and qualification procedures

Design for Reliability tools

ORTCINDEX

2007 ITRS Chapters

2008INDEX

Table PIDS6 Reliability Difficult Challenges

Difficult Challenges ≥ 22 nm Summary of Issues

Transistor Reliability Time dependent dielectric breakdown

Negative bias temperature instability

Threshold voltage shifts due to traps, carrier injection, program or erase

Mobility degradation due to mechanical stress relaxation or interface state density change

New or changed failure mechanisms (TDDB, PBTI, NBTI< moisture absorption, etc.) resulting from high κ/metal gate

Interconnect Reliability Copper electromigration and stress voiding in scaled interconnects (lines and vias)

Electrical breakdown of interconnect dielectrics, especially low κ and ultra low κ

Moisture absorption/transport due to voids in porous low κ dielectrics

Cu (ionic) migration through cracked or thin barrier metals

Packaging Reliability New failure mechanisms associated with Pb-free solders and new mold compounds

Electromigration in package traces, vias, and bumps

Impact of multichip modules and stacked dies on failure rate

Solder ball electromigration, for example in CSP and flip chip

Radioactive contaminants in packaging materials

Reliability in Extreme and/or Critical Applications

Automotive (define mission profile for HOT underhood versus passenger and substantial cycling)

Military (rugged versus shock and dust, highly diverse environmental requirements)

Space, i.e., radiation hard

Aeronautical (singe event effects tolerant and large, fast temperature swings)

Medical (corrosive, hermeticity, and safety)

Impact of Variability on Reliability Statistic variation growing larger and defect size is comparable to feature size: Distribution of dopant atoms; subtle ultra-thin gate oxide defects; line edge roughness and other litho "fidelity" issues; surface scattering

How to cope with cost-effective screens and qualifications that capture some "good" units

Design for Reliability in face of large percentage process variability

How to use yield to drive reliability


Reliability of novel devices, structures, materials and applications

ITRS proposes many new materials and structures, yet currently very little known about failure mechanisms

Need to have reliability characterization in place well in advance of application to develop appropriate reliability requirements and qualification procedures

Design for Reliability tools

Table PIDS7 Reliability Technology Requirements


Early failures (ppm) (First 4000 operating hours) [1] 50–2000 50–2000 50–2000 50–2000

Long term reliability (FITS = failures in 1E9 hours) [2] 50–2000 50–2000 50–2000 50–2000

SRAM Soft error rate (FITs/MBit) 1000-2000 1000-2000 1000-2000 1000-2000

Relative failure rate per transistor (normalized to 2007 value) [3] 1 0.83 0.71 0.66

1 0.5 0.5 0.5





[1] Failures during the first 4000 hours of operation (~1 year's use at 50% duty cycle). Early failures are associated with defects.

[2] Long term reliability rate applies for the specified lifetime of the IC.

[3] While the overall IC failure rate does not change with time, as the number of transistors per chip increases [from ORTC], the relative failure rate per transistor must decrease

Relative failure rate per m of interconnect (normalized to 2007 value) [4]

Reliability requirements vary with different applications. For many mainstream customers it will be sufficient to hold current reliability levels steady during this period of rapid technological change. However, other customers would like reliability levels to be improved. Degradation of current reliability levels is not acceptable. Reliability requirements are for the packaged device and include both chip and package related failure modes.

A reliability qualification can always be attempted with available knowledge. The better the knowledge the less risk in the qualification and vice versa. Yellow coloring indicates some risk. Striped indicates a greater risk (due to changed and possible new failure modes). Finally, red indicates an unspecified solution (e.g., what technology will be used for post-Cu) for which the reliability risk cannot be assessed until details about the solution are provided.

[4] As the length of interconnect per chip increases [from Interconnect Technology Requirements tables], the failure rate per m of interconnect must decrease. Even more important for reliability is the increase in the number of vias.

ORTCINDEX

2007 ITRS Chapters

2008INDEX

2011 2012 2013 2014 2015 2016 2017 2018 2019

50–2000 50–2000 50–2000 50–2000 50–2000 50–2000 50–2000 50–2000 50–2000

50–2000 50–2000 50–2000 50–2000 50–2000 50–2000 50–2000 50–2000 50–2000

1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000 1000-2000

0.57 0.51 0.46 0.4 0.37 0.31 0.29 0.26 0.23

0.25 0.25 0.25 0.12 0.12 0.12 0.06 0.06 0.06

[1] Failures during the first 4000 hours of operation (~1 year's use at 50% duty cycle). Early failures are associated with defects.

[2] Long term reliability rate applies for the specified lifetime of the IC.

[3] While the overall IC failure rate does not change with time, as the number of transistors per chip increases [from ORTC], the relative failure rate per transistor must decrease

Reliability requirements vary with different applications. For many mainstream customers it will be sufficient to hold current reliability levels steady during this period of rapid technological change. However, other customers would like reliability levels to be improved. Degradation of current reliability levels is not acceptable. Reliability requirements are for the packaged device

A reliability qualification can always be attempted with available knowledge. The better the knowledge the less risk in the qualification and vice versa. Yellow coloring indicates some risk. Striped indicates a greater risk (due to changed and possible new failure modes). Finally, red indicates an unspecified solution (e.g., what technology will be used for post-Cu) for which the

Technology Requirements tables], the failure rate per m of interconnect must decrease. Even more important for

2020 2021 2022

50–2000 50–2000 50–2000

50–2000 50–2000 50–2000

1000-2000 1000-2000 1000-2000

0.2

0.03

0.18 0.16

0.03 0.03

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