Introduction to System-on-Chip - TUTedu.cs.tut.fi/soc-sme/SoC_intro2003.pdf · Introduction to System-on-Chip ... – To support SMEs in the actual technology take-up process

Introduction to System-on-Chip

Prof. Jari NurmiTampere University of Technology

Institute of Digital and Computer Systems

[email protected]

26.03.2003 Tampere University of TechnologyInstitute of Digital and Computer Systems

SOC-SME Network► The Finnish SoC-SME network was established in January 2002

► A Nordic/Baltic Network was launched in October 2002– To promote take-up of SoC technology in SMEs

– To offer awareness seminars to SMEs (like this seminar!!!)

– To set up distance learning capabilities in SoC area in all countries

– To provide pilot courses for interested companies

– To support SMEs in the actual technology take-up process

► Members: industry associations from all 8 countries

► Expert members: KTH, TUT, DELTA, SINTEF

► 50% funding provided by Nordic Industrial Fund for the course provision / awareness activities

► SMEs interested in the SoC/ASIC/FPGA/embedded technology invitedto join the network


The Finnish Steering Board

► Setup for year 2003

– Jari Nurmi, TUT (chairman) – Marja Hamilo, SET – Risto Mäkikyrö, TEKES– Jouni Tomberg, TUT– Markku Åberg, VTT Espoo / THUT– Juha-Pekka Soininen, VTT Oulu– Hannu Heusala, Oulu University – Markku Laitala, Finnelpro– Petri Solanti, Cadence Design Systems– Markku Tuomola, Mentor Graphics


System-on-Chip Terminology

► What is a ”system”, in the first place?

► What kind of a system could be placed on a silicon chip, then?

► System-on-Chip – one term, many definitions– ”the IBM definition”: a single-chip system containing analog, digital

and MEMS (micro-electro-mechanical system) parts– ”the Lucent definition”: a single-chip system containing analog and

digital parts– ”the Synopsys definition”: a single-chip digital system– etc. etc.


System-on-Chip Terminology (cont’d)

► Most definitions include also the following requirements– one or more processors on the chip– none or very few external components required to complete a system

(again, what is a ”system”?)

► Some definitions bring along requirements about the methodology that is adequate to design such systems– to cope with the hardware and software complexity of the systems– to cope with the deep-submicron manufacturing technologies– to address inter-block communication instead of functional entities only– to operate in large multidiscipline and multi-cultural design teams

SoC, System-on-Chip is a relatively complex stand-alone system on a single semiconductor chip containing at least one processor, maybe some analog or even electro-mechanical parts, where the design needs to address on-chip communication


SoC Examples

► Agere Systems (Lucent) network application chip– 137M transistors in 0.16 µm

► UC Berkeley Maia reconfigurable baseband chip– 1.2M transistors in 0.25 µm

APC(ATM Layer

Switch)

APC(ATM Layer

Switch)

PHY(Framer& IMA)

PHY(Framer& IMA) EDCEDC

SAR(AAL0/AAL2/

AAL5)

SAR(AAL0/AAL2/

AAL5)


System-on-a-Programmable-Chip

► SoC manufacturing is costly– Foundries more and more expensive– Mask costs for fine-grain lithography are increasing– Silicon vendors concentrate on big customers with big quantities– Very few multi-project prototype services available– Malfunction will cost a lot of money and time

Full-wafer prototype round may cost even 500,000 ... 1M €► On the other hand, FPGA-type solutions are also evolving

– On-chip processor cores– Multi-million gate capacity– Some vendors also provide coarse-grain reconfigurability

FPGA-based SoC-type platforms thus have a growing niche► System-on-a-Programmable Chip (SOPC) term coined by Synopsys► Platform FPGA, Programmable System-on-Chip (PSOC) or System-on-

Reconfigurable-Chip (SORC) are alternative names for these solutions


Platform FPGA Examples► Xilinx Virtex-II Pro XC2VP30

– 3 million system gates (advert.)– 136 multipliers (18x18)– 136 18kbit block RAMs – 2 PowerPC processors– IBM CoreConnect bus– 8 multi-gigabit tranceivers

► Chameleon (R.I.P.) CS2112– Coarse grain reconfigurable logic

• 84 Datapath Units (32-bit)• 24 Multipliers (16x24 single cycle)• 48 Local Store Memories (24 KBytes)

– ARC core– PCI– DMA

RECONFIGURABLEPROCESSING

FABRIC

MEM I/FARCPCI


Network-on-Chip

► Interconnect delays are dominating in deep submicron technologies

► Increasing frequencies and higher wire densities also increase crosstalk and other noise induced

► Chip sizes are not scaled down with technology, thus it takes multiple (even 10 – 20 !) clock cycles to traverse across a chip

► Interconnects and communication need to be addressed more than the actual functional blocks

► Globally Asynchronous, Locally Synchronous (GALS) communication needs to be adopted

► Network-on-Chip is a name for layered communication protocols and hierarchical interconnect implementations for on-chip global communication (borrowing from the OSI layers in the macro world)


Network-on-Chip Examples

► KTH-VTT Tiled NoC– Mesh topology with fixed tiles– Packet-switched

► TUT PROTEO Network– Topology and protocols flexible– Packet-switched network

Interfacerouter

IP

Bridge

BridgeInterface

router

InterfacerouterIP

IP

•••

Sub-network 1Sub-

network 3

Sub-network 2


System-on-Package

► There are very different technologies to be integrated in a SoC– advanced digital CMOS for low-power and high complexity

integration– DRAM memory– analog and RF technologies, with high accuracy, low-noise and

possibly high-voltage requirements– MEMS (Micro-Electro-Mechanical Systems) technologies with

electro-mechanical or electro-chemical interfaces► ”One size does not fit all” – there is no single technology to

integrate all these in economically feasible way► Also, better interconnects and passive components achieved on

other substrates than silicon► Also, yield may force to partition the system to several chips► System-on-Package (SoP) or System-in-Package (SiP) are

advanced multi-chip packaging technology complementing SoC


SoP Examples ► Sharp 3-D SiP


SoP Examples (cont’d) ► Amkor Technology SiP Package


What Is The Difference Between... ?

► ASIC (Application Specific Integrated Circuit) and SoC?– SoC: different design methodology needed, explicit use as a

system, not a building block► FPGA (Field Programmable Gate Array) and SoPC?

– SoPC: the processor(s) and memory integrated, system-scale logic capacity, possibly also more coarse-grain reconfigurability

► MCM (Multi-Chip Module) and SoP?– SoP: explicitly a system, not a component

► Embedded System and SoC/SoP/SoPC?– SoC/SoP/SoPC: a more integrated embedded system!

► SLI (System-Level Integration) and SoC?– No big difference, SLI more a methodology issue and not requiring

a single-chip system by default


Intellectual Property

► Intellectual Property (IP) blocks are used to increase the abstraction level of circuit design and thus speed up the designprocess

► There can be in-house (”legacy”) IP, free public IP and IP provided by 3rd party companies

► Virtual Component is another name for a well-specified IP block, this name is used by the Virtual Socket Interface Alliance (VSIA)

► The name IP comes from the idea that the designer/provider of the core is encapsulating his intellectual property in the form of a specific functional block that is then reused (licenced)

► Common types of commercial IP are processor cores and different standardized functions like MPEG-4, mp3 decoding or RSA encryption


Standardized Core Interfaces

► Some proprietary ”de Facto standard” on-chip buses exist, e.g.– ARM AMBA (AHB, APB)– IBM CoreConnect

► Real vendor-independent standard development done by– Virtual Socket Interface Alliance, VSIA

• Virtual Component Interface, VCI (AVCI, BVCI, PVCI)• Idea to encapsulate IP blocks with a universal interface• Compromise/combination of different bus interfaces

– Open Core Protocol International Partnership, OCP-IP• Practically a superset of VCI• Allows better use of ”different” communication channels like

networks• Originally developed by Sonics, Inc.

for their SiliconBackplane bus, opened to public through OCP-IP► Final standard by e.g. IEEE, with some issuing delay


Processor Cores

► The most successful IP cores (commercially) are processors► ARM RISC cores are the market leader in this segment► Also ARC, MIPS, PowerPC, Compact RISC, NIOS (Altera) etc. are used► At least LEON (Sparc), XiRISC and COFFEE free cores available► In DSP cores the market leader is DSP Group (now with Parthus Ceva

Ltd.) with its Pine, Oak, Palm, Teak, etc. cores► Also other players like VS-DSP from VLSI Solution (Finland), StarCore,

Clarkspur Design, and foundry-captive cores from Texas Instruments, Analog Devices etc.

► Practically no good open-source DSP cores are available► There are different licensing models

– Direct licensing from the provider (may be costly…)– The foundry, design tool vendor or FPGA vendor provides the core– Free (open source) cores


COFFEE TM RISC Core► A clean open-source RISC core architecture developed at TUT► Multiplier and barrel-shifter incorporated in a 7-stage pipeline

(DSP flavour) running at about 200 MHz clock frequency (0.18 µm)► Available as a free IP component

– Synthesizable VHDL codes– High-level simulation models (VHDL, SystemC)– MILK TM Floating-point coprocessor (also in synthesizable VHDL)– Assembler– Linker and loader– HLL compiler based on GNU compiler (under development)– Instruction set simulator (ISS) (under development)– RTOS ported (under development)

► Compatible with OCP-IP, VCI, AMBA interfaces► Basic peripheral set + 3rd party compatible peripherals usable► Some configurable features


SoC Design Paradigms / Methodology

► IP-based design– Reuse to increase productivity– Functionality is (mostly) built up of IP blocks– Interconnects and physical layout remains to be designed– Software content of integrated systems is increasing– Interfaces have to be well specified and standardized

► Interconnect-centric design– Interconnects form the major bottleneck from timing point of view– Crosstalk, transfer line effects and noise are major obstacles– Physical design must concentrate on ensuring signal integrity– Often also Network-on-Chip type of layered approach is appreciated


SoC Design Paradigms / Methodology (cont’d)

► Platform-based design– In addition to functional IP reuse, also the communication is reused– Standardized interfaces between the blocks and the communication

backplane still important– Parameterized application domain-specific platforms are emerging– Platform is designed once and it will live longer than one product or

fabrication technology generation– Platforms can be instantiated for different products or versions– Platform design and platform usage are separated– Fixed instances with reconfigurability can also form platform chips

(SoPC / Platform FPGA)– Programmable processors and their programs form a considerable

part of the platform functionality– Platform use is approaching embedded software engineering– The design task is to map the system description to the most suitable

platform instance (within the allowed parameter space) + SW


Platform-Based SoC Design

Reconf.Block

FixedBlock

A/D

RISC

A/D

DSP A-SProc.

COMMUNICATION

RF Analog

A/D

MEMS

RTOS RTOS

SW SWSW

Dig.I/O Shared

storage(electr.

HD)


SoC Technologies (and SoP Enablers)

► The primary technology is Complementary Metal Oxide Semiconductor (CMOS)– traditional digital technologies developed to deep submicron feature sizes

► Integrated Random Access Memory (IRAM) CMOS technologies– CMOS logic merged into DRAM technology

► Micro-Electro-Mechanical Systems (MEMS) technologies– micromechanics and interface logic in (CMOS) silicon technologies

► Silicon-on-Insulator (SOI)– high-speed radiation tolerant CMOS variant

► The properties of these technologies from SoC point of view will be reviewed next


Deep-Submicron CMOS

► Predominant digital and (mostly low-frequency) mixed-signal technology

► Scaling to 0.18 ... 0.13 µm (now) and 0.09 ... 0.05 µm (within next 5 years) is bringing along some side effects– low supply voltages– high operating frequency– dense wiring

power supply noise, cross-talk and transfer-line effects– leakage, leakage, leakage

► Low supply voltages (+ noisy on-chip environment) do not provide enough dynamic range for high-quality analog

► Good for very complex digital SoC with limited analog interfaces and possibly even radio frequency (RF) capability

► Power density, leakage handling and interconnect design remain as the major concerns for the future


IRAM

► Increasing amount of memory in integrated systems has lead to concern memory technologies for system integration

► IRAM is the leading concept, integrating logic into a DRAM-optimized process

► Extremely good in improving the memory access bandwith, which forms a bottleneck for systems using off-chip memory

► Dense memories achieved (DRAM is about 20x denser than SRAM that can be integrated in normal CMOS technologies)

► One main drawback is that the logic sizes are about 30 – 70% larger and delays 30 – 100% larger on the memory processes

► The technologies are not very mature yet, and suit the best for combining microprocessors and their memory within a single chip

► The latest trend is to combine RAM with reconfigurable logic


MEMS► Micro Electro Mechanical Systems (MEMS)► Micro Optical Electrical Mechanical Systems (MOEMS)

– also optoelectronics integrated► Allows integration of sensors and actuators with electrical

interfaces (mainly)► Fabricated by micromachining the silicon substrate► Similar drawback as with DRAM – different optimisation goals► Very limited complexity systems only can be integrated on a

single chip


SOI

► Silicon on Insulator (SOI)► Addresses the drawbacks of CMOS caused by the conducting

substrate► Active devices are fabricated on isolated islands► Lower substrate capacitances (no conducting bulk)

– higher speed– lower power consumption

► Very similar to CMOS and thus useful for SoC integration► Not very mature technology yet, problems with analog linearity► The wiring capacitances dominate in deep submicron...


Costs of SoC Integration

► Fabrication cost example case– 20mm2 in 0.35µm CMOS technology– Wafer costs 1800$, package TSOP48, testing time 4s– Circuits needed: 500 000– + 10% QA ja LAT

550 000– packaging yield 96%

572 000– fabrication process yield 82%

698 000 circuits order– 1500 circuits/8” wafer

466 wafers► The price becomes then:

– 466 wafers 840k$– Wafer sorting and testing 214k$– Packaging 180k$– Electrical testing of packaged circuits 190k$

TOTAL 1424 k$► Vendor adds 10% to cover risks + another 10% for profit

1708k$3.416 $/good packaged circuit


Costs of SoC Integration (cont’d)

► So, the ASIC/SoC fabrication is not so expensive► What costs is the MASK SET for fabrication (NRE, Non-Recurring Cost,

includes also test setup etc.) and it is increasing with new technologies– up to 500,000 ... 1M € for modern 100 nm scale technologies– e.g. for the 500,000 pieces 1-2 $/€ more price per packaged circuit– for 5,000 pieces 100-200 € more!

► Dedicated full mask set suits for large volumes only► So, there have to be ways to decrease small volume and prototype

costs– MPW (Multi-Product Wafer) runs

• several designs share a mask set• suits for prototypes and small volumes (a few thousands)

– Multilevel mask set• 4 layers per mask• smaller NRE-costs• suits for small volumes (e.g. 10 to 40 wafers)


Benefits of SoC Integration► Less components

– Component costs– Board size and cost– Assembly and testing costs

► Less inter-chip interconnects– Reliability– Power consumption– Board design, fabrication and assembly costs

► Smaller system volume (in cm2) and weight– Higher integration rate– Smaller case costs– Smaller transport costs

► In high volumes (in pcs), also lower circuit costs► The main question: how easily can you save the cost of the circuit

(from 1 to 100 € depending on the case) from the other parts of the system??? Or do you maybe add functionality/features that is worth the cost for the end user???


The Roadmap to SoC ► SoPC an inexpensive solution (almost no NRE) for integrating low-volume products

► SoC integration in CMOS for higher volumes

► SoP for multi-technology

Board-LevelEmbeddedSystems

PLD or ASIC-BasedBoards

SoPC

SoP

SoC

STANDARD COMPONENTS:LOW NRE COSTS, HIGH UNIT COSTS

CUSTOM COMPONENTS:HIGH NRE COSTS, LOW UNIT COSTS

FPGA Boards

LEVEL OF INTEGRATION


Trends

► More and more functionality on a single chip or module

► High fab costs of modern circuit technologies

► SoPC market share growing

► Design methodologies undergoing a paradigm shift

► Reuse on higher levels of abstraction needs standardized I/Os

► Verification also a growing challenge


Some SoC Research Projects in Finland

► GIGATRAN (TUT)– Creator of the PROTEO Network-on-Chip

► COMPLAIN (TUT, UTU, KTH)– Communication platforms, interconnect-centric design

► SoC-Mobinet (TUT, UTU, KTH, DTU, CTI, Infineon, Acreo, Spirea)– Education, training and PhD/MSc theses in System-on-Chip area

► NoC Arch (VTT, KTH)– Creator of the tiled Network-on-Chip paradigm

► ELASTIC (UTU, TUT)– Project application for scalable platform-based design

► PROMISE (TUT)– Project application for application-specific processor and inter-

processor communication optimisation for SoC platforms


SoC Conferences► International Symposium on System-on-Chip

– in Tampere, Finland since 1999– earlier called SoC Seminar– IEEE technical co-sponsorship since 2003

► IEEE Workshop on System-on-Chip for Real-Time Applications– in Canada since 2001– IEEE sponsorship since 2003

► IEEE International Conference on System-on-Chip– in USA– earlier ASIC/SoC (and before that ASIC) conference– since 2003 uses the SoC name

► International Workshop on IP-Based SoC Design– in Grenoble, France– earlier International Workshop on IP Based Synthesis and System Design– organized by Design & Reuse

► VLSI-SOC 2003– IFIP International Conference on Very Large Scale Integration– earlier called VLSI conference (without SoC)


Conclusions

► System-on-Chip needs new design paradigms

► System-on-Programmable-Chip is a good (and inexpensive) stepping stone on the way to SoC

► System-on-Package is a viable solution for blending different technologies within a single entity (no big difference to SoC from the user point of view)

► Reuse still plays an important role in digital SoC design – up to the platform level

► Research on SoC in Finland is in the forefront worldwide


Some References

► SoC Special issue of IEEE Micro, September 2002.

► NOC ”Networks on chips: a new SoC paradigm” IEEE Computer, January 2002.http://www.imit.kth.se/info/FOFU/NOC/

► SoPC http://www.altera.com/http://www.xilinx.com/

► SoP http://www.imaps.org/

► CMOS SIA Roadmap http://public.itrs.net/

► IRAM http://iram.cs.berkeley.edu/

"A Case for Intelligent DRAM: IRAM," IEEE Micro, April 1997.

► MEMS http://www.memsnet.org/

► SoC 2003 http://www.cs.tut.fi/soc/

► Jari Nurmi http://www.cs.tut.fi/~nurmi/

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Introduction to System-on-Chip - TUTedu.cs.tut.fi/soc-sme/SoC_intro2003.pdf · Introduction to System-on-Chip ... – To support SMEs in the actual technology take-up process