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ENG2410Digital Design

“Memory Systems”

Fall 2017S. Areibi

School of EngineeringUniversity of Guelph

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Week #11 Topics

o Random Access Memory� Static RAM

� Array of RAM ICs

� Dynamic RAM

� Types of Dynamic RAM

o Comparison

o Larger Wider Memories

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Resources

� Chapter #9, Mano Sections� 9.1 Memory Definitions

� 9.2 Random Access Memory

� 9.3 SRAM Integrated Circuits

� 9.4 Array of SRAM ICs

� 9.5 DRAM ICs

� 9.6 DRAM Types

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A Digital Computer System

Inputs: Keyboard,

mouse, modem, microphone

Outputs: CRT, LCD, modem,

speakers

Memory

Controlunit Datapath

Input/Output

CPU

Data/Instructions/code

clock

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Introduction

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Picture of Memory

• You can think of memory as being one big array of data.

– The address serves as an array index.

– Each address refers to one word of data.

• You can read or modify the data at any given memory address, just like you can read or modify the contents of an array at any given index.

Address Data

00000000

00000001

00000002

.

.

.

.

.

.

.

.

.

.

FFFFFFFD

FFFFFFFE

FFFFFFFF

Word

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Memory Signal Types

• Memory signals fall into three groups

– Address bus - selects one of memory locations

– Data bus

• Read: the selected location’s stored data is put on the data bus

• Write (RAM): The data on the data bus is stored into selected locations

– Control signals - specifies what the memory is to do

• Control signals are usually active low

• Most common signals are:

– CS: Chip Select; must be active to do anything

– OE: Output Enable; active to read data

– WR: Write; active to write data

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Properties of Memory

1. Volatile: Memory contents disappears if power turned off, found in:

� Typical computer systmes (laptops, desktops)

� PDA, Smart Phone, iPADs, …

2. Nonvolatile: Contents of memory remaineven if power turned off, found in:

� Smart Phones,

� Hard Drives,

� Memory Sticks

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RAM vs. ROM

1. Volatile Memory � RAM (Random Access Memory)

� Static RAM usually used for Cache

� Dynamic RAM used for Main Memory

2. Non-Volatile Memory� ROM (Read Only Memory), FLASH

� Used to store permanent programs in a computer system (booting)

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Classification

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Classification of Memory

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Key Design Metrics

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Memory Technologies

Memory Technology Typical Access time $ per GIB in 2012

SRAM Semiconductor memory 0.5 – 2.5 ns $500 - $1000

DRAM Semiconductor memory 50-70 ns $10 - $20

Flash Semiconductor memory 5,000 – 50,000 ns $0.75 - $1.00

Magnetic Disk 5,000,000 – 20,000, 000 ns $0.05 - $0.10

The access time and price per bit vary widely among these technologies, as seen in the table below.

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Memory Hierarchyo The design constraints on a computer memory can be summed up by

three questions (i) How Much (ii) How Fast (iii) How expensive.

o There is a tradeoff among the three key characteristicso A variety of technologies are used to implement memory systemo Dilemma facing designer is clear � large capacity, fast, low cost!!

o Solution � Employ memory hierarchy

registers

Cache

Main Memory

Disk Cache

Magnetic Disk

Removable Media

Cost

Capacity

Access

Time

Flip Flops

Static RAM

Dynamic RAM

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Main Memory vs. Cache

Static RAM

Dynamic RAM

Registers

Flipflops

Static RAM

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CPU

CacheController

CacheMemory

PCIController

DRAM

EISA/PCI BridgeController

Hard DriveController

VideoAdaptor

PC Card 1 PC Card 2

SCSIAdaptor

PC Card 3

Local CPU / Memory Bus

Peripheral Component Interconnect Bus

EISA PC BusSCSIBus

Co-processor

Memory

Static RAM

Dynamic RAM

Registers

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RAM vs. ROM

o RAM

� Read/write

� Volatile

� Faster access time

� Variants

� SRAM

� DRAM

• Application

� Variables

� Dynamic memory allocation

� Heaps, stacks

o ROM

� Read only

� Non-Volatile

� Slower

� Variants

� PROM,EPROM

� EEPROM, FLASH

• Application

� Programs

� Constants

� Codes, e.t.c

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Random Access Memory

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Random Access Memories

o So called because it takes the same amount of time to address any particular part

o Types of RAM1. Static RAM (SRAM), fast, expensive

2. Dynamic RAM (DRAM), slow, cheap

o How is memory accessed? Address Lines, Data Lines

Control Signals (R/W, chip select, …)

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Simple View of RAM

o Of some word size n=4,8,16 ….

o Some capacity 2k

o k bits of address line, k=10,11,..

� Has a read line

� Has a write line

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1K x 16 memory

o Variety of sizes

�From 1-bit wide

o Issue is no. of pins

o Memory size specified in bytes

�1K x 16 bit � 2KB memory

o 10 address lines and 16 data lines

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Chip Select and R/W Lines

o R/W Lines enable reading/writing

o Usually a chip select line is used.

o Why?

� To enable RAM chip to be accessed.

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Memory: Writing

o Sequence of steps� Setup address lines

� Setup data lines

� Activate write line (maybe a pos edge)

o The write cycle time is the maximum time from the application of the address to the completion of all internal memory operations required to store a word.

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Writing: Timing Waveforms

o CPU operates at 50 MHz (20 ns)

o 4 clock cycles to perform a write

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Memory Reading

o Steps

�Setup address lines

�Activate read line

�Data available after specified amount of time

o Read cycle usually is shorter than write cycle.

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Memory Waveform: Reading

o CPU operates at 50 MHz (20 ns)

o 65 ns required for a read cycle

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Static RAM

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MOSFET: Metal OxideSemiconductor

Field Effect Transistor

A voltage controlled device�Dissipates less power �Achieves higher density on an IC� Has full swing voltage 0 � 5V

nMOS Transistor

Ids

Vgs

|VGS|

An nMOS Transistor

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Static RAM: 4T and 6T

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SRAM Cell

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VDD GNDVDD VDDVDD

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Simplify Modeling using Latch

o Storage is modeled by an SR latch.

o Control logic

o One memory cell per bit

• For select = 0, the stored content is held.

• For select = 1, the stored content is determined by values on B and B’

• The outputs are gated by the select line also.

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Bit Slice

o Cells connected to form 1 bit position

o Word Select gates one latch from address lines

o Note it selects Reads alsoo B (and B’) set by R/W,

Data In and BitSelecto When R/W = 0 and

BitSelect = 1, then if Data in = 1 � the latch will be set (i.e. a 1 is written)

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Bit Slice can Become Module

o Basically bit slice is a one Dimensional array of memory

o What type of hardware do we need to access one row at a time?

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16 X 1 RAM

o 4 address lines required to access 16 locations.

o A Decoder is added to select the different words (each 1 bit wide).

o For 16 words we need a 4-to-16 line Decoder

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Row/Column

o Practical memories contains thousands of words!!

o If RAM gets large, there is a huge decoder

o Also run into chip layout issues

o How can we change the structure of Memory to solve this problem?

o Rearrange the memory into “2D” i.e., matrix layout

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16 X 1 as 4 X 4 Array

o Two decoders

• Row

• Column

o Address just broken up

o Not visible from outside

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16 X 1 as 4 X 4 Array

o Employing 2 decoders instead of 1 row decoder is called coincident selection

o Row Select and Column Select

o A3A2A1A0=0000 will attempt to choose RAM cell 0.

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Change from 16x1 to 8 X 2 RAM

o Minor change in logic

o Try addressing 011 on board

o Cells 6,7 are chosen for reading or writing.

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A Single Row Decodero Imagine 32k x 8 = (32 x 1024 x 8) = 262,144 bits �256K bit memory

o How many address lines required to locate 32K locations?o A 15 bit address line is required.

o 262,144/8 = 32,768 chunks each 8-bits

o One column layout would need a decoder with 32,768 outputs

� For a single decoder that would mean 32,800 gates

� This is not practical!

o Solution?

o Coincident selection.

262,144 bits

15 Address Lines

15-to-32768

Decoder

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Coincident Selectiono A 32K X 8 contains 256 Kbits (32 x 1024 x 8 = 262,144 bits)o To make the number of rows and columns equal we take the square root of

256K, giving 512 = 29

� A 9-to-512 decoder is required for the rows (9 address lines are fed to the Row Decoder).

� Remember we need 8 bits of output!! (Column Decoder?)o For the columns 512/8 = 64 = 26

� A 6-to-64 line decoder is required for the columns (6 address lines are fed to the Column Decoder).

o Total number of gates is now 512+64 = 576 gateso Thus reducing the total gate count by 50x.

262,144 bits

512

512

9-to-512

6-to-64

9 Address Lines

6 Address Lines

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SRAM Performance

o Current SRAMs have cycle times in low nanoseconds (say 2.5ns)

o Used as cache (typically on-chip or off-chip secondary cache)

o Sizes up to 256 Mbit or so for fast chips

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Memory Expansion

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Larger/Wider Memories

o Made up from sets of chips

o Consider a 64K by 8 RAM

� Note new symbols for sets of lines, 8 & 16 bits wide

� The “Chip Select” line will activate the memory chip

� How to increase capacity to 256K x 8?

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Larger: 256k x 8� Use 4 of these chips � 256 K x8

� Connect all output data lines together (tristate)

� Connect all input data line together

� Connect all 16 address lines together (i.e., 16 lines of address to fetch a word in any DRAM chip)

� But we need to activate only one chip at a time!!

How many address lines for 256K Memory?

How to select the specific RAM chip?

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Larger Capacity

o Decoder for high-order 2 bits

� Selects chip

o Check the address ranges

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Wider Memory – 64K X 16

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Dynamic RAM

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Dynamic memory

• Dynamic memory is built with capacitors.

– A stored charge on the capacitor represents a logical 1.

– No charge represents a logic 0.

• However, capacitors lose their charge after a few milliseconds. The memory requires constant refreshing to recharge the capacitors. (That’s what’s “dynamic” about it.)

• Dynamic RAMs tend to be physically smaller than static RAMs.

– A single bit of data can be stored with just one capacitor and one transistor, while static RAM cells typically require 4-6 transistors.

– This means dynamic RAM is cheaper and denser—more bits can be stored in the same physical area.

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Dynamic RAM

o Capacitor can hold charge

o Transistor acts as gate� No charge is a 0

� Can close switch & add charge to store a 1

o Then open switch (disconnect)

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DRAM Cell

DRAM read Operations

– Precharge bit line to VDD/2.– Take the word line HIGH.– Detect whether current flows into or out of the cell.– Note: cell contents are destroyed by the read!– Must write the bit value back after reading.

DRAM write Operations

– Take the word line HIGH.– Set the bit line LOW or HIGH to store 0 or 1.– Take the word line LOW.

– Note: The stored charge for a 1 will eventually leak off.

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Dynamic RAM (… continued)

(a) (c)

(f) (g)

Select

BT

C

DRAM cell

To Pump

(b)

(d) (e)

Stored 1 Stored 0

Write 1 Write 0

Read 1 Read 0

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DRAM Characteristics (Why Slow!)

o Destructive Read� When cell read, charge removed

� Charge must be restored after a read

o Refresh� Capacitors are not perfect! there’s steady leakage

� Charge must be restored periodically

o DRAM are dense (lots of cells) so there are many address lines.� To reduce the physical size of DRAM we can

reduce the number of pins by applying the address lines serially in two parts:

• Row Address, and then

• Column Address

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How DRAM WorksA7A6A5A4

A3A2A1A0

A7A6A5A4A3A2A1A0

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DRAM Read Signaling

o DRAM has a lower pin count by using same pins for row and column addresses

Delay until data

available

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DRAM Write Timing

DRAM-chip internal organization

64K x 1DRAM

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DRAM Logic Diagram

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DRAM charge leakage

Typical devices require each cell to be refreshed once every 4 to 64 mS.

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DRAM Refresh

o Many strategies

o Logic on chip

o Refresh counter and Refresh controller

o Refresh counter is used to provide the address of the row of DRAM cell to be refreshed.

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CAS Before RAS

o Set column address

o Apply CAS first (opposite of RW)

o Then toggle RAS enough times to cycle through row addresses

o On-board refresh counter applies the row addresses

CAS

RAS

Col Add Row Add Row Add Row Add Row Add

DRAM - Dynamic RAM

FPM RAM - Fast page-mode RAM

EDO RAM - Extended Data Out RAM

BEDO RAM - Burst Extended-data-out RAM

SDRAM - Synchronous Dynamic RAM

DDRRAM - Double Data Rate RAM

DRAM Chip Types

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Page Mode DRAMo DRAMs made to read & write blocks

o Example

� Assert RAS, leave asserted

� Assert CAS multiple times to read sequence of data

o Similar for writes

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Synchronous DRAM

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Synchronous DRAM (SDRAM)

o Double Data Rate SDRAM

o Transfers data on both edges of the clock

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DRAM EvolutionThere has been multiple improvements to the DRAM design in the past 20 years.

SDRAM: A clock signal was added making the design synchronous.

DDR SDRAM: The data bus transfers data on both rising and falling edge of the clock.

DDR2 SDRAM: Second generation of DDR memory scales to higher clock frequencies.

DDR3 SDRAM: Third generation has lower power consumption, higher clock frequency and denser modules

DDR4 SDRAM: Fourth generation, improvement over DDR3, high bandwidth, higher speed. However it is not compatible with any earlier type of (RAM) due to different signaling voltages.

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DDR SDRAM Comparison

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Memory Technologies

o DRAM: Dynamic Random Access Memory

� upside: very dense (1 transistor per bit) and inexpensive

� downside: requires refresh and often not the fastest access times

� often used for main memories

o SRAM: Static Random Access Memory

� upside: fast and no refresh required

� downside: not so dense and not so cheap

� often used for caches

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Summary

o RAMs with different characteristics

� For different purposes

o Static RAM

� Simple to use, small, expensive

� Fast, used for cache

o Dynamic RAM

� Complex to interface, largest, cheap

� Needs periodic refresh

� Dense, slow, used in Main Memory

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Links

Ram Guides (not very technical)

� http://arstechnica.com/paedia/storage.html

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