ENG241 Comb Logic Design PartB Week4

ENG241 Digital Design

Week #4 Combinational Logic Design Part B

Fall 2010 ENG241/Digital Design 2

Resources

Chapter #4, Mano Sections 4.1 Combinational Circuits 4.3 Decoding 4.4 Encoding 4.5 Multiplexers 4.6 Comb Function Implementations


Week #4 Topics

Decoders Combinational circuit Implementation

Encoders Priority Encoders

Multiplexers Combinational Circuit Implementation

Demultiplexers


Decoders Typically n inputs and 2n outputs Drives high the output corresponding to binary

code of input Example: Binary to Octal, Binary to Hex, e.t.c


2-to-4 Line Decoder

Notice they are minterms


Truth Table, 3-to-8 Decoder

Notice they are minterms


3-to-8 Line Decoder Schematic


2-to-4 with Enable


Enable Used for Expansion


VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral(algorithmic)

• Registers• State machines• Test benches

Sequential statements

Subset most suitable for synthesis

Fall 2010 11

entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic);end entity decoder_2_to_4;

architecture dataflow1 of dec_2_to_4 is

Signal A0_n, A1_n: std_logic;begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1;end architecture dataflow1;

entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic);end entity decoder_2_to_4;

architecture dataflow1 of dec_2_to_4 is

Signal A0_n, A1_n: std_logic;begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1;end architecture dataflow1;

Decoder: Data Flow Example: 2-to-4 decoder

D0

D1

D2

D3

A(1)

A(0)In

terf

ace

Fun

ctio

nalit

y

A0_n

ENG241/Digital Design


zmux: z <= d0 when sel1 = ‘0’ and sel0 = ‘0’ else d1 when sel1 = ‘0’ and sel0 = ‘1’ else d2 when sel1 = ‘1’ and sel0 = ‘0’ else d3;

When Else Statement


entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) );end entity dec_2_to_4;

architecture dataflow2 of dec_2_to_4 isbegin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX";end architecture dataflow2;

entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) );end entity dec_2_to_4;

architecture dataflow2 of dec_2_to_4 isbegin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX";end architecture dataflow2;

Decoder: Data Flow #2Example: 2-to-4 decoder

D(0)

D(1)

D(2)

D(3)

A(1)

A(0)In

terf

ace

Fun

ctio

nalit

y

A(1..0) D(3..0)

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0


Structural VHDL Descriptionof 2-to-4 Line Decoder


Structural VHDL Description(Entity Declaration)

-- 2-to-4 Line Decoder; structural VHDL Descriptionlibrary ieee;use ieee.std_logic_1164.all

entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic);end decoder_2_to_4_w_enable;


Structural VHDL Description(Signals)

A0_nA1_n

N0

N3

N1

N2


Structural VHDL Description(Components)

architecture structural1_1 of decoder_2_to_4_w_enable is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component;


Structural VHDL Description(Connecting components)

architecture structural1_1 of decoder_2_to_4_w_enable is-- component NOT1 declaration-- component NAND2signal A0_n, A1_n, N0, N1, N2, N3: std_logic;begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);end structural_1;


Cont .. Structural VHDL Descriptionof 2-to-4 Line Decoder

architecture structural1_1 of decoder_2_to_4_w_enable is-- component NOT1 declaration-- component NAND2signal A0_n, A1_n, N0, N1, N2, N3: std_logic;begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3);end structural_1;

A0_n

A1_n


Usage for Decoders

Implement logic circuits! Memory address lines Decoders are used in Micro

Computer Interfacing for Keyboard and Display applications.


Decoder generates appropriateminterm based on control signals

(it "decodes" control signals)

Decoders as General-purpose Logic

n:2n decoder implements any function of n variables With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function


Decoders as General-purpose Logic

Example: Implement the following boolean functions 1. S(A2,A1,A0) = SUM(m(1,2,4,7))

2. C(A2,A1,A0) = SUM(m(3,5,6,7))

1. Since there are three inputs, we need a 3-to-8 line decoder.

2. The decoder generates the eight minterms for inputs A0,A1,A2

3. An OR GATE forms the logical sum minterms required.


F1

Example F1 = A' B C' D + A' B' C D + A B C D

A B

0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD

4:16DECEnable

C D


Encoder

Encoder is the opposite of decoder 2n inputs (or less – maybe BCD in) n outputs Examples:

Octal to binary Hexadecimal to binary


Truth Table (Octal to binary)


Inputs are Minterms

A0 = D1 + D3 + D5 + D7


What’s the Problem? What if D3 and D6 both high? Simple OR circuit will set A to 111 Solution?


Priority Encoder

Chooses one with highest priority Largest number, usually

Note “don’t cares”

What if all inputs are zero?


Need Another Output!

A Valid Output!


Valid is OR of all inputs


Multiplexer (or Mux)

Selects one of a set of inputs to pass on to output

Binary control code, n lines Choose from 2n inputs

Useful for choosing from sets of data Memory or register to ALU

Very common

74153


Two Input Multiplexer


4-to-1 Line Multiplexer


Logic is Decoder Plus ….


Compare the two Diagrams!


Dataflow VHDL Descriptionof 4-to-1 Multiplexer

-- 4-to-1 Line Mux; Conditional Dataflow VHDL Descriplibrary ieee;use ieee.std_logic_1164.all

entity multiplexer_4_to_1_we is port (S: in std_logic_vector(1 downto 0); I: in std_logic_vector(3 downto 0); Y: out std_logic;end multiplexer_4_to_1_we;


Cont .. Dataflow VHDL Description

architecture function_table of multiplexer_4_to_1_we is

-- Using When Else

Begin Y <= I(0) when S = “00” else I(1) when S = “01” else I(2) when S = “10” else I(3) when S = “11” else `X’;end function_table;


Quad 2-to-4 Line Mux

Select one set of 4 lines

Fall 2010 ENG241/Digital Design 39CA B

01234567

10100011

S2

8:1 MUX

S1 S0

F

Muxes as General-purpose Logic

2n:1 multiplexer implements any function of n variables1. With the variables used as control inputs and2. Data inputs tied to 0 or 13. In essence, a lookup table

Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC


A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1

C'

C'

0

1 A B

S1 S0

F0123

4:1 MUX

C'C'01F

CA B

01234567

10100011

S2

8:1 MUX

S1 S0

Multiplexers as General-purpose Logic (cont’d)

2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its

complement Example:

F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC


Demultiplexer

Takes one input Out to one of 2n possible outputs


Demux is a Decoder

With an enable



Decoder Expansion

A 2-to-4 Line decoder requires 4 (2-input) AND gates A 3-to-8 line decoder requires 8 (3-input) AND gates If we want to design a 6-to-64 line decoder then we

will need? 64 (6-input) AND gates! Unfortunately, as decoders become larger, this

approach gives a high gate input count! Instead we will resort to a procedure that uses

design hierarchy to construct any decoder with n inputs and 2n outputs.

The resulting decoder should have the same or a lower gate input count than the one constructed simply enlarging each AND gate.


Decoder Expansion

To design a 3-to-8 line decoder (n=3) we can use a 2-to-4 line decoder and 1-to-2 line decoder feeding eight 2-input AND gates to form the minterms instead of using eight 3-input AND gates!


General Procedure

1. Let k=n.2. If k is even, divide k by 2 to obtain k/2. 3. Use 2k AND gates driven by two decoders of output size

2k/2. 4. If k is odd, obtain (k+1)/2 and (k-1)/2.5. Use 2k AND gates driven by a decoder of output size 2(k+1)/2 and a decoder of output size 2(k-1)/2

6. For each decoder resulting from step (2-3) (4-5), repeat with values obtained in step 2 until k=1.

7. For k=1, use a 1-to-2 decoder.


Decoder Expansion - Example 1

3-to-8-line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal

(k+1)/2 2-to-4-line decoder (k-1)/ 2 1-to-2-line decoder

2-to-4-line decoder Number of output ANDs = 4 Number of inputs to decoders driving output ANDs = 2 Closest possible split to equal

Two 1-to-2-line decoders See next slide for result


Decoder Expansion - Example 1

Result

3-to-8 Line decoder

1-to-2-Line decoders

4 2-input ANDs 8 2-input ANDs

2-to-4-Linedecoder

D0A 0

A 1

A 2

D1

D2

D3

D4

D5

D6

D7


Multi-Level 6-to-64


Aside:K Map for A0

X on input means we must satisfy for both possibilities: 0, 1


Variations

At right Enable not Inverted outputs


Variations


Structural VHDL Descriptionof 4-to-1 Line Multiplexer

N(0:3)D(0:3)S_n(0:1)


Cont .. Structural VHDL Descriptionof 4-to-1 Multiplexer

-- 4-to-1 Line Multiplexer; structural VHDL Descriptionlibrary ieee;use ieee.std_logic_1164.all

entity multiplexer_4_to_1_st is port (S: in std_logic_vector(0 to 1); I: in std_logic_vector(0 to 3); Y: out std_logic;end multiplexer_4_to_1_st;



architecture structural_2 of multiplexer_4_to_1_st is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; out1: out std_logic); end component; component OR4 port(in1, in2, in3, in4: in std_logic; out1: out std_logic); end component;



architecture structural_2 of multiplexer_4_to_1_st is-- component NOT1 AND2 OR4 declarations

signal S_n : std_logic(0 to 1);signal D, N : std_logic_vector(0 to 3);begin g0: NOT1 port map (S(0), S_n(0)); g1: NOT1 port map (S(1), S_n(1)); g2: AND2 port map (S_n(1), S_n(0), D(0)); g3: AND2 port map (S_n(1),S(0), D(1)); g4: AND2 port map (S(1),S(0), D(3)); g5: AND2 port map (S(1), S(0), D(3)); g6: AND2 port map (D(0), I(0), N(0)); g7: AND2 port map (D(1),I(1), N(1)); g8: AND2 port map (D(2),I(2),N(2)); g9: AND2 port map (D(3),I(3), N(3)); g10: OR4 port map (N(0), N(1), N(2), N(3), Y);end structural_2;

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ENG241 Comb Logic Design PartB Week4