Implementation of a Software GPS Receiver · 2017. 6. 27. · Clock Parameters IF bandwidth 2 MHz at 15.42MHz 2 MHz to 20 MHz (configurable at step size of 1kHz) Sampling rate GPS

Proceedings of ION GNSS 2004 (Session A3), Long Beach, CA, September 21-24, 2004 1

Implementation of a Software GPS Receiver

C. Ma, G. Lachapelle, and M.E. Cannon

Position, Location And Navigation (PLAN) Group Department of Geomatics Engineering, University of Calgary

Calgary, Alberta, Canada, T2N 1N4 BIOGRAPHY Dr. Changlin Ma is a senior research associate in the above department. He has been involved with GPS research for five years. He holds PhDs in electrical and geomatics engineering. His current research focuses on GPS receiver technology and wireless location. Dr. Gérard Lachapelle is a Professor in the above department, where he is responsible for teaching and research related to location, positioning, and navigation. He has been involved with GPS developments and applications since 1980. He holds a Canada Research Chair/iCORE Chair in wireless location since 2001. More info on http:///plan.geomatics.ucalgary.ca Dr. M. Elizabeth Cannon is a Professor and Head of the Department of Geomatics Engineering. She has been involved in GPS research and development since 1984, and has worked extensively on the integration of GPS and inertial navigation systems for precise aircraft positioning. Dr. Cannon is a Past President of the ION. More info on http:///plan.geomatics.ucalgary.ca ABSTRACT Software GPS receivers can provide full access to base band signal processing inside the receiver channels. Thus, it has become the key component when investigating and developing advanced GPS signal processing techniques. In this paper, a pure software GPS receiver, developed in the PLAN group of the University of Calgary, is described in detail. Test results proved the effectiveness of the receiver. INTRODUCTION With the increasing requirements of location-based service, GPS is being used for many promising applications, such as E-911, wireless location, and

vehicular navigation. In these applications, GPS receivers are generally integrated with other devices as location sensors and the signal environments, unlike that of conventional GPS, are challenging, such as foliage areas, urban canyons and indoors. In order to be able to use GPS receivers in these environments, high sensitivity technologies needs to be used. Compared to conventional hardware GPS receivers, software GPS receivers are more suitable for research and development and for deep integration with other sensors.. A conventional hardware receiver is normally based on ASIC chips of which the RF part comprises the down conversion, signal filtering, AGC, sampling, and quantization, while the signal processing part comprises all of the baseband signal processing and navigation solution computation. Although ASIC chips now have very high processing speeds, the chip design is fixed, and a chip cannot be modified to experiment with new signal tracking techniques. Pure software GPS receivers, on the contrary, realize all GPS functions in software, which obviously makes the above experimentation possible. Even more important is that, besides a front end, a software receiver does not require any other hardware, so it can work just as a software module and share system resources such as power, onboard memory and processor, with other subsystems. As a consequence, many research groups have undertaken the development of software receivers in recent years (e.g., Akos et al 2001, Ledvina et al 2003, Jovancevic et al 2003). The software GPS receiver developed in the PLAN group of the University of Calgary is described herein. This includes a high level description of the receiver architecture together and the hardware front end used, the fast FFT-based acquisition method, the state Mechanism for channel monitoring, and sample results.


SYSTEM ARCHITECTURE The L1 C/A contains the modules shown in Figure 1.

Front End

Acquisition

Tracking Loop

Measurement Derivation

Inner Clock Generation

Receiver Monitoring

Sub-frame Synchronization

Amplifier

Antenna

Navigation Solution

Front End

Acquisition

Tracking Loop

Measurement Derivation

Inner Clock Generation

Receiver Monitoring

Sub-frame Synchronization

Amplifier

Antenna

Navigation Solution

Figure 1: Receiver Architecture The front end is the only hardware module in the receiver. Made by Accord Inc, the front end, named the GPS Signal Tap (2003), has an intermediate frequency (IF) of 15.42 MHz and a variable sampling rate from 2 MHz up to 20 MHz. The number of quantization bits can be chosen as 1 or 2 bits. The second module is the signal acquisition module where the FFT-based signal acquisition scheme is realized. Three steps are consisted in the acquisition process. The first is noise floor computation, the second is coarse acquisition, and the third is Doppler refinement. The tracking module is key in the receiver. A tracking state Mechanism is created to coordinate signal tracking to switch among bit synchronization, coarse FLL tracking, refined FLL tracking, coarse PLL tracking, and refined PLL tracking. The measurement derivation module is used to measure the transmit time and the carrier of the incoming signal; the pseudorange and carrier phase measurements can thus be obtained by comparing such measurements to those corresponding to local receiver time. The subframe synchronization module is driven by incoming message bits and coordinated by a subframe state Mechanism. Currently, the first three subframes are decoded to extract ephemeris data used for receiver position and clock bias computation. An epoch-by-epoch least-squares method is used in the navigation solution computation. Since the position of satellites and the position of the receiver corresponds to different times, special care has to be taken to handle the Earth rotation between signal transmit time and signal receive time. Although small, the inner clock time generation module is a very important module because such clock is used to

simulate local GPS time and to synchronize and coordinate all modules of the software receiver. SIGNAL FRONT END The architecture and the front end are shown in Figure 2 and 3, and the specifications of the latter are given in Table 1.

Figure 2: Architecture of Signal Tap

Figure 3: Accord Signal Tap

Table 1: Specifications of Signal Tap

2 bitsADC quantization

±1.5ppm long term stability over temperature, 1.5ppm short term Stability

Clock Parameters

2 MHz at 15.42MHzIF bandwidth

2 MHz to 20 MHz (configurable at step size of 1kHz)

Sampling rate

C/AGPS code

GPS L1 at 1575.42 MHzFrequency

2 bitsADC quantization

±1.5ppm long term stability over temperature, 1.5ppm short term Stability

Clock Parameters

2 MHz at 15.42MHzIF bandwidth

2 MHz to 20 MHz (configurable at step size of 1kHz)

Sampling rate

C/AGPS code

GPS L1 at 1575.42 MHzFrequency

A value of 4.75 MHz is selected as the sampling rate because the signal frequency before ADC is 15.42 MHz with a 2 MHz bandwidth and such a sampling frequency results in a direct frequency transition without frequency aliasing, as discussed by Tsui (2000). Besides this, such a


low sampling rate can also reduce the computational burden during signal correlation. SIGNAL ACQUISITION The mathematical expression of a L1 C/A code GPS signal is ( ) ( ) ( ) ( )( ) ( )tntttDtACtr c ++−−−= φτωττ sin (1)

where cω is the carrier frequency, A is the signal amplitude, ( )tC is the C/A code, ( )tD is the navigation message, τ is the propagation delay, φ is the initial phase offset, and ( )tn is the receiver noise. The navigation message is a low frequency signal while the C/A code and carrier phase are high frequency signals. To receive a GPS signal, these two high frequency components have to be acquired and tracked. So, signal acquisition is a two-dimension search process. The FFT-based acquisition method is used in the receiver, and the theory is briefly summarized as follows. The multiply-accumulation operation in signal acquisition is actually the calculation of the correlation between the incoming signal and the local reference signal,

( ) ( ) ( )∑−

=+=

1

0

N

mnmymxnz (2)

The DFT of ( )nz in the frequency domain can be derived as ( ) ( ) ( )KYKXkZ *= . (3)

Thus the correlation of the received signal and the local reference signal can be calculated as follows ( ) ( )( ) ( )( )( )( )nyFFTCONJnxFFTIFFTnz *= (4)

It is obvious that three FFT operations can complete the PRN code offset search at one frequency bin. The exact acquisition procedure implemented in this receiver is illustrated in Figure 4 and several methods were applied to further reduce the computational burden. First, the input signal is common to all channels no matter which satellite is being acquired, so the FFT of the incoming signal after multiplying all possible local carriers can be conducted only once for every satellite. Obviously, the more the satellites under acquisition, the more saving can be achieved with the computational load. Second, the FFTs of the local C/A codes do not change, so they can be computed in advance and saved in a buffer.

As the result, the number of FFTs required is reduced by one third.

Figure 4: Acquisition by FFT

Finally, a special FFT calculation method implemented by Nielsen (2004) is used. With some approximations, this method can perform complex FFT computations with a very high speed. An important issue to be solved in signal acquisition is frequency refinement. As discussed by Ward (1996), the largest frequency bin size is about ( )T∆32 where T∆ is the coherent integration time. It is obvious that frequency estimation accuracy will be high if longer coherent integration time is used. However, the computation load will be significantly increased as well because the search points will dramatically increase with the increase of integration time. For example, if the coherent integration is 1 ms, the largest bin size in this case is about 667 Hz and thus the Doppler frequency error in the coarse acquisition can be up to 333 Hz. But the number of searching points in this case is only about 15 if the Doppler searching range is from -5 kHz to 5 kHz, and each point need only three 1 ms FFT’s. If the coherent integration time is 10 ms, the largest bin size is 66.7 Hz. The number of search points in this case is about 150 with the same Doppler search range, from -5 kHz to 5 kHz, and each point requires three 10 ms FFT instead of three 1 ms FFT. It means that computational burden will increase at least by a square law. An analytic frequency refinement method based on the shape of the correlation waveform is used to simultaneously reduce acquisition time and improve frequency estimation accuracy. It works well when the C/N0 is above 32~35 dB-Hz and can be simply described by the following mathematical derivation. After down conversion, sampling and quantization, the incoming L1 C/A code GPS signal is

( ) ( )( ) ( )kkkkBkksk

kkkkBkksk

DACtfDACQDACtfDACI

φφφφ

sinsincoscos

0

0

=+==+=

(5)


where Bf is the signal frequency. During acquisition, this incoming signal needs to be sequentially pre-processed by Doppler removal, correlation, accumulation and dump. Assuming that the local carrier for a searching point is φref = fref ⋅ tk + φref

0 , the output of Doppler removal will be

( ) ( )( ) ( )φφφ

φφφ

∆+∆=+=

∆+∆=−=

kkkrefkkksk

kkkrefkkksk

ftDACDACQ

ftDACDACI

sinsin

coscos (6)

where

refk

refB fff

φφφ −=∆

−=∆ (7)

The correlation is actually a dispreading process since it tries to remove the C/A code by multiplying the output of Doppler removal with a locally generated C/A code. The correlation result is

( )( )φ

φ

∆+∆=

∆+∆=

kkrefksk

kkrefksk

ftDCACQ

ftDCACI

sincos

(8)

Accumulating for EM points within one navigation message bit, the output is

( )( )

( )( )∑ ∆+⋅∆=

∑ ∆+⋅∆=

=

=

E

E

M

kkrefk

M

kkrefk

tfCCADQ

tfCCADI

1

1

sin

cos

φ

φ (9)

When EM is large enough as in this case, the refkCC can be statistically replaced by the auto-correlation function, ( )τR , so the output of the accumulation is

( ) ( )

( ) ( ) ( )

( ) ( )

( ) ( ) ( )φπππτ

φτ

φπππτ

φτ

∆+⋅∆⋅∆⋅∆

=

∑ ∆+⋅∆=

∆+⋅∆⋅∆⋅∆

=

∑ ∆+⋅∆=

=

=

TfTf

TfADRM

tfADRQ

TfTf

TfADRM

tfADRI

E

M

kk

E

M

kk

E

E

sinsin

sin

cossin

cos

1

1

(10)

In acquisition, the signal amplitude, 22 QIG += , is normally used which is obviously of the following form

( ) ( )Tf

TfARMG E ⋅∆⋅∆

=ππτ sin (11)

Figure 5 shows a two-dimensional plot of the acquisition result of a set of real GPS data. It proves the above

mathematical derivation that the waveform of acquisition variable G in the frequency dimension is the absolute value of a sinc function as predicted in the above equation.

Figure 5: Two-Dimensional Search for Acquisition

When the coherent integration time is chosen as 1 ms, G will have a normalized waveform as illustrated in Figure 6. Here, the horizontal axis represents the acquisition frequency error and the vertical axis represents the normalized signal amplitude. Four vertical lines represent three frequency bins of which the width is 666 Hz. The highest peak in acquisition must be in the central bin. Without losing generality, three searching points, denoted by L, P, and R, are shown in the figure.

-2000 -1500 -1000 -500 0 500 1000 1500 20000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency (Hz)

Nor

mal

ized

Acq

uisi

tion

Var

iabl

e

L

P

R

Figure 6: Normalized Acquisition Waveform in

Frequency Dimension It is evident that the signal amplitudes of the search point L, P, and R are a function of the frequency error. A discriminator can be constructed to derive such frequency error based on the measured amplitudes at L, P, and R. In the software receiver, the following discriminator is used.

P

RL

GGGF −

= *5 (12)


The discriminator is a function of the acquisition frequency error as illustrated in Figure 7 where the horizontal axis represents the frequency error and the vertical axis represents the discriminator output.

-500 -400 -300 -200 -100 0 100 200 300 400 500-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

F

Frequency Error (Hz)

Discriminator for Frequency Refinement

-500 -400 -300 -200 -100 0 100 200 300 400 500-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

F

Frequency Error (Hz)

Discriminator for Frequency Refinement

Figure 7: Acquisition Error Discriminator

The final frequency estimate is derived by removing the frequency error from the coarse frequency estimate as follows:

( )Fmff Pacq −= (13) where Pf is the estimated frequency from the coarse acquisition and ( )Fm is the frequency correction calculated from the discriminator output. Figure 8 shows the final frequency error when the discriminator output is approximated with a linear function. The error can be as large as 20 Hz when the frequency error in coarse acquisition is less than 333 Hz. Figure 9 shows the final frequency error when the discriminator is approximated with the following third order polynomial: ( ) FFFm 5.204135.4 3 +−= . (14)

where F is the discriminator output. In this case, the final frequency error can be decreased to 2~3 Hz when the frequency error in coarse acquisition is less than 333 Hz. In reality, the estimation error may reach tens of Hertz even using the third order polynomial fitting because of the existence of noise.

-500 -400 -300 -200 -100 0 100 200 300 400 500-50

-40

-30

-20

-10

0

10

20

30

40

50

Fina

l fre

quen

cy e

rror

(Hz)

Coarse frequency error (Hz) -500 -400 -300 -200 -100 0 100 200 300 400 500

-50

-40

-30

-20

-10

0

10

20

30

40

50

Fina

l fre

quen

cy e

rror

(Hz)

Coarse frequency error (Hz) Figure 8: Frequency Error with a Linear

Approximation of the Acquisition Error Discriminator

-500 -400 -300 -200 -100 0 100 200 300 400 500-5

-4

-3

-2

-1

0

1

2

3

4

5

Fina

l fre

quen

cy e

rror

(Hz)

Coarse frequency error (Hz) -500 -400 -300 -200 -100 0 100 200 300 400 500-5

-4

-3

-2

-1

0

1

2

3

4

5

Fina

l fre

quen

cy e

rror

(Hz)

Coarse frequency error (Hz) Figure 9: Frequency Error with a Third Order

Approximation of the Acquisition Error Discriminator In summary, the acquisition method proposed in the receiver contains two steps, coarse acquisition and analytic frequency refinement. For coarse acquisition, a 1 ms coherent integration and a 666 Hz frequency bin size are used, so the Doppler frequency error can be up to 333 Hz. During refinement, the acquisition waveform is sampled around the candidate frequency point derived from coarse acquisition, and polynomial fitting the output of the error discriminator reduces the frequency error down to several Hz. As shown in the test section, this method works well when GPS signal is stronger than 32~35 dB-Hz because 1 ms coherent integration is used in coarse acquisition. Higher sensitivity can be achieved if longer coherent integration time is used. SIGNAL TRACKING The acquisition approach discussed above gives the initial estimates of the Doppler and code offset, then control will be handed over to tracking loops to track the variations of carrier phase and code offset due to the line of sight movement between satellites and the receiver. Conventional DLL/FLL/PLL based tracking loops (Raquet, 2004) were implemented in the software GPS receiver as illustrated in Figure 10.


DopplerRemoval

sin cos

Correlator Accumulator(Predetection Filter)

Coder

Code NCO(time, time rate)

DLLDiscriminator

PLLDiscriminator

FLLDiscriminator

Phase NCO(frequency)

DLLLoop Filter

PLLLoop Filter

FLLLoop Filter

I/Q I/Q

IE/QE

IP/QP

IL/QL

IE/QE

IL/QL

IP/QP

E P L

Pulse

δτ

δφ

δf

τδ &̂

f̂δ

τδ &̂Carrier Aiding

f̂ Scaled to

RXt

SVtPseudorange

IntegrationPhase

Doppler

DopplerRemoval

sin cos

Correlator Accumulator(Predetection Filter)

Coder

Code NCO(time, time rate)

DLLDiscriminator

PLLDiscriminator

FLLDiscriminator

Phase NCO(frequency)

DLLLoop Filter

PLLLoop Filter

FLLLoop Filter

I/Q I/Q

IE/QE

IP/QP

IL/QL

IE/QE

IL/QL

IP/QP

E P L

Pulse

δτ

δφ

δf

τδ &̂

f̂δ

τδ &̂Carrier Aiding

f̂ Scaled to

RXt

SVtPseudorange

IntegrationPhase

Doppler

Figure 10: Tracking Loops Implemented

To track an incoming GPS signal, both carrier phase and C/A code need to be matched by the locally generated counterparts. As a result, the carrier locked loop (FLL or PLL) and delay locked loop need to be coupled together as shown in Figure 10. Once one of them loses lock, the other one will lose lock as well. Generally, the carrier loop is a weaker loop because the carrier wavelength is much shorter than the chip length and the carrier loop needs to track all dynamics while the code loop needs only to track the dynamic difference between carrier loop and code loop when carrier aiding is applied to code loop. Since the basic tracking loop theory has been extensively discussed by quite a few researchers based on classic control and phase locked loop theory, this part is skipped here. Instead, only the specific techniques implemented in the software receiver are briefly summarized. C/N0 estimation is conducted based on the algorithm discussed by Van Dierendonck (1996). The estimation accuracy depends on the a priori knowledge of the bit transition and can be improved by averaging many C/N0 estimate samples. Bit synchronization is realized using an histogram technique which is also discussed by Van Dierendonck (1996). As shown in Figure 11, twenty counters are set to keep track of the number of bit transition for all boundaries between two 1-ms C/A code sequences. The bit boundary is assumed to be successfully located when the counter of one bin exceeds the upper threshold NBS1; it is not assumed to be successfully located when two counters exceed the lower threshold NBS2. NBS1 and NBS2 are functions of SNR and the length of the time for bit transition counting, and can be determined from the equations in the above reference.

0 2 4 6 8 10 12 14 16 180

5

10

15

20

25

30

Bin number

Bin

coun

ts

NBS1

NBS2

Threshold 1

Threshold 2

0 2 4 6 8 10 12 14 16 180

5

10

15

20

25

30

Bin number

Bin

coun

ts

NBS1

NBS2

Threshold 1

Threshold 2

Figure 11: Bit Synchronization Histogram

The DLL used is a second order tracking loop. Although all DLL discriminators discussed by Ward (1996) can be chosen, the normalized early-minus-late envelope discriminator described below is selected as the default one because it is good within +/- 1.5 chip code error, which is the widest among all candidate DLL discriminators. This becomes evident in Figure 12 which illustrates the change in the DLL discriminator output with respect to the code error.

-1.5 -1 -0.5 0 0.5 1 1.5-1.5

-1

-0.5

0

0.5

1

1.5

True input error (chips)

DLL

dis

crim

inat

or o

utpu

t (ch

ips)

Dot product powerEarly minus late powerEarly minus late envelopeNormalized early minus late envelope

Figure 12: DLL Discriminator

To improve code tracking performance, narrow correlation technique can be used. In the receiver, the interval between the early reference code and the late reference code can vary from 0.1 chips to 1 chip. The FLL used can be either a second or third order FLL. The discriminator used in the receiver is the decision-directed cross-product discriminator expressed as

( ) ( )1111 −−−− +−= iiiiiiiii QQIIsignQIQIfδ (15) where iI and iQ are current integration components,

1−iI and 1−iQ are previous integration time. The advantage of this discriminator is that it is insensitive to data bit transition, but the output is not linear with respect to the frequency error and the effective range is smaller than that of the arctangent discriminator.


The PLL used in the receiver can also be a second or third order PLL. The discriminator used here is a four-quadrant arctangent discriminator because the output of the discriminator is linear with respect to the phase error. Further more, it is optimal in the maximum likelihood sense at both low and high SNR. The mathematical equation is ( )IQ,2arctan=φ , where I and Q are the current coherent integration results. To work reliably, the receiver channels generally need to be monitored and coordinated by some mechanisms. In this software receiver, a simple mechanism, named the WN_Mechanism as shown in Figure 13, is used to switch the channel status between acquisition, wide bandwidth FLL tracking, narrow bandwidth FLL tracking, wide bandwidth PLL tracking, and narrow bandwidth PLL tracking.

ACQ

WFLL

NFLLWPLL

NPLL

1

1

1

1

1

2

2

2

2

2

3

3

3

44

ACQ

WFLL

NFLLWPLL

NPLL

1

1

1

1

1

2

2

2

2

2

3

3

3

44

Figure 13: State Mechanism of a Channel

(WN_Mechanism) ACQ stands for signal acquisition state where a two-dimensional search in code offset and Doppler frequency offset is conducted. If a correlation peak is successfully identified, the channel will move forward to wideband frequency tracking loop, otherwise, the channel will stay in acquisition state. It is evident that the key point in acquisition state is to establish a suitable criterion to reliably detect the correlation peak. Tong search strategy, discussed by Ward (1996), is realized here. For each single trial, the detection threshold is derived by )ln(2 fant PV −= σ where nσ is 1-sigma

noise amplitude in the I and Q components and faP is the probability of false alarm. nσ can be simply estimated

from the acquisition variable 22 QIG += which is a Rayleigh distribution when no signal exists. Such an estimate can be expressed as

∑==

N

iin G

N 1

2

21σ̂ . (16)

WFLL stands for the wide bandwidth frequency tracking state where a second order frequency locked loop with a loop bandwidth of 10 Hz is used to track the incoming signal frequency. To detect if the signal frequency is successfully locked or not, a frequency lock detector of the following form is applied:

( ) ( )( )kkkk

kkkkkkkkF QQII

QQIIsignQQIIL

⋅+⋅⋅+⋅⋅⋅−⋅

= −−−− 1111 . (17)

Substituting Equation (10) into the above formula, the lock detector can be simplified as

⎟⎠

⎞⎜⎝

⎛ ∆+∆= − T

ffL kk

F 22cos 1π , (18)

where T is the coherent integration time, 1−∆ kf and kf∆ are the frequency errors in two consecutive coherent integration intervals. Obviously, FL is a function of frequency error and will approach 1 when the frequency is successfully tracked as shown in Figure 14. However, the output in Figure 14 is very noisy and cannot be reliably used in the receiver. To remove the noise, a very simple low pass filter, as shown in Figure 15, is used to smooth the lock detector output. Figure 16 is the smoothed result and it reaches 1 when the signal frequency is accurately tracked. In the software receiver, a threshold 9.0=T

FWNL is used to switch the frequency tracking loop from a wide bandwidth frequency tracking to a narrow bandwidth frequency tracking. Three possible transition may occur when the channel resides in WFLL states: it will transfer to narrow bandwidth frequency tracking when T

FWNF LL > ; it will stay in WFLL when TFWNF LL < ; it will return back to acquisition when 0NC is

smaller than a threshold, say 27 dB-Hz, which means the signal lock is probably lost.

0 2000 4000 6000 8000 10000-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

Epoch

FLL Lock Detector (Not Averaged)

Figure14: Original FLL Lock Detector


Z-1

α = 0.01

(1- α)= 0.99

F(n) L(n)

L(n-1)Z-1

α = 0.01

(1- α)= 0.99

F(n) L(n)

L(n-1)

Figure 15: Smoothing Filter

Figure 16: Smoothed FLL Lock Detector

NFLL stands for narrow bandwidth frequency tracking before bit synchronization is achieved. The only difference from WFLL is the loop bandwidth. In NFLL, the bandwidth is reduced from 10 Hz to 4 Hz. Four possible transitions may occur when the channel resides in the NFLL state: it will transfer to wide bandwidth phase tracking when the bit synchronization is completed; it will stay in NFLL when T

FNWF LL > which is selected as 0.75 herein; it will return to WFLL when T

FNWF LL < ; it will return directly back to acquisition when the 0NC becomes smaller than a threshold, say 27 dB-Hz, which means the signal lock is lost. WPLL and NPLL stand for wide bandwidth and narrow bandwidth phase tracking states. The loop bandwidth of WPLL is 18 Hz and the loop bandwidth for NPLL is 10 Hz. The transition between them is determined by the following phase lock detector (Van Dierendonck 1996):

( )kk

kkC φφ 2cos

NBPNBD

2 ≈= (19)

where 2

1

2

1⎟⎠⎞⎜

⎝⎛∑−⎟

⎠⎞⎜

⎝⎛∑=

==

M

ii

M

iik QINBD (20)

and 2

1

2

1⎟⎠⎞⎜

⎝⎛∑+⎟

⎠⎞⎜

⎝⎛∑=

==

M

ii

M

iik QINBP (21)

Figure 17 shows the change of PLL lock detector with respect to tracking time. Obviously, the above PLL lock

detector is a function of the phase error and will approach 1 when the phase error becomes small. Similarly, two thresholds are selected to switch phase tracking between WPLL and NPLL. If a channel is in WPLL state, it will switch to NPLL state when 9.02 => PWNk LC φ ; if it is in NPLL state, it will switch to WPLL state when

75.02 =< PNWk LC φ . A channel in either WPLL or NPLL state may return directly back to the acquisition state if the 0NC is so low that lock is assumed to be lost.

0 2000 4000 6000 8000 10000 12000 14000 16000 180000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Epoch

C2φ

k

PLL Lock Detector

Figure 17: PLL Lock Detector

TEST RESULTS Test Setup Tests have been conducted to prove the correctness of the software GPS receiver. The test platform is shown in Figure 18 where three types of GPS signals can be used. The first type is the true GPS signal received from an antenna, the second type is the simulated signal generated by a hardware GPS simulator, and the third type is the simulated signal generated by the software GPS signal simulator which was developed by Dong & Lachapelle. (2004). The first two types of GPS signals are RF signals with L1 as the central frequency, so a hardware front end is required to down convert the signal and to transform the analog signal into digital signal samples. The software simulator generated signal, on the contrary, consists directly of digital signal samples, so it does not require a hardware front end. Such a software signal simulator is highly flexible, for example, it allows unlimited simulation time, and enables simulation of all kinds of GPS errors, including that of deteriorated propagation channels due to interference and spoofing. In this section, both software simulated and true GPS signals are used to investigate acquisition and tracking performance in both static and dynamic mode.


SoftwareSimulator

SoftwareGNSS Receiver

Splitter

Front-end

Referencereceiver

Hardware Simulator

LNA

GPS Antenna

SoftwareSimulator

SoftwareGNSS Receiver

Splitter

Front-end

Referencereceiver

Hardware Simulator

LNA

GPS Antenna

Figure 18: Test Platform Acquisition Performance As discussed previously, the acquisition algorithm used in the receiver is a two-step method. The first step is coarse acquisition where the FFT-based two dimensional search is conducted using an 1 ms coherent integration, and the second step is a fine acquisition where an acquisition waveform-based interpolation method is used. Figure 19 demonstrates the 1-σ frequency error when the non-coherent time is 20 ms and 30 ms, respectively. The test is a Monte Carlo simulation and 1,800 independent tests were conducted to compute the frequency estimation error for each point. It is evident that the resulting frequency error is less than 100 Hz when the C/N0 is above 32 dB-Hz, and the stronger the received signal is, the higher the frequency estimation accuracy is. Although the frequency estimation accuracy is higher in the 30 ms non-coherent integration case, both estimates are accurate enough for FLL to converge.

30 35 40 450

20

40

60

80

100

120

140

160

180

200

C/N0 (dB-Hz)

One

σ F

requ

ency

Err

or (H

z)

Fine Acquisition

20 1ms coherent integration30 1ms coherent integration

Figure 19: Frequency Error after Fine Acquisition

Receiver Performance in Static Mode The data used is true GPS data received by an antenna located at a known point with WGS84 latitude, longitude, and height of 51º05’, 114º08' and 1120 m. The Signal Tap was used to log GPS signal samples. The sampling rate was 4.75 MHz and the quantization bit was 1. The time length of the data here is 80 seconds. Performance in the signal and position domains are shown for PRN 13, although five satellites are available in the test. Figure 20 and 21 show the I and Q components of the PRN 13 after 1 ms integration and dump. It is clear that,

when the signal is correctly tracked, the Q component is pretty much noise-like and the I component contains almost all the signal power. These two figures are key figures because they show the signal tracking quality and determine the overall receiver performance.

Figure 20: In-phase Component - Static Test

Figure 21: Quadrature Component - Static Test Figure 22 and 23 show the outputs of the PLL discriminator and PLL loop filter, which are the indicators of PLL tracking quality. The output of the PLL discriminator is actually the phase difference between the incoming signal and the local reference signal. From Figure 22, one sigma of such phase error is around 5-8 degrees, which means the PLL remains in a good tracking status. The output of the PLL loop filter, shown in Figure 23, is essentially the Doppler frequency. It is now due only to the satellite movement with respect to the Earth since the receiver is static.

Figure 22: Output of PLL discriminator

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 104

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

number

Out

put o

f PLL

dis

crim

inat

or (c

ycle

s)

PRN 13

2 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.1

x 104

-800

-600

-400

-200

0

200

400

600

800

time (ms)

Q P

unct

ual

PRN 13

2 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.1

x 104

-800

-600

-400

-200

0

200

400

600

800

time (ms)

I Pun

ctua

l

PRN 13


Figure 24 and Figure 25 show the output of the DLL discriminator and DLL loop filter, which are indicators of the DLL tracking quality. The output of the DLL discriminator is actually the code phase difference between the incoming signal and the local reference signal. One sigma of such a code phase error is around 0.01 chips degrees, which means the DLL tracking is healthy. The output of the DLL loop filter is in fact code Doppler frequency in chip/second.

Figure 23: Output of PLL Loop Filter (Essentially

Doppler) It is worth noticing that a jump from about 2.2 chip/second down to about 0 chip/second occurs in the output of DLL loop filter. This is due to the inline clock calibration implemented in the software GPS receiver. The nominal value of the oscillator used in the Signal Tap is a 10 MHZ oscillator, and the nominal sampling frequency chosen in the test is 4.75 MHz. However, the true sampling frequency, due to the clock error, is not 4.75 MHz, so a constant code Doppler frequency error will appear in the DLL if the nominal 4.75 MHz sampling frequency is used. In the receiver, an inline calibration method is designed to remove such sampling frequency error by investigating clock bias and drift derived from navigation solution since such sampling frequency error will go directly into the receiver time error. It is obvious from the Figures that the code Doppler frequency error due to the sampling frequency error can be removed by such a calibration method.

Figure 24: Output of DLL Discriminator

Figure 26 shows the C/N0 estimation. Obviously, the C/N0 is lower during the convergence period, and becomes stable when stable phase and code lock is achieved. Figure 27 is the positioning error in the horizontal plane. It can be seen that the RMS of the horizontal error is less than 5 m, which means that the receiver yields a satisfactory positioning accuracy.

Figure 25: Output of DLL Loop Filter

Figure 26: C/N0 Estimate of PRN 13

Figure 27: Horizontal Positioning Error

Receiver Performance in Dynamic Mode Dynamic tests were conducted to show the tracking capability of the receiver in high dynamic situations. The

-30 -20 -10 0 10 20 30-30

-20

-10

0

10

20

30

Horizontal RMS: 2.7 m

West-East Error (m)

Nor

th-S

outh

Erro

r (m

)

Horizontal Solution

-30 -20 -10 0 10 20 30-30

-20

-10

0

10

20

30

-30 -20 -10 0 10 20 30-30

-20

-10

0

10

20

30

Horizontal RMS: 2.7 m

West-East Error (m)

Nor

th-S

outh

Erro

r (m

)

Horizontal Solution

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 104

-1710

-1700

-1690

-1680

-1670

-1660

-1650

-1640

-1630

-1620

-1610

number

Out

put o

f PLL

loop

filte

r (H

z)

PRN 13

0 1 2 3 4 5 6 7 8 9 10

x 104

0

5

10

15

20

25

30

35

40

45

50

time (ms)

C/N

0

PRN 13

0 1000 2000 3000 4000 5000 6000-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

number

Out

put o

f DLL

loop

filte

r (ch

ips/

seco

nd)

PRN 13

0 1000 2000 3000 4000 5000 6000-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

number

Out

put o

f DLL

dis

crim

inat

or (c

hips

)

PRN 13


dynamic test presented below is simulated by the software GPS signal simulator. The simulation date is July 6th, 2004, and the starting GPS time is 208800 seconds, and the starting point is Calgary. The receiver motion consists of five stages. The first stage of 15 seconds is a static warm up period; the second stage of 25 seconds consists of a constant acceleration of 5 m/s2 in the northern direction; the third stage of 25 seconds includes a right turn circular movement with a constant speed of 125 m/s and a radius of 500 m; the fourth stage of 40 seconds is a linear motion with a constant speed of 125 m/s; and the final stage is a left turn circular motion with a constant speed of 125m/s and a radius of 400 m. Using the above simulation parameters, the true trajectory, velocity, acceleration and absolute jerk in the local level frame are shown in Figure 28 to 31.

0 20 40 60 80 100 120 140-2000

0

2000

4000

6000

8000

Test Time (s)

m

Eastern PositionNorthern Position

-1000 -800 -600 -400 -200 0 200 400 600 800 10000

2000

4000

6000

8000

Eastern (m)

Nor

ther

n (m

)

Figure 28: Trajectory of the Dynamic Test

0 20 40 60 80 100 120 140-150

-100

-50

0

50

100

150

Test Time (s)

m/s

Eastern VelocityNorthern Velocity

Figure 29: Receiver Velocity

0 20 40 60 80 100 120 140-50

-40

-30

-20

-10

0

10

20

30

40

50

Test Time (s)

m/s

2

Eastern AccelerationNorthern AccelerationTotal Acceleration

Figure 30: Receiver Acceleration

0 20 40 60 80 100 120 1400

5

10

15

20

25

30

35

40

45

Test Time (s)

m/s

3

Jitter

Figure 31: Absolute Receiver Jerk

It is obvious from these figures that high acceleration (up to 5g) occurred during the circular motion and serious jerks occurred during the transition between constant acceleration and circular motion. These will have an adverse impact on the tracking loops, especially to the FLL and PLL loops, since they need to track all dynamics and are weaker tracking loops thatn the DLL loops. In the following, receiver performance under two types of channel monitoring mechanisms is compared in both the position and tracking domain. The first mechnism is the WN_mechanism shown in Figure 13, where a receiver channel switches among WFLL, NFLL, WPLL, and NPLL, based on the FLL and PLL lock detectors. The second mechanism is the adaptive FLL-Assisted-PLL mechanism, where the FLL and PLL loops are used simutaneously so there is no such concepts as WFLL, NFLL, WPLL, NPLL. However, an adaptive loop bandwidth is still applied to simulate the bandwidth difference between coarse and refined tracking. Receiver Performance Using WN_Mechanism Here, the loop bandwidth of the WFLL and NFLL is fixed at 10 Hz and 4 Hz, while that of the WPLL and NPLL is fixed at 18 Hz and 10 Hz. Figure 32 shows the tracking status of all satellites during the test. In the software receiver, each state is assigned a specific value: 1 for coarse acquisition, 2 for fine acquisition, 4 for WFLL, 8 for NFLL, 16 for WPLL, 32 for NPLL, 64 for bit synchronization, and 128 for sub frame synchronization. The first four states are exclusive, and the latter two can exist together with other states. Bit and subframe synchronizations are not affected by state switching among WFLL, NFLL, WPLL, and NPLL. But they are assumed lost when satellite tracking fails and acquisition has to be reconducted. Thus, from the change of bit synchronization and subframe synchronization, one can easily assess the tracking quality of a channel. It is evident from the figure that quite a few channels lose lock during the test, and the time of lock loss corrsponds to the time when strong jerks occurs. This result demonstrates that the state mechanisms shown in Figure 13 is not


robust when the dynamic is very high. This is because the FLL and PLL did not operate at the same time. Although the NPLL is of higher accuracy, its stable tracking region is very small and it collapses in high dynamic situations.

Figure 32: Satellite Tracking Status Using

WN_Mechanism Figure 33 and Figure 34 illustrate the horizontal position error, DOP, and the number of satellites used. It is evident that the position accuracy deteriorates when strong jerk occurred and the number of satellites available decreases.

-10

0

10Positioning Error (FLL: 10/4 Hz PLL: 18/10 Hz)

E-W

-10

0

10

N-S

0 20 40 60 80 100 120 1400

5

10

Test Time (s)

Hor

izon

tal

Figure 33: Horizontal Error Using WN_Mechanism

Figure 35 to 38 show the effect of high dynamic on signal tracking for PRN 7. Figure 35 shows both the I and Q components with a 1 ms integration and dump. Large peaks occurs in the Q component when strong jerk occurs, which means that phase tracking seriously deteriorates. Figure 36 and 37 show the PLL and FLL lock detectors. Obviously, both FLL and PLL tracking become worse when jerk occurs. Figure 38 shows the C/N0 estimate, which is quite low when receiver dynamic is high.

0.5

1

1.5

2

2.5

3DOP & SV Number (FLL: 10/4 Hz PLL: 18/10 Hz)

DO

P

North DOPEast DOPHorizontal DOP

0 20 40 60 80 100 120 1404

5

6

7

8

Test Time (s)

SV

Num

ber

Figure 34: DOP and Number of Satellites Tracked

Using WN_Mechanism

-600

-400

-200

0

200

400

600

I

PRN 7 (FLL: 10/4 Hz PLL: 18/10 Hz)

0 20 40 60 80 100 120 140-500

0

500

Test Time (s)

Q

Figure 35: I and Q Components of PRN 7

0 20 40 60 80 100 120 1400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Test Time (s)

PLL

Loc

k D

etec

tor

PRN 7 (FLL: 10/4 Hz PLL: 18/10 Hz)

Figure 36: PLL Detector of PRN 7


0 20 40 60 80 100 120 1400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Test Time (s)

FLL

Lock

Det

ecto

r

PRN 7 (FLL: 10/4 Hz PLL: 18/10 Hz)

Figure 37: FLL Detector of PRN 7

0 20 40 60 80 100 120 140-5

0

5

10

15

20

25

30

35

40

45

Test Time (s)

C/N

0 (dB

-Hz)

PRN 7 (FLL: 10/4 Hz PLL: 18/10 Hz)

Figure 38: C/N0 Estimate of PRN 7

Receiver Performance Using FLL Assisted PLL To improve the receiver performance in high dynamic situations, adaptive FLL assisted PLL is also implemented in the receiver. Unlike that in WN_Mechanism where FLL and PLL are two exclusive stages, the FLL and PLL loops are working simultaneously in this FLL assisted PLL mechanism where the FLL attempts to catch frequency variations and the PLL attempts to catch the residual phase variations. Such mechanism is more robust in higher dynamic situations, but the disadvantage is the reduced accuracy since the FLL is more noisy than the PLL. A second order FLL assisting a third order PLL is also implemented in the receiver. To simulate the WFLL, NFLL, WPLL, and NPLL, an adaptive bandwidth adjusting scheme, based on the PLL and FLL lock detectors, is used. Figure 39 shows the bandwith variation with respect to the PLL and FLL lock detectors. Figure 40 shows the tracking status of all channels. It is obvious that no loss of lock occurs when strong jerk happens. The horizontal position error, DOP and number of satellites used are shown in Figure 41 and 42. An obvious

improvement can be identified compared to the results when the WN_Mechanism was used.

0 0.2 0.4 0.6 0.8 10

2

4

6

8

10

12

14

16

18

20

Lock Detector

Band

wid

th (H

z)

PLL BandwidthFLL Bandwidth

Figure 39: Adaptive Bandwidth of FLL and PLL

Tracking Loops

Figure 40: Satellite Tracking Status with FLL Assisted

PLL Mechanism

-10

0

10Positioning Error (FLL-Assisted-PLL FLL: 10/4 Hz PLL: 18/10 Hz)

E-W

-10

0

10

N-S

0 20 40 60 80 100 120 1400

5

10

Test Time (s)

Hor

izon

tal

Figure 41: Horizontal Positioning Error


0.5

1

1.5

2

2.5

3DOP & SV Number (FLL-Assisted-PLL FLL: 10/4 Hz PLL: 18/10 Hz)

DO

PNorth DOPEast DOPHorizontal DOP

0 20 40 60 80 100 120 1404

5

6

7

8

Test Time (s)

SV

Num

ber

Figure 42: DOP and Number of Satellites Used

Similarly, PRN 7 is used to show the tracking quality. Figure 43 shows the I and Q components. The Q component still deteriorates when jerk occurs. However the transition period is much shorter due to the FLL assistance. Figure 44 to 46 show the PLL lock detector, FLL lock detector, and C/N0 estimation. Compared to the results when the WN_Mechanism was used, they were better.

-600

-400

-200

0

200

400

600

I

PRN 7 (FLL-Assisted-PLL FLL: 10/4 Hz PLL: 18/10 Hz)

0 20 40 60 80 100 120 140-500

0

500

Test Time (s)

Q

Figure 43: I and Q Components of PRN 7

0 20 40 60 80 100 120 1400

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Test Time (s)

PLL

Loc

k D

etec

tor


Figure 44: FLL Lock Detector

Figure 45: PLL Lock Detector

0 20 40 60 80 100 120 1400

5

10

15

20

25

30

35

40

45

Test Time (s)

C/N

0 (dB

-Hz)


Figure 46: C/N0 Estimate

The software receiver is already being used for various research tasks, namely interference studies (Deshpande & Cannon 2004, Jiang et al 2004), GPS L5 and Galileo signal analysis, indoor signal acquisition and tracking, and ultra-tight integration with inertial measurement units. CONCLUSIONS AND FUTURE WORK A software GPS receiver, running on a standard PC, is developed and tested in this paper. The only hardware module is the front end, which converts the RF GPS signal to discrete IF samples. The software modules, taking such IF samples as its input, perform the baseband signal processing and navigation solution computation. One contribution of the paper is the proposition of a fast acquisition refinement algorithm, which is based on the fact that the acquisition waveform in the frequency domain is the absolute value of a sinc function. A discriminator is constructed to analytically estimate the frequency error of the coarse acquisition, and then remove


it to get refined the acquisition result. Test results shows that satisfactory frequency accuracy can be achieved if the C/N0 is above 32 dB-Hz. Another contribution is the implementation of a channel monitoring mechanism, namely the WN_Mechanism, based on FLL and PLL lock detectors. Results showed that this mechanism works well in low dynamic situations. In high dynamic situations, adaptive FLL-Assisted-PLL is preferred because the FLL, which is more robust in high dynamic situations, is always working to update carrier loop. REFERENCES Akos, D.M., P.-L. Normark, P. Enge, A. Hansson, and A. Rosenlind (2001). Real-Time GPS Software Radio Receiver, Proc. of the Institute of Navigation National Technical Meeting, January 22-24, 2001, Long Beach, CA. Deshpande, S., and M.E. Cannon (2004) GPS Receiver Acquisition Parameters and Their Effects. Proceedings of GNSS 2004 conference (San Diego, Sep 21-24), The Institute of Navigation. Dong, L., C. Ma and G. Lachapelle (2004). Implementation and Verification of a Software-Based IF GPS Signal Simulator. Proceedings of National Technical Meeting, Institute of Navigation, 26-28 January 2004, San Diego. Jiang, Z., C. Ma and G. Lachapelle (2004) Mitigation of narrow-band interference on software receivers based on spectrum analysis. Proceedings of GNSS 2004 conference (San Diego, Sep 21-24), The Institute of Navigation. Jovancevic, A., A. Brown, S. Ganguly, J. Goda, M. Kirchner and S. Zigic (2003). Real-Time Dual Frequency Software Receiver, Proceedings of ION GNSS 2003, The Institute of Navigation, September 9-12, 2003, Portland, Oregon. Ledvina, B.M., S.P. Powell, P.M. Kintner, and M.L. Psiaki (2003). A 12-Channel Real-Time GPS L1 Software Receiver, Proc. of the Institute of Navigation National Technical Meeting, January 22-24, 2003, Anaheim, CA. Nielsen, J. J. (2004). Arbitrary N FFT C-source, http://hjem.get2net.dk/jjn/fft.htm. Raquet, J. F. (2004), GPS Receiver Design, ENGO 699.10 lecture notes, Dept. of Geomatics Engineering, university of Calgary

Tsui, James B-Y. (2000), Fundamentals of Global Positioning System Receivers: A Software Approach, John Wiley & Sons Inc. Van Dierendonck, A.J. (1996). GPS Receivers, in Global Positioning System: Theory and Applications, Vol. I, Parkinson, B.W. and Spilker, J.J. Jr., eds, American Institude of Aeronautics and Astronautics, (Washington, 1996), pp. 329-407. Ward, P. W. (1996). Satellite Signal Acquisition and Tracking, in Understanding GPS: Principles and Applications, Kaplan, E. D. pp.119-208, Artech House Publishers, Boston, MA, 1996.

Documents

Implementation of a Software GPS Receiver · 2017. 6. 27. · Clock Parameters IF bandwidth 2 MHz at 15.42MHz 2 MHz to 20 MHz (configurable at step size of 1kHz) Sampling rate GPS