IGBT short circuit safe operating area (SOA) capability and testing · 2019-03-08 · Gate signal pulse-width L s Stray inductance from DC-link L SC Short circuit load inductance

— A PPLI C ATI O N NOTE 5S YA 20 9 5 - 01

IGBT short circuit safe operating area (SOA) capability and testing

Today IGBT modules are the most widely used devices in a variety of power electronics applications due to their low loss and intrinsic protection features. In all applications where IGBT modules are used, failure events can occur leading to high fault currents. Under certain conditions together with a well-designed gate drive circuit, IGBT modules can limit current and withstand the fault. The aim of this application note is to describe the different short circuit failure modes and the corresponding test setups. Common protection circuits are discussed and examples under various conditions are given, which show the principal short circuit characteristics. The short circuit event is not a normal operation mode and should always be avoided.

1. Introduction Short Circuit (SC) - modesIGBT modules are used in voltage source converters as shown in Figure 1. A short circuit (SC) event can happen at any time and in any state of a converter. Parameters as the DC-link voltage, the current am-plitude or the current direction in the different paths as well as the location of the SC in the con-verter are defining the SC current and therefore the corresponding SC mode (see Table 1).

Standards, for example IEC60747-9 [STD1], define SC failures mode 1 and mode 2. Other SC-modes men-tioned above are not yet defined by standards.In high power SC events if the involved semiconduc-tors are not able to turn off high overcurrent, the maximum energy stored in the DC-link capacitor will be discharged at the failure location. As a result, sig-nificant destruction occurs with consequential dam-age followed by high repair costs. However, robust SC capable IGBTs can reduce these impacts.Each IGBT has typically freewheeling diodes in paral-lel. Moreover, depending on the design and state of a converter, freewheeling diodes under the case of SC can be loaded with high surge currents of various amplitudes and pulse durations. Therefore, diode surge current capability in the IGBT module has to be taken in account [3]. Extensive production test-ing on IGBT modules are made in order to ensure re-liable operation of ABB’s IGBTs.

SC type Description

SC mode 1 Low inductive single phase short [1]

SC mode 1.5High inductive short in between

phases, IGBT turns-on into SC

SC mode 2Low inductive short in one phase, with

conducting IGBT [5]

SC mode 2.5High inductive short in different

phases, with conducting IGBT

SC mode 3Low inductive short in one phase, with

conducting diode [7]

SC mode 3.5High inductive short in different

phases, with conducting diode

— Table of contents

001 Introduction Short Circuit (SC) - modes 003 Test setups for SC modes examination 003 SC mode 1004 Test procedure 004 Definitions of test-results 005 SC mode 1.5 005 SC mode 2 (SC2) 006 SC mode 3 008 Short circuit related IGBT characteristics 008 The short circuit current ISC vs. Vp, VGE(TO) and VCEsat 008 SC1 vs. Tvj 008 SC1 current vs. Vcc / Ls 009 SC1 vs. VGE, RGon, CGE 009 Externally applied and effective gate voltage 010 Critical/ limiting parameters 010 High gate voltage 010 High di/dt, peak current and peak power 010 High overvoltage 011 High junction temperature 011 Protection circuits 012 Active clamping 013 di/dt counter coupling 013 Production outgoing inspection tests by ABB 014 List of figures 014 Acronyms 015 Bibliography 015 Revision

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—We reserve the right to make technical changes or modify the contents of this document without prior notice. With re-gard to purchase orders, the agreed par-ticulars shall prevail. ABB AG does not ac-cept any responsibility whatsoever for potential errors or possible lack of infor-mation in this document.

We reserve all rights in this document and in the subject matter and illustrations contained therein. Any reproduction, dis-closure to third parties or utilization of its contents – in whole or in parts – is forbid-den without prior written consent of ABB AG. Copyright© 2018 ABBAll rights reserved

—ABB Switzerland Ltd.SemiconductorsFabrikstrasse 35600 [email protected]

abb.com/semiconductors

2. Test setups for SC modes examination To reproduce the different SC modes in case of a failure in the application, different test circuits are used by ABB during characterization of IGBTmodules. The test conditions have to reflect as good as possible the real operation conditions in possible applications. Since all dynamic tests and characteri-zation of ABB’s IGBT’s are done in phase leg configu-ration and one of the IGBT’s is utilized as an auxiliary switch, the SC-modes 2.5 and 3.5 with high induc-tive load (stray inductance) are not possible to test.

2.1. SC mode 12.1.1. Test circuit and conditionsPicture 2 shows the circuit for SC mode 1 testing. The high side (HS) auxiliary switch IGBT is shorted providing low inductive connection (LSC) of Device Under Test (DUT) to DC link.Following table describes test conditions and moni-tored signals:

—01 3-phase voltage source converter

3

HS1

VDC

M

HS2 HS3HS1 HS3

LS2LS1 LS3

Ls

LSC < 10 nH

VGDHS = -15 V

HS IGBT

GDHS

CDC

Rs (x mΩ)

VCC > 0 V

RG

on

VGDLS

RG

off

-VGoff

+

+VGon

-

GDLS

VCE

IC

LS IGBT

VGE

IG

S

1 2

VGon (typ +15 V)

VGoff (typ -15 V)

tSC < 10 µs

VGDLS

t

—02 Test circuit SC mode 1

Test-conditions

VCC DC-link voltage

tSC Gate signal pulse-width

Ls Stray inductance from DC-link

LSC Short circuit load inductance

Tvj Virtual junction temperature

VGon, VGoff

On- and off-state gate-emitter voltage

RGon, RGoff Turn-on/ off gate resistors

Monitored signals

VCE

Collector-emitter voltage, measured differential be-tween

collector and emitter auxiliary terminals

IC

Collector-current, measured with a Rogowski current probe

VGE

Gate-emitter voltage, meas-ured differential between gate and emitter auxiliary terminals

IC / VCE

VGE

t

t

0

0

VGEoff

VGEon

ICM

VCEM

10% (VGEon)

10% (ISC) 10% (ISC)

td(i)on

90% (ISC)

ISC

VCC

50% (ICM)tPW

50% (ICM)

90% (ISC)

35% (tPW) 65% (tPW)

tr(i)on

t(i)on

tf(i)off

VGEmax

td(i)off

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—03 Typical short circuit mode 1 curves and references for pa-rameter calculating

—04 Short circuit mode 1 test at elevating collector-emitter voltage

2.1.2. Test procedure1. The DUT is at the specified junction

temperature Tvj

2. Capacitor CDC charged the to a desired voltage VCC and the DUT is triggered (S 12) with RGon

3. After a specified time (typically 10 µs) the DUT is switched off soft (S 21) with RGoff >> RGon

2.1.3. Definitions of test-resultsTest results are calculated with following set of pref-erences. Whenever possible, they should comply with international standards.

4

Test-results

VCCAverage over the last 10 % of VCE

VCEM

Maximum of VCE obtained by searching the highest value

VGEoff

Average over the first 10 % of VGE signal vector lenght

VGEmax

Maximum of VGE by searching the highest value and then forming the average over a

specified number of data points

VGEon

Average over VGE between 35 and 65 % of tPW

ICM

Maximum of IC by searching the highest value

Test-results

tPW

Current-pulse-width-time referenced to a specified value of IC (50 % of ICM) during rising flank and a specified value of IC (50

% of ICM) during falling flank

ISC

Average over IC between 35 and 65 % of tPW

t(i)on

Current on time referenced to 10 and 90 % of ISC

td(i)on

Turn on delay time referenced to 10% of VGEon and 10 % of ISC

td(i)off

Turn off delay time referenced to 10% of VGEon and 90 % of ISC

tr(i)on

Current rise time referenced to 10 and 90 % of ISC

tf(i)off

Current fall time referenced to 90 and 10 % of ISC

dion/dt

Current turn on slope referenced to 10 and 90 % of ISC (straight line)

dioff/dt

Current turn off slope referenced to 90 and 10 % of ISC (straight line)

ESC1

Short circuit energy is the integration of the product of VCE x IC over a specified

time (typically over the whole measurement window)

Pp(SC1)

Short circuit peak power by searching the highest value of the product VCE x IC

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5

2.2. SC mode 1.5In Figure 5 above the test circuit for SC mode 1.5 is shown. Its high side auxiliary switch HS IGBT is by-passed with desired inductive connection LSC. The difference to the SC1 test is the higher inductance value of LSC, which is between ≈ 10 nH…10 µH to sim-ulate the dynamic behavior of SC on motor termi-nals. The rest of the test setup is equal to the SC1 one.As the rate of current rise depends on the induc-tance (Ls+ LSC), VCE drops with higher inductances up to saturation levels. When current reaches the de-saturation or short-circuit level, VCE rises again with a positive dv/dt slope up to the DC-link voltage level. This positive dv/dt causes a displacement cur-rent through the inevitable parasitic Miller capaci-tance of the IGBT, overcharging the gate and conse-quently leading thus to a higher VGE and short-circuit current amplitude. In addition, the lower di/dt yields in less inductive coupling to the gate (usually named as counter-coupling), which further amplifies the ef-fect of higher VGE. This behavior can be seen even at SC tests with low DC-link voltage VDC (see Figure 6).

2.3. SC mode 2 (SC2)2.3.2. Test circuit and conditionsFigure 7 shows the SC2 test circuit. As defined in

section 2, in this SC mode the DUT conducts current IC before the short circuit event occurs. For a test, a normal IGBT turn off sequence will be started with a specific load current through Lload. Then, the high side auxiliary switch HS IGBT is turned on as fast that the di/dt is only limited by the circuit stray in-ductance Ls thus simulating a spontaneous fault. Usually for this, the high side gate drive (GDHS) volt-age VGon is increased (e.g. 20 V) and the RGon reduced. The resulting signal is shown in Figure 9.

—05 Test circuit SC mode 1.5

Ls

LSC < 10 µH

VGDHS = -15 V

HS IGBT

GDHS

CDC

Rs (x mΩ)

VCC > 0 V

RGon

VGDLS

RGoff

-VGoff

+

+VGon

-

GDLS

VCE

IC

LS IGBT

VGE

IG

S

1 2

VGon (typ +15 V)

VGoff (typ -15 V)

tSC ≈ 10 µs

VGDLS

t

-40

-30

-20

-10

0

10

20

0

1000

2000

3000

4000

5000

6000

0 5 10 15 20 25

Vg

e [V

]

Ice,

Vce

[A

, V]

t [µs]

Short circuit type 1.5 with different Ls: 0.15...4 µH

Ice

Vce

Vge

—06 Short circuit mode 1.5 test at elevating LSC

Ls

Lload >> 10 nH

HS IGBT

CDC

Rs (x mΩ)

VCC > 0 V

RG

on

VGDLS

RG

soft

-VGoff

+

+VGon

-

GDLS

VCE

LS IGBT

VGE

IG

S

1 2

IC > 0 A

RG

on <

<

VGDHS

RG

off

-VGoff

+

+VGon

-

GDHSS

1 2


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6

VGon (typ +15 V)

VGoff (typ -15 V)

tSC < 10 µs

VGDLS

t

VGon (>15 V)

VGoff (typ -15 V)

tonHS > 10 µs

VGDHS

t

—08 Timing SC mode 2

Comments:The DUT IGBT in this SC mode is already conducting current and the voltage VCE over the DUT is on the corresponding on-state level. When the desaturation or short-circuit current level is reached, VCE shows a positive slope (dv/dt) up to and even beyond the DC-link voltage level. The corresponding dv/dt is usually higher than in SC type 1.5 due to the very fast desat-uration speed. This positive voltage slope causes a high displacement current through the IGBT para-sitic Miller capacitance, charging the gate to a higher VGE and provoking short-circuit current. De-pending on the stray inductance, the di/dt is rather high (≈ Vdc / Ls) and thus leading to higher peak cur-rents too. In these cases, a protective di/dt-counter coupling circuit can help to limit the di/dt and peak current stress to the IGBT (see in section 6.2)

2.4. SC mode 32.4.2. Test circuit and conditionsFigure 10 shows the circuit for SC3 testing. As de-fined in Section 2, in this SC mode, the current IC in the DUT is < 0 and the diode is conducting free-wheeling current before the SC event occurs. When the current freewheels in a DUT-diode the high side auxiliary switch HS IGBT is turned on as fast as

the di/dt is only limited by the stray inductance Ls. For this, usually the gate voltage VGon from the GDHS is increased (e.g. 20 V) and the RGon reduced. The re-sulting signal is shown in Figure 11.The typical waveform of SC mode 3 can be seen in Figure 12. Since the parallel-connected IGBT is usu-ally turned on during diode freewheeling and the voltage VCE at the DUT is applied very fast, the cur-rent IF in the diode is commutating with a very high di/dt to the IGBT (see Figure 12). Unfortunately, this di/dt cannot be controlled actively and is just lim-ited through the low internal inductance between the diode and IGBT. This high di/dt leads to high-peak power at diode turn-off, depending on the ac-tual condition regarding current, voltage etc. the di-ode may fail even if the IGBT would be able to handle this SC event.Figure 14 shows an example for SC3, measured on a special made module where the current in the diode can be measured separately. Already at nominal test voltage, the maximum allowed peak power Pprec in the diode is exceeded and leads to a diode failure.

—09 Typical waveform SC mode 2

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—11 Timing SC mode 3

7

Ls

Lload >> 10 nH

HS IGBT

CDC

Rs (x mΩ)

VCC > 0 V

RG

on

VGDLS

RG

soft

-VGoff

+

+VGon

-

GDLS

VCE

LS IGBT

VGE

IG

S

1 2

IF > 0 A

RG

on <

<

VGDHS

RG

off

-VGoff

+

+VGon

-

GDHSS

1 2

IFIC VGon (typ +15 V)

VGoff (typ -15 V)

tSC < 10 µs

VGDLS

t

VGon (>15 V)

VGoff (typ -15 V)

tonHS > 10 µs

VGDHS

t

—12 Typical waveform SC mode 3

—13 Zoom of Figure 12

—14 Diode current and Pprec @ SC3

—15 Zoom Figure 14

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—16 Correlation ISC vs. pinch off voltage Vp

8

—17 Correlation ISC vs. VGE(TO)

3. Short circuit related IGBT characteristics The dynamic behaviour of an IGBT in SC mode 1 is dependent on the gate conditions as well as on the static characteristics of the IGBT:• VGE

• RGon

• CGE

• VGE(TO)

• VCEsat

• Vp (pinch off voltage)

An IGBT data sheet provides typical values. Usually the pinch-off voltage Vp is not given explicitly in a data sheet, but can be read out from the transfer characteristic (Figure 22). The following sections show, some typical correlations. The characteristics are more or less the same for all SC-modes. Results are shown for SC1 as an example.

3.1. The short circuit current ISC vs. Vp, VGE(TO) and VCEsat

The short circuit current ISC (as defined in section 2.1.3) correlates quite strongly with the pinch off voltage as well as to the gate emitter voltage VGE(TH)

(Figures 16 and 17). The influence of the IGBT on-state VCEsat is less but correlates to the SC current too. The high turn-on di/dt at SC event can be criti-cal too, this is shown by its correlation against the maximum SC current (ICM) as in Figure 19. Different di/dt can result from the variation of the pinch off voltage VP but can also be influenced by other pa-rameters like Ls.

3.2. SC1 vs. Tvj

The carrier mobility in the channel of the IGBT is higher at lower temperature. Hence the short circuit current is increased and highest at the minimum al-lowed junction operation temperature. In addition, the switching speed is also faster at lower tempera-ture. Therefore SC capability tests are usually done at the lowest specified operation temperature, e.g. -40 °C.Thermal capability tests at highest Tvj are performed by varying the conduction time duration tsc.During SC event, the junction temperature of the IGBT increases significantly (see section 5.4). Therefore, the desaturation current will decrease during the pulse duration depending on the tem-perature rise.

3.3. SC1 current vs. Vcc / LsThe SC mode 1 is defined by the condition that the total inductance in the circuit (Ls + LSC) is not limit-ing the diC/dt too much -> the short circuit current should reach its maximum within the first 25 % of the gate pulse width tSC [1].The positive dion/dt causes a voltage drop over the stray inductance Ls. If this voltage drop reaches the range of VCC, the dion/dt will be limited by Equation 1 (see also Figure 4):

�� ≈

�� + ��

Equation 1

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—18 Correlation ISC vs. VCEsat

9

—19 Correlation ICM vs. di/dt

If VCC is high enough, the short circuit current will rise with the time constant given by Equation 2 Equation 2 is accurate, as long as neither dv/dt nor di/dt influences the internal gate voltage on the IGBT.

Real measurements show, that parasitic elements like internal inductivities and capacities in the de-vice do affect the dynamic behavior (see section 4.4). Therefore, calculated results do not fit exactly with real measurements (Figure 21):

3.4. SC1 vs. VGE, RGon, CGE

The gate voltage VGE (nominal value 15 V) is having a direct influence on the SC current value ISC. The higher the voltage at the gate, the higher the SC current. This is represented in the data sheets by the output characteristic.RGon and CGE have mostly an influence on the switching speed (di/dt) and the SC peak current ICM. It is recommended to use the gate parameters listed in the IGBT modules data sheet. These driv-ing conditions are optimized regarding losses and SOA. Increasing RGon will slow down the turn-on speed of the IGBT and reduce the stress in an SC event. However, it will increase the switching losses at IGBT turn on. Lowering the RGon below, the data sheet value with unchanged Ls is not recom-

𝜏𝜏𝜏𝜏 = 𝑅𝑅𝑅𝑅𝐺𝐺𝐺𝐺 × (𝐶𝐶𝐶𝐶𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺 + 𝐶𝐶𝐶𝐶𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺)

𝜏𝜏𝜏𝜏 = (𝑅𝑅𝑅𝑅𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺 + 𝑅𝑅𝑅𝑅𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺) × (𝐶𝐶𝐶𝐶𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺 + 𝐶𝐶𝐶𝐶𝐺𝐺𝐺𝐺𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 + 𝐶𝐶𝐶𝐶𝑟𝑟𝑟𝑟𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖)

Equation 2

mended, as it will increase the stress during SC and at diode turn-off.

3.5. Externally applied and effective gate voltageAs the control interface for the IGBT chips Gate (G) and auxiliary Emitter (Ea) is not directly connected to the IGBT’s chips gate terminals. The parasitic ele-ments like inductances and capacitances do have significant influence on the dynamic behavior of the IGBT during short circuit. It does make sense to ex-tend the electrical model of the IGBT module ac-cording to Figure 23. For the dynamic behavior of the short circuit current, the internal gate voltage VGEint is mainly relevant. The IGBT model in Figure 23 shows the influence of diC/dt and dVCE/dt on the in-ternal gate voltage.• The positive diC/dt causes a voltage drop over Lse

and reduces the effective gate voltage g the IGBT turn on will be slowed down (negative feed-back).

• In the beginning of the short circuit transient, the negative dVCE/dt, caused by the stray inductance Ls (see Figure 2), induces a negative current in the reverse transfer capacitance Cres and reduces the gate voltage g the IGBT turn on will be slowed down again (negative feedback).

• After the voltage drop at Ls is stabilized and the dVCE/dt is changing to positive values, a positive current is flowing through Cres and increases the effective gate voltage gthe IGBT will be speeded up (positive feedback). Higher internal Vge ap-plied to chip increases the short circuit current value.

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—20 SC mode 1 vs. Tvj

10

—21 di/dt during SC mode 1 Turn on

The dynamic switching influences the feedback and it is also influenced by the feedback (closed loop), this makes it difficult to estimate the real switching behavior.

4. Critical/ limiting parametersAs long as ABB’s IGBT modules operate within the specification limits defined in the data sheet, they should be capable to withstand all SC types men-tioned above. Nevertheless, some main parameters/ conditions have a direct influence on the SC capabil-ity. Critical parameters for SC can be:• High gate voltage VGE

• High di/dt, peak current and peak power in the IGBT (low VCC, low RGon, short-circuit inductance LSC)

• High overvoltage during turning off a SC (high stray inductance, low RGoff)

• Thermal runaway (long SC pulse duration)

4.1. High gate voltageThe gate voltage should be kept at the IGBT modules terminals to nominal level, VGE = ± 15 V.Anyhow, the switching behavior depends on the gate voltage near the IGBT-cell of the IGBT chip. It is shown in section 3.5 that real voltage at the chip gate differs from the voltage at the module gate-terminal. ABB IGBT’s are capable to withstand short dynamic overvoltage, induced by coupling ef-

fects (section 3.5). For normal operation, it’s recom-mend limiting the voltage at the gate-terminal to 15 V. Exceeding this level may lead to SC-failures be-cause of the device overstressing.

4.2. High di/dt, peak current and peak powerThe higher the di/dt during turn on into a SC, the higher is the stress on the IGBT. Especially in case of SC 2 and SC 3, where the IGBT initially has no voltage across collector-emitter terminals, the di/dt and re-sulting peak power is even higher. Where it is possi-ble, a circuit for di/dt-counter coupling on every IGBT module should be applied (see section 5.2). This circuit helps to limit the di/dt during turn on into a SC and reduces the device stress.

4.3. High overvoltageOvervoltage across device higher than guaranteed in an IGBT’s datasheet may lead to breakdown of the IGBT module or reduce its lifetime. This has to be avoided in any operation stage. In applications with low voltage IGBT such as 1700 V-devices, the circuit stray inductance is high and cannot be reduced. To avoid exceeding nominal breakdown voltage and device damage, the overvoltage protection circuit may be used on every IGBT module. A simple design is shown in section 5.1.

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—22 Output characteristic 5SNA 1500E330305

11

—23 Internal and external gate voltage

4.4. High junction temperatureThe short circuit current amplitude ISC will be limited by the IGBT itself depending on the channel mobility in the IGBT. During SC event a lot of energy is de-posed into the IGBT and heats it up. With the as-sumption, that all energy is stored in the IGBT chip and no heat is dissipated during the short circuit (adiabatic process), the junction temperature can be calculated as follows:

As an example, the junction temperature for 5SNA 1500E330305 is calculated with following pa-rameters:

Equation 3

0

500

1000

1500

2000

2500

3000

0 1 2 3 4 5 6VCE [V]

I C [A

]

Tvj = 150 °C

17 V

15 V

13 V

11 V

9 V

19 V

C

E

G

Ea

RGint

Ca

LGint

Cres

Cies

Coes

Lse

Lspe

Lsc

Lspc

VGE

VCE

VGEint

IC, diC/dt

VLse ~ diC/dt

G’

C’ICres ~ dVC’G’/dt

𝑇𝑇𝑇𝑇𝑗𝑗𝑗𝑗′ = 𝑇𝑇𝑇𝑇𝑗𝑗𝑗𝑗 𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 +𝐸𝐸𝐸𝐸𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆1

𝑙𝑙𝑙𝑙 ∗ 𝑏𝑏𝑏𝑏 ∗ 𝛿𝛿𝛿𝛿𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 ∗ 𝑐𝑐𝑐𝑐𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 ∗ 𝑛𝑛𝑛𝑛𝑐𝑐𝑐𝑐ℎ𝑆𝑆𝑆𝑆𝑖𝑖𝑖𝑖

The picture 24 shows the calculated junction tem-perature for different IGBT modules after typical SC mode 1 tests.Typically, the lower voltage classes IGBT’s show higher junction temperatures than the higher volt-age classes IGBT’s. This is because the silicon vol-ume is almost linearly correlated to the nominal volt-age Vn, unlike the more or less constant “power density” Vn*In (Figure 25).Usually after a short circuit event, the IGBT has to block the full DC-link voltage over a specific time (depending on the application). If the junction tem-perature after short circuit is too high, the IGBT can lose its blocking capability, due to the thermal run-away. This can happen, if the heating power gener-ated through the leakage current in the IGBT is higher than the cooling power of the system [2]. Therefore, it is recommended to design a system properly regarding thermal aspects.

5. Protection circuitsThe ability to control the switching behaviour of IGBT’s is the precondition for gate protection circuit designs for overvoltage protection and di/dt counter coupling. In best case, this protection cir-cuits are used to avoid damages on semiconductors under certain operation conditions, like short circuit or IGBT turn off under SOA conditions.

l * b * tChip length * width *

thickness13.6 * 13.6 * 0.38 mm

dSi Density from silicon 2.33 g/cm3

cSiSpecific heat

capacity from silicon707 J/kg*K

nchip Number of IGBT chips 24 1

Tj startJunction start

temperature150 °C

ESC 2500V*6400A*10µs 160 J

Tj’Junction temperature

after short circuit208 °C

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—24 Junction temperatures after SC mode 1

12

—25 Voltage class dependency’s SC mode 1

They are not needed for steady state operation. Therefore, they should be designed and dimen-sioned in the way that they have no influence under normal operation conditions. Otherwise, e.g. switching losses could be increased and lead to a thermal overstress for the semiconductors.Nevertheless, the protection circuits have to work properly over the whole operation range regarding:• Voltage• Current• Temperature• Environment

5.1. Active clampingThe purpose of an overvoltage active clamping cir-cuit is to reduce and limit the overvoltage VCEM to a specific value (lower than the breakdown voltage of the device) in case of IGBT turn-off. The active clamping circuit affects the gate signal of the IGBT. Usually, the active clamping circuit supplies current into the gate during turn off and so pushes the IGBT back into an active state and slows down the switching speed.There are many different ways to implement active clamping circuits; here is one example. Designs for overvoltage protection (active clamping) utilizes the auxiliary collector contact (Ca) for the VCE- feedback. The voltage level and its slope are used as input to the IGBT control path (Gate). One such design is shown in Figure 26.If VCE exceeds the Zener-voltage of DAC, the gate will

be positive charged over RAC above threshold and so will slow down the turn-off speed of the IGBT and the overvoltage will be limited. Additional current will flow into the gate from the parallel capacitor CAC, proportional to dVCE/dt. This can help to reduce possible oscillations and have a smooth control by the active clamp. CAC has to be carefully designed as it worsens the short circuit capability when desatu-ration occurs. The capacitor acts in the case as in-creased Miller capacitance, hence the internal inter-nal gate voltage will be increased (see 4.1).It is not possible to design an active clamping circuit without considering the switching behavior of the particular IGBT over the whole operation range. Both, the active clamp and the IGBT are coupled in a close loop. At a short circuit, the overvoltage is usu-ally not as critical as at IGBT turn off during SOA conditions, assuming that short circuit is detected properly and that the gate drive will turn off the IGBT under soft gate conditions (RGsoft > RGoff).Comments:• The active clamp circuit has to be able to with-

stand the full collector-emitter-voltage under each operation condition and should be de-signed as reliable as the rest of the system.

• Breakthrough in an active clamp circuit will lead to serious damage of the whole converter.

• It is recommended to test the functionality of an active clamp circuit experimentally over the whole operation range of an application.

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—26 Overvoltage protection with active clamping

13

—27 di/dt counter coupling circuit

RAC

GDLS VGE

IG RG

VGDLS

C

E

G

Ca

Ea

CAC

DAC

IC

VCE

GDLS

VGE

IG RG

VGDLS

C

E

G

Ea

IC

ZGE

RGint

VLse ~ diC/dt x Lspe

Lspe

5.2. di/dt counter couplingTo increase the IGBT turn on immunity in SC mode, another protection circuit for counter coupling the di/dt at the gate can be applied. During short circuit type 2 or 3, the di/dt is very high as it is only limited by the total circuit stray inductance. High di/dt causes significant voltage drop across internal mod-ule stray inductance between main and auxiliary emitter (Figure 27). This voltage drags down the gate voltage via the Zener diodes and limits the peak short circuit current [5]. To avoid a permanent influence and decouple the gate from the power emitter, the protection circuit is clamped with a Zener diode ZGE in both directions. The threshold of the di/dt is controlled by the Zener-voltage level. Figure 27 shows a simple design.Following design rules are given as a starting point to setup a di/dt counter coupling circuit. It is recom-mended to verify the proper function experimen-tally. The calculated numbers are given as an exam-ple for the 5SNA 1500E330305 HiPak IGBT module:1. Calculate the maximum possible di/dt during

normal operation, e.g. (VN – VDCmax) / Ls, and add some margin e.g. 10..20 % gdi/dt = (3.3 kV – 2.5 kV) / 100 nH = 8 kA/µs gchosen di/dt value = 10 kA/µs.

2. Find out the stray inductance Lspe from the emit-ter terminalgdatasheetgmodule stray induc-tance gLspe = LsCE / 2 gLspe = 8 nH / 2 = 4 nH.

3. Calculate Zener-voltage ZGE ≤ di/dt x Lspe = 10 kA/µs x 4 nH = 40 V, reduce the value e.g.

10..20 % => VZ = 36 V.4. Test the circuit under fault conditions, e.g. with

an SC2 test.5. Verify the circuit within the normal operation

range of the IGBT module git should not have too much influence e.g. to switching losses.

6. The Zener diode should be placed as near as pos-sible to the gate / power terminal for excluding parasitic circuits.

Comments:• If the IGBT module is not providing an auxiliary

emitter terminal, this protection-circuit does not work. In this case, the di/dt has to be sensed in another way.

• If the influence from the di/dt feedback loop is too strong/ fast, an additional resistor in series to the Zener diode can be used to limit the im-pact.

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14

6. Production outgoing inspection tests by ABBThe test circuit in the figure above is typically used for all production dynamic testing. These tests are performed in phase leg configuration, including SC testing (SC mode 1). Usually the low side IGBT or di-ode is defined as DUT.

7. Appendix7.1. List of figuresFigure 1: 3-phase voltage source converter 3Figure 2: Test circuit SC mode 1 3Figure 3 Typical short circuit mode 1 curves and ref-erences for parameter calculating 4Figure 4: Short circuit mode 1 test at elevating col-lector-emitter voltage 4Figure 5: Test circuit SC mode 1.5 5Figure 6 Short circuit mode 1.5 test at elevating stray inductance 5Figure 7: Test circuit SC mode 2 5Figure 8: Timing SC mode 2 6Figure 9: Typical waveform SC mode 2 6Figure 10: Test circuit SC mode 3 7Figure 11: Timing SC mode 3 7Figure 12: Typical waveform SC mode 3 7Figure 13: Zoom of Figure 12 7Figure 14: Diode current and Pprec @ SC3 7Figure 15: Zoom Figure 14 7Figure 16: Correlation ISC vs. pinch off voltage Vp 8Figure 17: Correlation ISC vs. VGE(TO) 8Figure 18: Correlation ISC vs. VCEsat 9Figure 19: Correlation ICM vs. di/dt 9Figure 20: SC mode 1 vs. Tvj 10Figure 21: di/dt during SC mode 1 turn on 10Figure 22: di/dt during SC mode 1 turn on 11

—28 Single-phase leg for dynamic testing

Ls

CLload

S1

S2

S3

Rs

S4

Vcc

DUT

Aux

Figure 23 Output characteristic 5SNA 1500E330305 11Figure 24: Internal and external gate voltage 12Figure 25: Junction temperatures after SC mode 1 12Figure 26 Voltage class dependency’s SC mode 1 13Figure 27: di/dt counter coupling circuit 13Figure 28: Single-phase leg for dynamic testing 14

7.2. Acronyms

di/dt Current slope

dv/dt Voltage slope

DUT Device Under Test

SCSOA Short-Circuit-Save-Operating-Area

IGBT Isolated-Gate-Bipolar-Transistor

LS1...3 Low Side 1...3

HS1...3 High Side 1...3

Tvj Virtual junction temperature

CDC DC-link capacitor

VDC DC-link voltage

VCE Collector-Emitter-Voltage

VCEM Collector-Emitter-Voltage-Maximum

IC Collector-Current

VGE Gate-Emitter-Voltage

IG Gate-Current

IF Diode-Forward-Current

LSC Short-Circuit-Inductance

Ls (Ls)Stray-Inductance (Commutation-Inductance)

Rs

Series Resistor (limiting failure peak current)

GDHS/ GDLSGate-Drive-High-Side/ Gate-Drive-Low-Side

SSCM Self-Clamping-Switching-Mode

C Main collector contact

E Main emitter contact

G Gate contact

Ca Auxiliary collector contact

Ea Auxiliary emitter contact

RG Gate-Resistor

RGint Internal Gate-Resistor from the IGBT

CGE Gate-Emitter-Capacitance

CGC Gate-Collector-Capacitance

CCE Collector-Emitter-Capacitance

Cies Input capacitance

Coes Output capacitance

Cres Reverse capacitance

RGDS Nominal Gate-Resistor from data sheet

CGEDS

Nominal Gate-Emitter-Capacitor from data sheet

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15

Version Change Authors

01 initial release A. BaschnagelE. Tsyplakov

7.3. Bibliography[1] International Standard IEC, “Semiconductor de-

vices – Discrete devices – Part 9: Insulated-gate bipolar transistors (IGBTs)”, IEC 60747-9.

[2] ABB, “Thermal runaway during blocking”, Appli-cation Note 5SYA 2045-01.

[3] ABB, “Surge currents for IGBT Diodes”, Applica-tion Note 5SYA 2058-02.

[4] Stefan Linder, “Power Semiconductors”, EPFL Press, ISBN 2-940222-09-6

[5] Steffen Pierstorf, Different Short Circuit Types of IGBT Voltage Source Inverters , PCIM Europe 2011, 17 – 19 May 2011, Nuremberg, Germany

[6] Arnost Kopta, “Short-Circuit Ruggedness of High-Voltage IGBTs”, Shaker Verlag GmbH, ISBN 978-3-8322-9383-3

[7] Josef Lutz, Ralf Döbler, Short Circuit III in High Power IGBTs

8. Revision

Documents

IGBT short circuit safe operating area (SOA) capability and testing · 2019-03-08 · Gate signal pulse-width L s Stray inductance from DC-link L SC Short circuit load inductance