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IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY 1

Development of Package-on-Package UsingEmbedded Wafer-Level Package Approach

Ser Choong Chong, David Ho Soon Wee, Vempati Srinivasa Rao, and Nagendra Sekhar Vasarla

Abstract— The ever-increasing demands of higher perfor-mance, multiple functions, higher density, and lower cost man-date the reduction of the I/O pitch on the die as well as on thepackage. Pitch specifications of current substrate technologiesdo not match the stringent fine-pitch I/O requirements. Combin-ing embedded wafer-level package (EMWLP) and package-on-package (PoP) technologies yields a preferred solution providingfan-out area to route the fine-pitch I/Os of the chip to large-pitchI/Os on to the extra area of fan-out EMWLP packages and allowsthe use of conventional substrate technology. However, there aremany challenges to realizing the PoP of EMWLP packages. Theyinclude the die shift during the reconstruction process, double-sided reroute distribution line (RDL), and through-mold via(TMV) connections on a thin bottom package. The assembly ofEMWLP and PoP, thermal management of PoP packages, andtheir reliability are also major concerns. This paper describesthe development of an EMWLP PoP of 12 mm × 12 mmfootprint with 432 I/Os and the adoption of TMV to enablePoP connections. The top package circuitry is accessed throughTMVs in the bottom package with double-sided RDL. Solid TMVand side-wall-plated TMV are demonstrated in the EMWLP.Mechanical modeling of the PoP is conducted to optimize thestructures of the packages for good reliability performance of thePoP. Thermal dissipation of the PoP is another area of concern,because the thermal path of the top package is limited in mobileapplications. The thermal performance of the developed PoP wasanalyzed by thermal modeling and was successfully validated bythermal characterization of the PoP module. The developed PoPsuccessfully passed the JEDEC standard reliability tests such asmoisture sensitivity level 3 test; the unbiased highly acceleratedstress test for 96 h, 500 air-to-air thermal cycling (–40 °C to125 °C), and 30 drop tests.

Index Terms— Embedded wafer-level package (EMWLP),finite element analysis, package on package (Pop), solder jointreliability, thermal analysis, through-mold via (TMV).

Manuscript received January 14, 2013; revised April 4, 2013 and May 16,2013; accepted July 9, 2013. This work was supported in part by theElectronics Packaging Research Consortium led by the Institute of Micro-electronics, the research institute of the Agency for Science, Technology andResearch, whose members include Infineon Technologies Asia Pacific PteLtd., Ibiden Singapore Pte Ltd., NXP Semiconductors, Asahi Glass Co. Ltd.,Aurigin Technology Pte Ltd., Kinergy Ltd., Compass Technology Co Ltd.,and Unimicron Technology Corporation. Recommended for publication byAssociate Editor S. Mahalingam upon evaluation of reviewers’ comments.

S. C. Chong and V. S. Rao are with FAB-PAT, Institute of Microelec-tronics, 117685 Singapore (e-mail: [email protected]; [email protected]).

D. H. S. Wee is with IPP, Institute of Microelectronics, 54000 Singapore(e-mail: [email protected]).

N. S. Vasarla is with FAB, Institute of Microelectronics, 117685 Singapore(e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2013.2275009

I. INTRODUCTION

THE consumer market demands for increasing miniatur-ization, higher performance, greater multifunctionality,

and lower costs continue to drive contemporary consumerelectronic package designs. In addition, the shrinkage of thebond pad pitch and pad sizes on the IC chip is more aggressivethan the shrinkage at the substrate level, leading to a wider“interconnect gap” between the chip’s pad pitch and substrate’spad pitch. To address these issues, the fan-out embeddedwafer-level package (EMWLP) was developed. This packageoffers additional space for high-density routing, easing thedemand on the substrate’s pitch [1]–[5]. The introduction ofpackage-on-package (PoP) stacking with through-mold vias(TMVs) has further encouraged the adoption of the EMWLPapproach in consumer markets [6].

The next-generation EMWLP PoP packages involve double-sided reroute distribution lines (RDLs) with vertical intercon-nection in the bottom EMWLP package with 0.5-mm thicknessand at least 12 mm × 12 mm size [7]. Vertical interconnectionsallow the integration of heterogeneous packages with differentfunctionalities. In earlier days, PoPs required wire bonding forintra-PoP connections. However, recently, PoP technologiessuch as bare-die PoP, embedded solder on pad, and laser-via PoP have emerged in the packaging industry to meetconsumer demands in terms of the package form factor [8].The development of laser-via PoP allows the TMV to beincorporated into EMWLP, which in turn aids in the 3-Dintegration of various packages into one single unit [9].

The thermal performance of PoP needs to be consideredseriously, as PoP modules target mobile application and thereis limited space to implement cooling solutions. Single pack-ages offer better thermal path than PoPs [10]. The top packagein aPoP without heat sinks suffers from poor thermal perfor-mance because the thermal path for top package is limitedwhen compared to that of the bottom package. The higherthermal conductivity of the substrate used in EMWLP actsas a heat spreader and lowers the overall thermal resistanceof the package, resulting in lower junction temperature of thePoP [11], [12].

In this paper, we present an EMWLP PoP package of12 mm × 12 mm × 0.8 mm with 432 I/Os using TMVs asvertical interconnection. Both the top and bottom EMWLPpackages are of 12 mm × 12 mm × 0.2 mm size. PoPpackages using the ultrathin EMWLP approach encounterseveral challenges. The major challenges are related to die shiftduring the reconstruction process [13], performance reliability,

2156-3950 © 2013 IEEE


2 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY

Fig. 1. PoP structure.

TABLE I

POP SPECIFICATIONS

thermal performance of the PoP, and the integration of TMVand double-sided RDL layer fabrication on the thin moldedwafer because of the expected high warpage of the wafer.

The key developments in mechanical modeling, thermalsimulations, TMVs, the double-sided RDL process, and PoPassembly are discussed in detailed in this paper. The developedPoP using the EMWLP approach is analyzed for its reliabilityperformance using moisture sensitivity level 3 (MSL3) test,unbiased highly accelerated stress testing for 96 h (HAST),500 air-to-air thermal cycling (–40 °C to 125 °C), and 30dropt tests. The thermal performance of the EMWLP PoP ischaracterized experimentally, and the results match well withthe simulation results.

II. PACKAGE DESCRIPTION

The PoP structure and the PoP specifications are shown inFig. 1 and Table I, respectively. The bottom package withTMVs has a solder pitch of 0.4 mm. It has 432 pads and88 TMVs. The schematics of the daisy chains to monitorthe solder interconnects between the top package and theprinted circuit board (PCB) through the TMV incorporatingsolder interconnects between the bottom package and thePCB are shown in Fig. 2(a) and (b). The top package hasthe same size as the bottom package but with the solderpitch of 0.5 mm. The silicon die of 7 mm × 7 mm size isembedded inside the top package, whereas the silicon die of8 mm × 8 mm size is embedded inside the bottom package.The top package has 168 solder balls, as shown in Fig. 2(c)and (d). The substrate is made of FR4 with 1-mm thickness.The substrate’s pad is solder-mask-defined with a diameter

Fig. 2. Package layout. (a) Schematic diagram of bottom package. (b) Padlayout of bottom package. (c) Schematic diagram of top package. (d) Padlayout of top package.

Fig. 3. Finite element model of PoP.

TABLE II

MATERIAL PROPERTIES USED IN THERMOMECHANICAL MODELING

of 200 µm, and pad finish is electroless nickel immersiongold (eNiAu).

III. THERMOMECHANICAL MODELING

Thermomechanical modeling of the PoP was carried outusing finite element analysis to optimize the structure in orderto achieve minimum stress in the package. Fig. 3 illustratesthe model implementation of the PoP. The material propertiesused in the modeling are given in Table II. The solder jointpitch for the top package is 500 µm, while the solder pitchfor the bottom package is 400 µm. Two-dimensional planestrain analysis is performed on the diagonal cross-sectionof the package. The temperature of the package is assumedto be constant, and perfect adhesion is assumed betweenall material interfaces. The materials are modeled as elastic


CHONG et al.: DEVELOPMENT OF PoP USING EMBEDDED WAFER-LEVEL PACKAGE APPROACH 3

Fig. 4. Maximum peel stress location on PoP.

Fig. 5. Peel stress as a function of the UBM diameter on the top and bottompackages.

materials except for copper which is considered to obey theelastic–plastic material behavior. The SnAgCu solder bumpsare modeled according to Anand’s model with the inclusionof viscous–plastic properties [14]. The thermal loading wasfrom 260 °C to 25 °C with one load step for stress analysis.The stress analysis was conducted on the PoP structures tooptimize the diameter of the under bump metallurgy (UBM)on the top and bottom packages with respect to the maximumpeel stress experienced by the PoP structures. The diameterof the UBM on the top package used in the modeling is 250,300, or 350 µm. For the bottom package, the UBM diameterof 150, 180, or 200 µm is considered.

The result of the thermomechanical modeling indicate thatthe maximum peel stress occurs at the solder joint near thePCB pad, as shown in Fig. 4. The location of the maximumpeel stress occurs near the silicon/mold compound interface.This location experienced maximum local coefficient of ther-mal expansion (CTE) mismatch as compared to other loca-tions, and therefore a high stress level is expected here. Thepeel stress encountered by the PoP may have been caused byan earlier failure during the reliability assessment. Therefore,the PoP with 250-µm UBM diameter on the top package and200-µm UBM diameter on the bottom package was chosen,as it demonstrates the lowest peel stress, as shown in Fig. 5.The UBM diameter of the bottom package influences thestress level of the PoP more than the UBM diameter ofthe top package because the CTE mismatch between thebottom package and substrate is much higher than that betweenthe top and the bottom package. The optimized structure ofPoP experiences the lowest peel stress, which means betterreliability performance.

IV. THERMAL SIMULATION OF POP

The PoP is designated in mobile applications where thespace available for thermal dissipation is limited as compared

TABLE III

MATERIAL PROPERTIES USED IN THERMAL SIMULATION

Fig. 6. Temperatures of the PoP structure at a power dissipation of 0.5 Wper package.

to desktop application. The PoP structure also poses a thermalchallenge in heat dissipation from the top package to thePCB because heat from the top package needs to route eitherthrough the bottom package or through the air above thepackage. To analyze these effects, detailed thermal simulationswere carried out. Effects of varying the TMV sizes anddistribution, solder pad layout, the introduction of underfillmaterial, and heat spreader on the reduction of thermal loadingof PoP were analyzed. The simulation results were validatedusing the thermal measurements on the PoP, and suitablethermal solutions for PoPs in mobile application are identified.

The computational fluid dynamics software toolFLOTHERM fth8.2 was used to perform the thermalsimulation. A JEDEC 51-2-compliant natural convectionmodel (at the ambient temperature of 25 °C) was set upfor package-level modeling of the PoP design. The thermalsimulations were aimed at investigating the impact of TMVs,solid and side-wall-plated TMVs, solder joint layout for thebottom package, and thermal impact of the underfill material.The material properties used in the thermal simulation arelisted in Table III.

A. Effect of TMV

The thermal simulation results on PoP without TMV andboth top and bottom package powered at 0.5 W indicate thatthe top package’s temperature is 29% higher than that of thebottom package (Fig. 6). Thus, the critical thermal element ofthe PoP is the top package’s heat path.

One of the unique features of the PoP design is the useof TMVs in the bottom package as electrical feed throughconnections from the top package to the board. TMVs mayalso offer a thermal path through which the heat from toppackage can flow to the bottom package and down to thePCB. To understand the TMVs’ effectiveness in routing heat,the package was modeled with TMV diameters varying from0.2 to 0.3 mm and the pitch set at 0.4 mm. The TMV wasmodeled as filled with solid copper with a thermal conductivityof 390 W/mK. Effect of the side-wall-plated TMV with a



Fig. 7. Effect of TMV on junction temperatures.

Fig. 8. Effect of TMV material thermal conductivity on junctiontemperatures.

Fig. 9. Parametric results showing PoP temperature gradient as the solderball configuration increases in density.

different thermal conductivity from that of the fill material wasalso analyzed. TMV configurations ranging from two rows(184 TMVs) to three rows (276 TMVs) were tested in thethermal model. The thermal simulation results indicate thatthere is negligible effect on thermal performance for differentTMV configurations (Fig. 7). There is also negligible thermalperformance difference between solid-copper TMV and side-wall-plated TMV, as shown in Fig. 8.

B. Effect of Solder Array on Bottom Package

In order to improve the cooling of the bottom package,a comparison of the initial model’s depopulated peripherybottom solder array with a full array design was conducted.The results show better thermal performance for the full-arraybottom solder layout, as both the top and bottom packageregistered lower temperatures (Fig. 9).

Fig. 10. Effect of adding underfill in between the EMWLP packages, orbelow bottom package only, on the package junction temperature.

Fig. 11. Effect of heat spreader on chip’s temperature.

C. Effect of Underfill

The effect of underfill on the thermal performance of thePoP was studied by assuming perfect contact between bothpackages powered at 0.5 W. The underfill material equalizesthe two packages’ temperatures, as shown in Fig. 10. Theunderfill material between the top and bottom packages andbetween the bottom package and the substrate enables the toppackage to be cooled down by 37%, while adding underfill tothe bottom package alone yields only 2% cooling. The additionof underfill material removes the thermal bottleneck betweenthe two packages.

D. Effect of Heat Spreader

The effect of a heat spreader on the thermal performancewas studied by varying the power of the PoP from 1 to 3.5 W.The heat spreader mounted on the top package is instrumentalin removing the heat to the surrounding environment andenables a maximum 3-W total PoP power while maintainingthe chip temperature below 85 °C, as shown in Fig. 11.

V. FABRICATION OF EMWLP WITH TMV

TMVs are needed for the PoP structure, as the externalsignal/control needs to access the top package through theTMVs in the bottom package. The TMVs in the EMWLPare fabricated either by solid Cu or using the side-wall-plated approach. The subsequent sections illustrate the twoapproaches of TMV fabrication on EMWLP.



Fig. 12. Process flow for EMWLP with Cu-pillar TMV. (a) Stacking ofAl daisy-chain chips onto sacrificial Si chips with DAF. (b) Pick-and-placeof chip stacks onto molding tape on molding carrier. (c) Mold compoundencapsulation to form the reconstructed wafer. (d) Thinning of both sides ofreconstructed wafer to remove sacrificial chips and DAF and to expose Cu-pillar TMVs. (e) Bonding of thinned reconstructed wafer to Si carrier usingtemporary bonding adhesive. (f) Front-side Cu RDL process on reconstructedwafer. (g) Debonding of reconstructed wafer from Si carrier and rebondingthe front side to Si carrier. (h) Backside Cu RDL process on the reconstructedwafer. (i) Debonding the reconstructed wafer from the Si carrier followed byENiG process to form UBM.

A. Fabrication of EMWLP With Solid Copper TMV

The process flow of an EMWLP with Cu-pillar TMVsis illustrated in Fig. 12. Aluminum (Al) daisy-chain chipsare fabricated using SiO2-passivated wafer. Al metallizationis first carried out on the wafers. Photolithography and wetetching are used to pattern the Al daisy-chain structures.A layer of 1-µm-thick SiO2 passivation is deposited usingplasma-enhanced chemical vapor deposition, followed by pho-tolithography and dry etching to form via openings on the Aldaisy-chain structures. A 100-nm Ti/ 200-nm Cu seed layeris then sputtered for Cu electroplating. A layer of 100-µm-thick dry-film photoresist is laminated and patterned usingphotolithography for electroplated Cu pillar interconnects. Cupillars of 75 µm height are electroplated on the aluminumdaisy-chain wafer, followed by photoresist stripping and wetetching of the seed layer. The Al daisy-chain wafer with cop-per pillars is subsequently thinned down to 150-µm thicknessand a dicing die-attach film is laminated on the backside priorto singulation.

Cu pillars are fabricated on a sacrificial Si wafer using asimilar process as for the Al daisy-chain wafer. A 100-nmTi/200-nm Cu seed layer is sputtered on the sacrificial waferand a 200-µm-thick dry-film photoresist is laminated onto thewafer. After patterning the photoresist, 220-µm-high Cu pillarsare electroplated onto the wafer. The photoresist is stripped andthe seed layer is removed. The sacrificial wafers are thinnedto 300-µm thickness and then singulated.

The singulated Al daisy-chain chips are attached to thesacrificial chips using the DAF. The two chip stacks are

Fig. 13. EMWLP wafer with solid Cu TMV.

then picked and placed on the molding tape laminated ona molding carrier. The reconstructed wafer is sent for moldcompound encapsulation to form the reconstructed wafer.The reconstructed wafer is thinned down on both sides tocompletely remove the sacrificial chips to expose the Cu pillarto form the solid TMV in the wafer. The final thickness ofreconstructed wafer with the solid Cu TMV is 200 µm.

In order to handle the thin 200-µm reconstructed waferduring the RDL process, the reconstructed wafer is bondedto a 725-µm-thick silicon carrier using a temporary bondingadhesive (HT-10.10 from Brewer Science) in an EVG waferbonder. The thick silicon carrier wafer reduces the warpageof the thin reconstructed wafer, allowing subsequent RDLprocessing [15]. The photodielectric material is spin-coated,patterned, and hard-cured at 200 °C for 1 h to form a5-µm-thick dielectric passivation layer on the reconstructedwafer. A 100-nm Ti/200-nm Cu seed layer is sputtered onto thereconstructed wafer. Photoresist is spin-coated and patternedfor Cu electroplating to form the redistribution interconnec-tion. The photoresist is stripped after Cu electroplating, and theseed layer removed. A 3-µm-thick Cu RDL is electroplated.A 5-µm-thick photodielectric passivation layer is formed onthe Cu RDL to complete the front-side RDL process.

The reconstructed wafer with front-side RDL is debondedfrom the Si carrier by thermo sliding at 180 °C in an EVGdebonder. The reconstructed wafer is then rebonded to the Sicarriers for the backside RDL process. The completed frontand backside RDL wafer is debonded to form the EMWLPwafer with solid Cu TMVs (Fig. 13).

B. Fabrication of EMWLP Wafer With Side-Wall-Plated TMVs

The fabrication process for EMWLP with side-wall-platedCu TMVs is illustrated in Fig. 14 [16]. A layer of 5-µm-thickphotodielectric is spin-coated, patterned on the reconstructedwafer, and hard-cured to form the first passivation layer withphoto via opening on Al metallization pads. Cu UBMs aredeposited on top of the Al pads to protect the Al metallizationfrom the electroless Cu plating chemistry. The reconstructedwafer is thinned down to 200 µm, and a 5-µm blanketphotodielectric passivation layer is deposited on the backsideof the wafer. A laser ablation machine is used to ablate throughholes in the reconstructed wafer. An electroless Cu seed layeris deposited onto the reconstructed wafer by immersing the



Fig. 14. Process flow of EMWLP with sidewall Cu TMV. (a) Front sidepassivation. (b) Cu UBM on Al pad. (c) Wafer backside thinning. (d) Blanketbackside passivation. (e) Laser ablation to form through hole. (f) ElectrolessCu seed deposition. (g) Dry-film photoresist lamination and patterning on bothsides. (h) Cu electroplating, followed by photoresist stripping and seed layeretching. (i) Permanent dry-film photoresist lamination on both sides with viaplugging.

Fig. 15. EMWLP wafer with side-wall-plated TMV.

wafer in a series of chemical baths. A dry-film photoresistis laminated and patterned on both sides of the reconstructedwafer. Electroplating is done to form the redistribution Cutraces connecting the through holes and Cu UBMs. The dry-film photoresist is stripped away and the Cu seed layer etchedaway, leaving a 10-µm-thick Cu RDL connecting the plated-through hole to the Al pads. Permanent dry-film photoresistis then vacuum-laminated on both sides using a wafer bonderto form the final passivation, with the permanent photoresistfilling in the through holes to form via-plugs. Openings arethen developed on the final passivation layer on the thinmolded wafer to expose the pads for solder balls. The EMWLPwafer with side-wall-plated TMVs is completed, and is readyfor subsequent dicing, ball mounting, and board attachment(Fig. 15).

VI. ASSEMBLY PROCESS OF POP

PoP assembly needs to ensure good solder interconnectsbetween the top and bottom packages and also between thebottom package and the underlying PCB. The warpage of thepackage is likely to impact the yield of PoP assembly, as thesolder joint may not form properly between the packages andalso between the package and substrate [17]. The poor yieldof PoP is attributed to the different warpage directions of thetop and bottom packages. The yield is further impacted by thesmall solder ball diameter. However, the warpage of EMWLP

Fig. 16. Assembly process of PoP.

Fig. 17. Cross-section of PoP.

Fig. 18. Warpage measurement on top and bottom package before the reflowprocess.

is reported to be fairly constant as compared to the ball gridarray package used in PoP during the reflow process [7].

The PoP assembly is carried out with 1× reflow processto minimize multiple reflow exposures to the bottom package,as illustrated in Fig. 16. Fig. 17 depicts good solder jointsbetween the packages and between the package and PCB.Warpages of both the top and bottom package are character-ized before the attachment process and after the reflow process.As shown in Fig. 18, the warpage of the top package andbottom packages was 4.5 and 20 µm, respectively, before thereflow process. The warpage results are given in Table IV.The PoP is attached successfully on the PCB with eNiAupad finish.

Underfilling of PoP is a challenge because there are twolocations where the underfill material needs to fill: the area



TABLE IV

WARPAGE RESULT FOR POP

No Package Before Attachment After Reflow Process

1 Bottom Package 20µm (Sad Face) 20µm (Smiling Face)

2 Top Package 4.5µm (Sad Face) 35µm (Sad Face)

Fig. 19. CSAM image of PoP.

Fig. 20. Cross-sectional image showing the filler of the underfill material.

Fig. 21. Thermal experimental characterization setup.

between the two packages, and area between package andsubstrate. In this paper, a one-step process is adopted to fillthese two areas simultaneously. The underfill is dispensedalong one edge of the PoP, with the substrate maintainedat 90 °C. The elevated temperature lowers the viscosity ofthe underfill material and promotes material filling inside PoP.Confocal scanning acoustic microscopy (CSAM) and through-scan analysis indicate that the PoP has no visible void in theunderfill area. Fig. 19 shows the CSAM image of the PoP,indicating no void between the packages. The fillet shape ofthe underfill material at the edge of POP is shown in Fig. 20.The developed PoP assembly process is then subjected tothermal characterization and reliability assessments.

VII. THERMAL CHARACTERIZATION OF POP

Experimental characterization of the package’s thermalresistance is performed for the validation of the theoreticalmodels with assembled PoP modules adhering to the JEDECJESD-51 thermal test standards. Junction temperatures anddie power are measured using commercial thermal test dies

Fig. 22. Experimental temperature measurements with variation in powerconfiguration.

Fig. 23. Experimental model validation as the difference between measure-ment and simulated temperatures as the package configuration varies.

(DELPHI PST3) in the package. The experimental setup isshown in Fig. 21.

The dies’ temperature-sensitive parameter is calibratedto obtain its K -factor constant, with the averageK -factor for the device of 104.7 °C/V (1). The standarddeviation of sample set is less than 3% of average, andthus the average K -factor can be used to represent each testsample

Kaverage =∣∣∣∣

(THi − TLo)

(VHi − VLo)

∣∣∣∣= 104.7 ± 0.5

◦C

V. (1)

In different power configurations, the top package sam-ples had a higher temperature variation of less than 9% ascompared to less than 4% for the bottom package samples(Fig. 22). The simulation results vary, on average, by lessthan 10% from the experimental results, as shown in Figs. 23and 24. For the bottom package, the deviation generally rangesfrom 0.98% to 9.4% of the experimental average. For the toppackage, the deviation ranges from 1.22% to 8.16% of theexperimental average. Thus, the theoretical model has beenvalidated with the experimental results. For the nonunderfilledPoP modules, the 125 °C extreme temperature limit can bemet, under baseline conditions, at a maximum total PoP powerdissipation of 1 W. Because of its ability to remain under themaximum junction temperature limit at sustained processingand memory power levels, the EMWLP PoP is thermallysuitable for power-efficient mobile applications.



Fig. 24. Experimental model validation as the percent difference betweenmeasurement and simulated temperatures.

TABLE V

RELIABILITY RESULTS FOR EMWLP PACKAGE

TABLE VI

RELIABILITY TEST CONDITIONS FOR POP

VIII. RELIABILITY TESTING OF POP

The individual EMWLP package was subjected to MSL3with Pb-free reflow profile, unbiased HAST, and thermalcycling [15]. No failure was observed in these tests (Table V).The assembled PoP was subjected to drop tests and theboard-level thermal cycling test (TCOB). The reliability testconditions were as per JEDEC standards, and the details aregiven in Table VI. The integrity of the PoP was assessed bydaisy-chain electrical measurement for both top and bottompackages. Failure analysis was carried out by cross-sectioningthe failed sample.

A total of 12 samples were subjected to both TCOB anddrop tests. No failure was detected for both tests. Cross-sections done on the passed sample revealed intact solder jointand good integrity of TMV (Fig. 25). The developed PoP hasdemonstrated its reliability performance and meets all JEDECrequirements.

Fig. 25. Good solder joint and TMVs of EMWLP package.

IX. CONCLUSION

The effects of UBM diameter, TMV structures, solderlayouts, and underfill material of a 12 mm × 12 mm × 1.2 mmPoP using the EMWLP approach were investigated forimproving the assembly as well as thermal and reliabilityperformance of an organic substrate. A summary of theimportant results and recommendations is as follows.

1) The UBM diameter of bottom package impacts the stresslevel experienced by the PoP structures.

2) TMV in the EMWLP can be realized either by solidcopper or by the side-wall-plated process. TMV con-figuration has negligible impact on the package-levelthermal performance.

3) The thermal performance of PoP can be enhanced byhaving a full solder array for the bottom package as wellas by the use of underfill material between the packagesand between the bottom package and the PCB.

4) A maximum total power of the PoP of 3 W is possiblewith the introduction of a heat spreader mounted on thetop package.

5) The assembly of the PoP is accomplished by stackingboth the top and bottom packages on the PCB andsubjecting it to a 1× reflow process.

6) The developed PoP passed both the board-level drop testand the temperature cycling test.

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[15] H. J. Kim, S. C. Chong, D. S. W. Ho, E. W. Y. Yong, C. H. Khong,C. W. L. Teo, D. M. Fernandez, G. K. Lau, N. S. Vasarla, V. W. S. Lee,S. R. Vempati, and K. O. K. Navas, “Process and reliability assessmentof 200 µm-thin embedded wafer level packages (EMWLPs),” in Proc.ECTC, Jun. 2011, pp. 78–83.

[16] S. W. Ho, F. M. Daniel, L. Y. Siow, W. H. SeeToh, W. S. Lee,S. C. Chong, and V. S. Rao, “Double side redistribution layer processon embedded wafer level package for package on package (POP)applications,” in Proc. 12th EPTC, Dec. 2010, pp. 383–387.

[17] N. Vijayaragavan, F. Carson, and A. Mistry, “Package on packagewarpage—Impact on surface mount yields and board level reliability,”in Proc. 58th ECTC, May 2008, pp. 389–396.

Ser Choong Chong received the bachelor’s degreefrom the Department of Mechanical Engineering,Nanyang Technology University, Singapore, in 2001,and the Master Engineering degree from the Depart-ment of Material Science, Nanyang Technology Uni-versity, in 2008.

He has authored or co-authored more than 50journal and conference publications on electronicpackaging. He is a Senior Research Engineer withthe Packaging and Assembly Technology Depart-ment, Institute of Micro-Electronics, Singapore. His

current research interests include flip-chip packaging, lead-free assemblyprocesses, 3-D chip stacking packaging, and chip to wafer bonding process.

David Ho Soon Wee received the bachelor’s degreefrom the Department of Material Science, NanyangTechnology University, Singapore in 2005. He isworking as a Senior Research Engineer with theThrough Silicon Via Department, Institute of Micro-electronics, Singapore. His current research interestsinclude wafer fabrication in the area of embeddedwafer level package, TSV, and TSI devices.

Vempati Srinivasa Rao received the B.Tech. degreein metallurgical engineering from the National Insti-tute of Technology (earlier Regional EngineeringCollege), Warangal, India, in 2002, and the M.Eng.degree in mechanical engineering from the NationalUniversity of Singapore, Singapore, in 2005.

He is currently a Manager with the Packagingand Assembly Technologies Laboratory, Institute ofMicroelectronics (IME), Singapore. Prior to joiningIME in 2006, he was a Research Engineer withthe Nano Wafer-Level Packaging Group, National

University of Singapore. He has authored or co-authored more than 50 journaland conference publications on microelectronic materials and electronicpackaging. His current research interests include wafer level packaging, fan-out wafer level packaging, fine pitch micro bump interconnects, Cu/low-kpackaging, through silicon via technology, 3-D stacked module, chip-to-waferbonding, thin wafer handling, wafer level backend process integration, andpackage reliability.

Nagendra Sekhar Vasarla received the bachelor’sdegree in metallurgy from the National Instituteof Technology, Warangal, India, and the master’sdegree in material science from the National Uni-versity of Singapore, Singapore, in 2006.

He is currently with the Institute of Microelec-tronics, A*STAR, Singapore, and actively involvedin microelectromechanical systems (MEMS) proto-typing and microelectronic product development. Hehas published more than 50 journal and conferencepublications and one book chapter. He regularly

publishes work in IEEE journals and conferences. His current researchinterests include MEMS wafer level packaging technologies, 3-D-throughsilicon via advanced wafer level packaging, wafer level bonding, thin waferhandling technologies, and reliability and failures analysis.

Dr. Vasarla is listed in Who’s Who in the World.

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