IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR … · 2013-12-17 · IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 2, FEBRUARY 2012 255 The Design

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 2, FEBRUARY 2012 255

The Design of an Operational AmplifierUsing Silicon Carbide JFETs

Ayden Maralani, Member, IEEE, and Michael S. Mazzola, Member, IEEE

Abstract—Superior performance of the Silicon Carbide (SiC)semiconductor in high temperature and harsh environment iswidely known. However, utilizing the Vertical Channel 4H-SiCJFET (SiC JFET) for analog design exhibits significant designchallenges, even at room temperature. The fundamental chal-lenges are low intrinsic gain, the limitation of the Gate to SourceVoltage Range (GSVR), and restrictions on utilizing ChannelLength (CL) as a design parameter due to fabrication complexity.These challenges must be successfully overcome at room temper-ature, before moving towards high temperature design. The mainobjective of this paper is to establish a design base, overcome thechallenges, demonstrate the feasibility, and present a novel all SiCJFET based operational amplifier (opamp) that addresses overallperformance at room temperature. Before attempting design,Enhancement Mode (EM) and Depletion Mode (DM) SiC JFETsare characterized, analyzed, andmodeled for simulation. A uniqueand reliable four stage opamp configuration is presented that takesdesign requirements into account, uses threshold voltage inplace of CL as a design parameter, and employs gain enhancingdesign techniques while achieving maximum obtainable frequencyresponse. The final opamp is fabricated and tested and shown tohave 66.7 dB DC gain and 5.71 MHz unity gain frequency.

Index Terms—Analog, JFET, operational amplifier, silicon car-bide.

I. INTRODUCTION

D EMAND for capable and reliable semiconductor anddevice fabrication technology for high temperature

electronics, for power electronics, or for both applicationshas increased in recent years. Silicon Carbide (SiC) is a widebandgap compound semiconductor (4H-SiC with 3.2 eV) thathas superior characteristics such as high thermal conductivity,high breakdown voltage, and long-lasting reliable operation atelevated temperature i.e., operation at 500 C for over seventhousand hours [1], [2]. SiC based Integrated circuits canprovide significant benefits in a variety of harsh environmentapplications. Integrated power management units [3] and con-version modules in Hybrid Electric Vehicles (HEVs), integratedsensors for aircraft engines, and development of button-sized

Manuscript received November 02, 2010; revised February 26, 2011 andMay06, 2011; accepted June 09, 2011. Date of publication September 15, 2011; dateof current version January 27, 2012. This paper was recommended by AssociateEditor J. Li.A. Maralani is with the Berkeley Sensor and Actuator Center (BSAC),

University of California, Berkeley, CA 94720 USA (e-mail: [email protected]).M. S. Mazzola is with the Department of Electrical and Computer En-

gineering, Mississippi State University, Mississippi State, MS 39762 USA(e-mail: [email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TCSI.2011.2162370

portable power generators [4] are among the many applicationsthat require reliable integrated circuits with long functional lifetimes. Operational amplifiers (opamps) as the main elements inthe mentioned systems are a subject of research in SiC devices.Opamps have been reported based on SiC MOSFET [5]–[7]and SiC MESFET [8] devices. This paper presents an all Ver-tical Channel 4H-SiC JFET (SiC JFET) based opamp, whichis designed, fabricated, and tested. SiC MOSFETs and theiranalog circuits show short functional lifetime related to thegate oxide at elevated temperature. Poor channel mobility dueto the channel-oxide interface imperfection is also a concern,especially in P-type SiC MOSFETs [7]. SiC MESFETs cansuffer backgating due to poor interface between the N-channeland P-type buried backgate layer [8]. In contrast, SiC JFETsare excellent candidates for high temperature and power elec-tronics applications for a number of reasons. SiC JFETs of thetype shown in Fig. 1(a) and (b) [9] have a physical structurethat is easier to fabricate and does not require a critical oxidelayer, thus, they are free of the related issues, making the designof the circuits adequately stable, reliable, and long-lasting[1], [2]. In SiC JFET devices, mobility degradation at highertemperature is also lower than the counterparts, thus, devicesmaintain higher transconductance at elevated temperature. TheSiC JFET has the additional advantage that it can be fabricatedin the form of an Enhancement Mode (EM) meaning a positivethreshold voltage for an N-channel device, and a Deple-tion Mode (DM) with a negative . As for design constraintof Gate to Source Voltage Range (GSVR), both MESFETsand JFETs have low GSVR compare to MOSFETs. GSVR isdefined as the range of applicable gate to source voltage of aJFET or MESFET in “ON” state where the gate to source P-Njunction is reverse biased. The lower and upper boundaries ofthe GSVR are determined by and the built in voltage ofthe gate to source P-N junction, respectively. Increasing gateto source voltage above the built in voltage will forward biasthe junction producing undesirable forward leakage current. Inorder not to enter to the forward bias region, the upper limit ofthe GSVR should stay below 2.5 V (4H-SiC bandgap is 3.2 eV)in room temperature (or below 2 V at 350 C). Therefore, in anEM SiC JFET where is greater than zero, maximum GSVRis less than 2.5 V at room temperature. With the silicon JFET,the maximum GSVR is less than 0.6 V making EM siliconJFET almost unusable. GSVR is considered a design constraintwhen the upper boundary of the GSVR (2.5 V) is less thanthe operating drain to source voltage of the transistor, whichis the case in this paper. The limitation of the GSVR creates asignificant design challenge in both analog and digital design,but it is more significant in the analog domain. This paper

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256 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 59, NO. 2, FEBRUARY 2012

Fig. 1. (a) Device structure of fabricated Vertical Channel 4H-SiC JFETs.m, mm, and m to 1.5 m (sizes are not in

scale). (b) SEM image of a fabricated SiC JFET. (c) Equivalent circuit modelfor SiC JFET.

shows that the challenge of the GSVR limitation is successfullyaddressed. Before starting the design, devices are characterizedand modeled for simulation, then the opamp circuit configura-tion and its design for overall performance is presented.

II. DEVICE CHARACTERISTICS AND MODELING

A conceptual device structure of a Vertical Channel 4H-SiCJFET [9], or simply SiC JFET, with Channel Length (CL) of2 m, Channel Width (CW) or FingerWidth (FW) of 2 mm, andFinger Length (FL) of 1.1 m to 1.5 m is shown in Fig. 1(a).From the size of the CW, it is realized that these devices wereoriginally fabricated for high current and power electronics ap-plications. Total CW of 2 mm is the sum of the parallel arrays ofthe fingers shown in the SEM image of Fig. 1(b). Both EM andDM devices that are used throughout this paper share the samedevice structure and geometry, with the exception of different

FLs. Devices with FL of 1.1 m are EM devices (positive ),while the longer ones towards 1.5 m are DM devices (nega-tive ). Besides changing FL, the of the device can beadjusted by changing the doping level of the device channel.Fig. 1(a) reveals an important point that the device channel isvertical, which implies that it is difficult to fabricate a numberof these transistors with various CLs all of them on the samedie. Therefore, choosing arbitrary CL (when vertical channeldevices are used) as a design parameter for analog circuit de-sign is quite restricted. In order to solve this problem, in thispaper, parameter is used instead of CL to adjust the outputresistance of the devices (noting that and CL are indepen-dent parameters). Section II-A provides detailed discussion onthis subject.In the modeling process, both EM and DM devices are char-

acterized and modeled using level five GaAs FET [10] model.A suitable SPICE model to support the simulation of SiC JFETbased analog circuits has an essential role in the design process.Our emphasis is analog circuit analysis and design using the SiCJFET, rather than device specific modeling; therefore, the GaAsFET model is used because it is a built-in model in SPICE andsimulation tools and was suitably adapted for this work. Thesimilarity between the current versus voltage characteristics ofthe two compound semiconductor devices (GaAs FET and SiCJFET) allows us to apply the model and obtain a quite accu-rate result. A level five GaAs FET model based on the equiva-lent circuit model [10] shown in Fig. 1(c) defines cutoff, linearand saturation region, and versus in (1), (2), and (3),respectively.

(1)

(2)

(3)

A summary of the parameters used in the equations is given inTable I [10]. To visually inspect the modeling and its accuracy,a DM device with of 0.68 V is characterized and modeledat room temperature, as shown in Figs. 2, 3(a), and 3(b). On themeasured curves of the Fig. 2 device self-heating due to highdrain current can be observed at higher , in the saturationregion. That feature does not create any performance issues forthe opamp because every stage of the opamp designed to operateat drain currents below where self-heating could otherwise besignificant.Although the aim of this paper is to identify and overcome

analog design challenges associated with SiC JFETs at room

MARALANI AND MAZZOLA: THE DESIGN OF AN OPERATIONAL AMPLIFIER USING SILICON CARBIDE JFETS 257

TABLE ISUMMARY OF THE MODEL PARAMETERS AND DESCRIPTIONS

Fig. 2. Measured and modeled versus curves of a DM SiC JFET with, and m, mm.

Fig. 3. Measured and modeled (a) versus and (b) versuscurves of a DM SiC JFET with , and m,mm.

temperature, it is also informative to illustrate some of thebasic characteristics of these devices at elevated temperature.Fig. 4 shows measured transconductance, output resistance,

Fig. 4. Measured transconductance, output resistance, and threshold voltagevariation of an EM device in the temperature range of 25 C to400 C.

and threshold voltage variation of an EM devicein the temperature range of 25 C to 400 C. Obviously, theperformance of these devices is well beyond the capability ofsilicon and SiC MOSFET [5]–[7] devices, but they are yet tobe optimized for high temperature opamp design. Transcon-ductance and output resistance variation of the devices can beadjusted to meet the design requirements at elevated tempera-ture. Threshold voltage variation of mV C is more thanthree times better than the reported variation of mV Cin existing SiC MOSFETs [7]. Therefore, the SiC JFET showsbetter thermal and threshold voltage stability in a wider tem-perature range than for the SiC MOSFET.

A. Device Characteristics for Design

In order to evaluate the device capabilities for amplificationstages, maximum transconductance and average output resis-tance of a number of EM and DM devices based on theirare measured (in the saturation region) and shown in Fig. 5(a).Fig. 5(b) shows a basic self-biased Common Source Amplifier(CSA) illustrating the driver J1 as an EM SiC JFET and thecurrent source or load transistor J2 as a DM SiC JFET. Ob-viously, driver transistor J1 must have higher than J2 todrive the drain current. Moreover, EMs show higher transcon-ductance and output resistance than DMs resulting in higherintrinsic gain. However, there is tradeoff between the intrinsicgain and the GSVR of the devices. If higher GSVR is requiredinstead of a higher gain, then DMs can also be used as drivers,and the load transistors always have to have lower than thedriver transistors. As mentioned earlier, fabrication restrictionin utilizing CL as a design parameter is another design chal-lenge that is compensated by using instead. For instance,as device increases from negative to positive, both outputresistance and transconductance increase resulting in intrinsicgain to increase, which is shown in Fig. 5(a); therefore, canplay a similar (but not an exact) role as CL. The difference be-tween the influence of CL and that of is that CL is inverselyproportional to the transconductance, where as is in directproportion. Increasing CL increases output resistance but de-creases transconductance, while increasing from negativeto positive in these devices increases both output resistance andtransconductance. To illustrate the use of in the absence ofCL for gain adjustment, level one drain current (4) can be con-sidered [11]. Equation (5) represents drain current in the sat-uration region. By applying (5) into the gain relation (6) and


Fig. 5. (a) Maximum transconductance and average output resistance variationof the devices based on their , in the saturation region. (b) Basic CSA withself-biased current source load. (c) Gain variation of the CSA based on thevariation of the driver and current source load transistors.

knowing that both EM and DM have the same dimensions ex-cept different FLs, (7) is obtained. Equation (8) shows that if

of J2 tends to zero, maximum gain can be achieved.

(4)

(5)

(6)

(7)

(8)

This means that moving J2’s closer to J1’s causes currentand transconductance to drop, but a large increase in output re-sistance results in an increase in the overall gain [12]. It canbe realized [12] that in a basic CSA (Fig. 5(b)), if the ofJ1 and J2 are chosen to be 0.5 V and 0.5 V, respectively, awell-balanced combination of gain and drain current can be ob-tained. Since the variation of is proportional to overall gain,its effect is sometimes undesirable, i.e., when variation ofis due to the fabrication process variation. In order to illustratehow much this variation will affect the overall gain, a numberof CSA with driver and load transistors having various wastested. The measurement result, that is also consistent with (7),is shown in Fig. 5(c). The peak point is 41 , and theminimum is 24 . Process variation in the form ofvariation can be compensated by using a number of circuit tech-niques such as adding a tuning sub-circuit [13]. Since the designand fabrication of SiC JFET based circuits are in an early stage,the aim of this paper is to avoid complexity and employ a min-imum number of transistors.

B. Current Source Configurations and Characteristics

DM devices are used as current sources or loads for am-plifiers. Fig. 6(a) to (f) shows various load configurations ina self-biased current source mode. Self-biasing eliminates ad-ditional biasing circuits. The corresponding output resistanceprofile of each load configuration is measured and presented inFig. 6(g). The single transistor load in Fig. 6(a) has the lowestoutput resistance. Double transistors with cascoded configura-tion show quite an improvement. In Fig. 6(b), two exact deviceswith the same are used. However, we have found that if J2has a more negative (Fig. 6(c)), the result is more currentdeliverability and higher output resistance, at the same time. Inother words, J1 will be able to maintain more drain to sourcevoltage (as long as J2 is on) moving more towards the saturationregion and benefiting from its higher output resistance. Whenthis configuration is used in the basic CSA of Fig. 5(b), higheroutput resistance, along with higher current deliverability, en-ables the driver to maintain higher transconductance, resultingin a gain improvement. Fig. 6(h) presents measured gain of theCSA using various load types from Fig. 6(a) to (f). Equations(9) through (12) show the overall output resistance of each con-figuration with respect to the transconductance and output resis-tance of the transistors.

(9)

(10)

(11)

(12)


As the number of cascoded transistors increases in Fig. 6(d)[14] through 6(f), higher output resistance can be observed.Fig. 6(e) shows a better curve at lower compared to othersbut less current deliverability, resulting in lower gain, shown inFig. 6(h). Fig. 6(f) is an improved version of Fig. 6(e), where theamount of current can be adjusted by of J2 and J3. Based onthe current and gain requirement of a CSA, a load configurationcan be selected using Fig. 6(a) to (h).

III. OPAMP CONFIGURATION AND DESCRIPTION

The overall configuration of the opamp that is capable ofdriving a 1 nF capacitive load, shown in Fig. 7(a), containsfour stages and two Compensation Elements (CEs) composedas CE1 and CE2. Corresponding circuit blocks of the four stageconfiguration are illustrated in Fig. 7(b) to (e). Themain strategyof the overall design is to keep the number of transistors to aminimum. In the first stage, a differential amplifier (diffamp)is followed by a Differential to Single ended and Level Shifter(DSLS). A Common Gate Amplifier (CGA) is employed as athird stage, which is seldom seen in conventional opamps. Usu-ally a high gain CSA is used as a second amplifier stage, but inthe case of the SiC JFET, the low Input Voltage Range (IVR) ofa CSA (because of the low GSVR of the EM device) preventsits use. Instead, a source degenerated configuration can be used,which introduces a significant tradeoff between gain and IVR.Unlike a CSA, a CGA has a higher IVR for a comparable gain.A CGA provides the opamp not only a high gain, but also amaximum achievable unity gain frequency in a two gain stageopamp. In the final stage, a Source Follower (SF) is used to de-liver the amplified signal to the load.

A. Differential Amplifier With Enhanced Cascoded Load

The first stage of the opamp in Fig. 7(b) is a diffamp, whichuses the enhanced cascoded load configuration of Fig. 6(c). Itconsists of four EM devices, J1–J4 with of 0.5, and fourDM devices, J5–J8 with of 0.5, 0.5, 2, and 2, re-spectively. J3 and J4 are cascoded EM devices to obtain hightail output resistance and better CommonMode Rejection Ratio(CMRR). Fig. 8(a) shows the measured gain of the diffamp,which produces 28 voltage gain with an offset voltageof 59 mV created by geometrical mismatch and process vari-ation of the transistors. The fabrication technology for SiC de-vices andmore specifically SiC JFET transistors and differentialpairs is still evolving; therefore, the design should accommodatethe currently larger tolerances for devices. The small signal dif-ferential gain equation of the diffamp is presented in (13) and(14):

(13)

(14)

The frequency response of the diffamp is measured and shownin Fig. 8(b). Cutoff frequency is 610 KHz, and unity gain fre-quency is 23 MHz. These devices were designed and fabricatedfor high current and power electronics applications; correspond-ingly their gate to drain and gate to source areas are very large,

Fig. 6. (a) DM SiC JFET based current source load in self-biased configura-tion. (b) Double cascoded load with to enhance the outputresistance. (c) Double cascoded load with more negative thanto better enhance the output resistance. (d) through (f) Triple cascoded load withvarious for J1, J2, and J3 for higher output resistance. (g) Output resistancecurves of DM SiC JFET based current source loads from (a) to (f) configura-tions. (h) Gain of the CSA with various load types from (a) to (f).

and so are their associated capacitances. The device structurein Fig. 1(a) reveals that the area between gate to drain is evenlarger than the area between gate to source. These two reasonsexplain the limitation seen in the diffamp’s measured frequencyresponse. However, the frequency response can be improved byusing transistors with smaller geometry.


Fig. 7. (a) Circuit configuration of the opamp with external CE1 and CE2. (b) First stage or diffamp with enhanced cascoded load. (c) Second stage or DSLS.(d) Third stage or CGA. (e) Output stage or SF.

B. Differential to Single Ended and Level Shifter

The second stage of the opamp is a differential to single-ended level shifter (DSLS) that contains eight EM transistors,J9–J16 with of 0.5 V. It plays an essential role in the en-tire design (Fig. 7(c)) by delivering a preamplified signal to thesecond amplifier stage. It inputs differential signals and con-verts them to a single ended output. The DSLS biases the secondgain stage (CGA) and ensures that the GSVR limitation of thedriver transistor of the CGA is respected. Four diode connectedEM transistors, J13–J16, not only level shift the output signalbut also make sure that the GSVR limitation of the transistorsJ9–J10 are also accounted for. Small signal analysis of the DSLSis conducted and differential mode gain, common mode gain,and differential to common mode gain ratio are calculated andshown in (15), (16), and (17), respectively (shown at the bottomof the next page). Considering these equations, differential andcommon mode gains of 1.16 V/V and 0.19 V/V can be obtainedresulting in a differential to common mode gain ratio of 6.1V/V. The CMRR of the opamp is mainly determined by the dif-famp. However, the DSLS contributes to the overall CMRR aswell. It should be mentioned that the number of these diode con-nected transistors can determine the amount of level shifting,differential to common mode gains ratio, and the output voltageswing. In other words, when the number of these diodes in-creases both differential and common mode gains decrease, but

common mode gain decreases more rapidly resulting in an in-crease in the differential to common mode gain ratio, which isa desirable effect. For example, using the four diode connectedtransistors in Fig. 7(c) resulted in an increase of 17% in the dif-ferential to common mode gain ratio compared to using onlytwo diode connected transistors. If no diodes are used, the DSLSis simplified [15] and the voltage swing is maximized, and equa-tions reduce to (18) and (19), shown at the bottom of the nextpage. This is not recommended, because J9 and J10 will receiveexcessive gate to source voltages beyond their GSVR limits.

C. Common Gate AmplifierThe third stage of the opamp is a CGA in Fig. 7(d). This stage

consists of a driver, J17 with of 0.5, connected to thecurrent source load configuration of Fig. 6(e), which provideshigh output resistance. Transistors J25–J28 are DMdevices with

of 0.5 V used as voltage dividers. Transistor J24 is an EMdevice with of 0.5 V used as a diode connected device toset the gate bias voltage for J17. The measured gain of the CGAin Fig. 8(c) shows 79.8 amplification, as a second gainstage. In Fig. 8(d), the measured frequency response of the CGAshows a cutoff frequency of 490 KHz and a unity gain frequencyof 28 MHz, which is greater than that of a CSA, as expected. Anadditional benefit of using a CGA is that the IVR of the amplifieris greater than the GSVR of the driver transistor (J17), unlike ina CSA. Therefore, CGA can receive a higher IVR from DSLS


before J17 becomes overdriven. Consequently, reliability of thedesign (opamp) increases. The small signal gain of the CGA iscalculated and shown in (20):

(20)

D. Source Follower Stage

The fourth stage of the opamp is a SF, in Fig. 7(e), consistingof two EM, J21 and J22 ( of 0.5), and a DM J23 withof 1.5 V. This stage can supply 56 mA of current and is ca-pable of driving a 1-nF capacitive load. Diode connected J22 isused to down level-shift the output in order to ensure that J1 andJ2 will not be overdriven (because of their GSVR limitations)when the opamp is used in a feedback mode. Equation (21) rep-resents the small signal gain of the SF, which is less than unity:

(21)

E. Frequency Compensation of the Opamp

In order to provide the opamp with stability, the compensa-tion scheme of Fig. 9 is used. In this opamp other compensation

schemes, such as Miller, nested Miller, etc., would not be prac-tical because there is no high gain inverting stage, plus the aimis to avoid complexity and to use a minimum number of transis-tors. Fig. 9 shows the first stage (diffamp) with andwithout com-pensation along with an ac model for stability analysis. Equa-tions (22) and (23) show the frequency response of the diffampwithout compensation.

(22)

(23)

A pole associated with the amplifier’s input (a low frequencypole) and the amplifier’s output (a high frequency pole) and aright half plane zero created by gate to drain capacitances ofthe driver transistors J1 in (22) and J2 in (23) can be observed.The right half plane zero has the same effect on the transferfunction’s phase response as a left half plane pole; consequently,the combination of a low frequency pole and a right half plane

(15)

(16)

(17)

(18)

(19)


Fig. 8. (a) Transfer curves of the diffamp with gain of 28 on eachoutput side. (b) Frequency response of the diffamp. (c) Second amplifier (CGA)with gain of 79.8 . (d) Frequency response of the CGA.

zero results in a 180 phase drop producing instability. In orderto introduce stability to the opamp, CE1 and CE2, which containcompensation capacitors in series with resistors are

Fig. 9. Diffamp and compensation scheme of the opamp.

added to the outputs of the diffamp (Fig. 9). Equations (24) and(25) demonstrate the frequency response of the amplifier withcompensation in effect:

(24)

(25)

Due to the compensation, both a new dominant pole and a lefthalf plane zero are created and located in the denominator andnumerator of the transfer functions. A compensation capacitor

adds a new dominant low frequency pole to roll off themagnitude response before reaching to the previous low fre-quency pole. The small series resistor adds a new left halfplane zero to control the effect of the right half plane zero. Itreverses the phase drop created by the new pole and continuesthe reversal until reaching the right half plane zero and the fol-lowing pole (a high frequency pole). Therefore, the phase re-sponse of the amplifier maintains an appropriate phase margin,introducing stability to the opamp.


Fig. 10. Final schematic of the opamp.

IV. COMPLETE OPAMP AND RESULTS

The complete opamp of Fig. 10 contains all the describedstages plus a bias stage setting appropriate tail current for thediffamp to obtain maximum differential gain. Since the InputCommon Mode Range (ICMR) of the diffamp depends on thetail bias current, the current can be reduced to increase the ICMRat the expense of reducing the maximum differential gain. Thefinal design shown in Fig. 13 was fabricated, packaged, andtested. Since fabrication of analog circuits with SiC devicesof any kind is in its infancy, non idealities, such as large mis-matches and offsets, are expected. The final opamp is fabri-cated by integrating forty die on an aluminum nitride substrateand wire bounding the connections. Each die is 650 m by650 m containing four transistors. Every stage, along withthe entire opamp, is both simulated and tested. In the devicemodeling process, devices are modeled to reflect slightly worsesmall signal characteristics than their actual measured charac-teristics; therefore, test results always showed slightly betterperformance than the simulation results. Performance param-eters of this opamp are shown in Fig. 11, Fig. 12, and Table II.In Table II the performance parameters of the current work arecompared with previous work [16]. Previous work was focusedon gain and CMRR, while this work emphasizes on a more uni-versal design for overall performance with improved reliability,since the influence of the GSVR limitation is reduced. More-over, Table II shows that the unity gain frequency and slew rateof the current design are improved significantly. Improvementin the unity gain frequency and reliability is a direct result ofusing a CGA as the second stage of amplification. It should bementioned that the input voltages of J1 and J2 have to be withinthe ICMR and should not exceed the ICMR’s upper limit; oth-erwise, they will be overdriven beyond their GSVR limits.SiC JFET device fabrication technology is evolving and the

performance of the devices is improving; consequently, thereare only a few SiC JFET based circuit design reports publishedto date. A design work [17], which was concurrently conducted

Fig. 11. (a) Frequency and phase response of the opamp. (b) Output of theopamp driving a 1 nF capacitive load.

with this work, has reported a number of diffamps based onLateral Channel DM SiC JFET and Resistor technology. Usingthis technology has both advantages and disadvantages overusing Vertical Channel EM & DM SiC JFET technology. ALateral Channel DM SiC JFET has higher GSVR compared toEM devices and device fabrication and integration for mono-lithic design is easier than the Vertical Channel SiC JFET. How-ever, the lack of a Lateral Channel complementary device is adisadvantage that results in reducing the design flexibility and


Fig. 12. (a) CMRR, PSRR+, and PSRR- performance of the opamp. (b) ICMRperformance of the opamp.

Fig. 13. Fabricated, packaged, and tested fully EM and DM SiC JFET-basedopamps.

limiting the circuit functionality. The Transistor/Resistor tech-nology that was used in [17] cannot accommodate a differentialinput to single ended output opamp architecture without usingcomplementary devices. Additionally, the use of resistive loadsforced the supply voltage (VDD) to be high enough to ensurethat the devices are in saturation. As supply voltage increases,both power consumption and resistive self-heating increase. Asummary of the advantages and disadvantages of using VerticalChannel SiC JFET technology over Lateral Channel DM SiCJFET and Resistor technology is presented in Table III.

TABLE IIPERFORMANCE PARAMETERS SUMMARY OF THE CURRENT SIC JFET OPAMP

COMPARED WITH PREVIOUS WORK [16]

, , , ,, and C.

, , , , ,and C.

TABLE IIICOMPARISON SUMMARY OF THE CURRENT DESIGN WITH THE DESIGNS IN [17]

V. CONCLUSION

The design of a novel fully EM and DM SiC JFET basedopamp with unique and reliable configuration is presented. Thedesign had to overcome three major challenges imposed by SiCJFETs: low intrinsic gain, limited GSVR, and the restrictionon utilizing CL as a design parameter due to fabrication com-plexity. The low intrinsic gain issue is addressed by introducingand employing enhanced cascoded current source or load con-figurations to control the drain current and the gain of the am-plifiers. A CGA structure, which is seldom used in opamps, isused to achieve a high gain and maximum obtainable unity gainfrequency in an opamp with two amplifier stages. The GSVRlimitation is taken into account by: 1) using EM devices in a


diode connected configuration for level shifting to avoid over-driving of the transistors inputs beyond their GSVR, and 2) em-ploying a CGA that is capable of receiving higher IVR, un-like a CSA. Restrictions on utilizing CL as a design parameterdue to fabrication complexity is resolved by using param-eter of the devices instead. In designing the opamp, a diffampwith enhanced cascoded current source load, a reliable DSLS, aCGA for overall gain and reliability, and a first stage compensa-tion scheme were presented. The performance of the fabricatedfinal design confirms the feasibility of employing SiC JFETs inanalog design. The opamp’s performance can be improved in thefuture, as the fabrication process and technology are being im-proved. Highly matched devices with smaller feature size willreduce offsets and improve the opamp’s unity gain frequency.

ACKNOWLEDGMENT

The authors thank SemiSouth Laboratories, especially Dr.J. Casady and Dr. D. Sheridan for their supply of devices usedin this work, Dr. I. Sankin and Dr. A. Ritenour for their valuablediscussion on devices, andMr. V. Bondarenko for his assistancein characterization and packaging.

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Ayden Maralani (S’09–M’10) received the Ph.D.degree in electrical engineering from MississippiState University in 2009.He is currently with the Berkeley Sensor and

Actuator Center (BSAC), University of California,Berkeley, as an Assistant Scientist working withProfessor Albert P. Pisano. His research interestincludes analog/mixed signal IC design and de-sign/fabrication of circuits and systems for MEMS,harsh environment, and energy management ap-plications. Prior to joining BSAC, he held Design

Engineer positions with the I/O Center of Excellence of Cypress Semiconductorand SemiSouth Laboratories designing SiC JFET based analog/digital circuitsfor harsh environment and power management applications.

Michael S. Mazzola (S’84–M’86) received thePh.D. degree from Old Dominion University, Nor-folk, VA, in 1990.He is currently a Professor of electrical and com-

puter engineering at Mississippi State University(MSU). From 1990 to 1993, he worked at the NavalSurface Warfare Center in pulsed power researchand technology. In 1993, he joined the faculty ofMississippi State University and taught within theDepartment of Electrical and Computer Engineering.He has a technical background in semiconductor

devices and applications in power electronics, and their application in automo-biles gained while leading research in the MSU Center for Advanced VehicularSystems (CAVS). He has contributed in the areas of silicon carbide deviceprototyping and application as well as materials growth and characterizationfor the last 16 years. He is a co-founder of SemiSouth Laboratories, Inc., acommercial producer of silicon carbide power devices. From 2005 to 2007,while on a leave of absence from MSU, he served as Vice President forTechnology. He has published more than 100 papers and has been awarded 11patents.Dr. Mazzola is a Registered Professional Engineer.

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