A Study of Low-Power Crystal Oscillator Design

Kin Keung Lee∗†, Kristian Granhaug∗, and Nikolaj Andersen∗∗Novelda AS, Gjerdrums vei 8, N-0484 Oslo, Norway

†Department of Informatics, University of Oslo, N-0316 Oslo, Norway

E-mail: kklee@ifi.uio.no

Abstract—UWB backscatter RFID systems require high qual-ity clock signals and crystal oscillator is one of the few candidates.A study of a low-power parallel-mode crystal oscillator for suchapplications is presented. A 7.8125 MHz Pierce crystal oscillatoris realized in a TSMC 90 nm CMOS process. It has a frequencystability of ±7 ppm from 0 to 70 ◦C and draws 36 μW from a1.2 V supply. The core area excluding pads is 0.021 mm2.

Index Terms—CMOS, crystal oscillator, low-power, Pierce,RFID

I. INTRODUCTION

A UWB backscatter RFID system was proposed in [1].

Compared to the conventional narrowband counterparts, this

solution is more robustness to multipath fading and provides

accurate localization capability. One of the key components is

the clock generator, its performance affects the system detec-

tion rate. The absolute tolerance on the clock frequency has

to be smaller than ±100 ppm in order to achieve a desirable

communication quality [2], this requires a high performance

resonator (i.e. with high quality factor, Q) which is not avail-

able in standard CMOS processes. Crystal oscillators are one

of the only few candidates that can achieve such requirements.

It has very good frequency stability because it utilizes quartz

crystal which is a very good resonator (Q is usually in the

order of 100k). In addition, the power consumption has to

be minimized in order to increase the battery life and, hence,

reduce the maintenance cost.

In this paper, a study of low-power crystal oscillator design

is presented. A 7.8125 MHz Pierce crystal oscillator for UWB

RFID applications is realized in a TSMC 90 nm process.

Measurements show a frequency stability of ±7 ppm from

0 to 70 ◦C. The power consumption is estimated to be around

36 μW from a 1.2 V supply. The paper is organized as follows.

Section II describes the oscillator design. Experimental results

are described in Section III. A conclusion is presented in

Section IV.

II. CRYSTAL OSCILLATOR DESIGN

A. Crystal Model

A model of the crystal [3] is shown in Fig. 1, RM , CM and

LM are the motional resistance, capacitance and inductance

respectively and C0 is the package capacitance between the

inputs. Some of these parameters may be missing or over-

estimated on the datasheets, it is recommended to request the

measurement data from the manufacturers in order to optimize

the design. This can make sure a good candidate is chosen

before the design. Some manufacturers also provide custom-

made crystal manufacturing even for small-volume orders. A

custom-made AT-cut 7.8125 MHz fundamental-mode parallel-

resonant crystal in a HC49S package is used in this work.

Fig. 2 shows an example curve of the crystal reactance vs.

frequency, where fs and fp are the series and parallel resonant

frequencies respectively [4] and fs is given by:

fs =1

2π√

LmCm

(1)

Between fs and fp, the crystal acts as an inductor and the

reactance changes from 0 to positive infinite, which means,

ideally, the crystal can absorb any value of capacitance and

oscillate [5]. The difference between fs and fp (Δf ) is usuallysmall because of the high Q. Crystal oscillators operating in

this frequency range are referred to parallel-resonant topology.

Such topology is widely used for fundamental-mode crystal

oscillator because it usually requires fewer components and is

easier to design.

A useful parameter to compare different crystals is their

figure-of-merit (M ). It is defined as the maximum possible

ratio of current through the motional components and static

components (i.e. C0) and given by

M =1

ωoC0Rm=

QCm

C0(2)

RM CM LM

C0

Fig. 1. Crystal model.

freq.

Reactance

fpfs

f

MoreInductive

MoreCapacitive

Fig. 2. Crystal reactance vs. frequency.

978-1-4799-1647-4/13/$31.00 ©2013 IEEE

M1

RB

C1 C2X1

IBias

Fig. 3. Conventional Pierce crystal oscillator.

M1X1

RBM2

C1 C2

CC

RDCIBias

VB

M1X1

RBM2

C1 C2

(a) (b)

Fig. 4. a) Inverter-based and b) class-AB Pierce crystal oscillators.

Obviously any parasitic loading across the crystal inputs will

degrade its performance and should be minimized.

B. Conventional Pierce Crystal Oscillator

Pierce crystal oscillator is a very widely used parallel-

resonant topology because of its simplicity. In addition, it usu-

ally introduces less parasitic loading to the crystal compared

to other topologies [5]. Its conventional structure is shown in

Fig. 3a. In this section, we assume the oscillator is lossless

and the output swing is small enough so that the system is

linear. The oscillating frequency is given as

fo = fs · (1 + pc) (3)

where pc is the pulling factor and given as

pc =Cm

2CL(4)

and

CL = CGD +CGSCDS

CGS + CDS≈ C0 +

C1C2

C1 + C2(5)

if we assume the transistor parasitic capacitances are small

and can be ignored.

The impedance looking into the crystal inputs is given as

[3], [6]

Zxtal =Z1Z0 + Z2Z0 + gm1Z1Z2Z0

Z1 + Z2 + Z0 + gm1Z1Z2(6)

M1

RB×1×10

IBiasC1 C2

×1

M2

X1Vo

ROC

M8IBiasVBG M4

VIVI+

M3

M5 M6

M7

Vo

(a)

(b) (c)

Fig. 5. a) Top-level schematic, b) bias current generator and c) differentialamplifier.

where Zi = (jωCi)−1 and gm1 is the transconductance of

transistor M1. Zxtal is negative for small gm1 and the oscillator

will oscillate if −Re(Zxtal) ≥ Rm, which yields

gm1 ≥ gm1,min ≈ ωC1C2

QCm

(1 +

C0

C1||C2

)(7)

Usually |Re(Zxtal)| is set to 2-3 times larger than Rm to

ensure oscillation start-up. Also, the start-up time constant is

given as:

τs =Lm

Re(Zxtal) + Rm(8)

A fast start-up (order of ms) is needed for the targeted

application in order to achieve synchronization between the tag

and reader. Large gm1 can provide faster start-up and larger

oscillating amplitude. However, when the oscillating ampli-

tude is too large, M1 will enter triode region and introduce

distortion.

C. Other Kinds of Pierce Crystal Oscillator

An inverter-based Pierce crystal oscillator structure is shown

in Fig. 4a. The main advantage is its simplicity, no biasing

circuit is needed. Also, the PMOS transistor M2 provides

extra transconductance, which potentially reduces the power

consumption. However, it is difficult to control the output

swing, the transistors may operate in triode region and this

increases the non-linearity [3].

To improve this, class-AB structure was proposed [7] and

shown in Fig. 4b. The trade-off is the increased circuit com-

plexity, additional circuits are needed to bias M2.

a

b

c

d d

278μm

77μm

Fig. 6. A chip photo and layout. a: Current generator, b: Output buffer, c:Oscillator core and d: C1 & C2 (10 pF each).

Fig. 7. fo variation vs. temperature.

D. Designed Crystal Oscillator

The conventional structure is adopted as a trade-off between

circuit complexity and performance. The top-level schematic

is shown in Fig. 5a. Accounting for the losses, the following

condition has to be meet [3]:

gm1 ≥ gm1,min + G1 + G2 + 4G0 (9)

where G0 = R−1B , G1 and G2 are the loss conductance mainly

due to the parasitic components of C1 and C2 respectively. It

is difficult to model pc and τs, nevertheless the effect due

to the losses are usually insignificant with careful design and

layout.

M1 is operating in moderated inversion region (with an

overdrived voltage of 180 mV) as a trade-off between power

consumption and size of parasitic capacitance. The output

swing (peak-to-peak) is set to be around 600 mV to reduce

the power consumption and lower the distortion. Also, it may

accelerate aging and even damage the crystal if too much

power is applied [3]. A buffer amplifier is needed to make the

output clock signal rail-to-rail. A diode-connected transistor

M2 is used to mimic M1 and generates the oscillator DC

output voltage. The bias current generator is shown in Fig.

5b, the generated current is given by:

IBias ≈ VBG

ROC(10)

III. EXPERIMENTAL RESULTS

The crystal oscillator is implemented in a TSMC 90 nm

CMOS process. A chip photo is shown in Fig. 6. The core

area excluding pads is 278 × 77 μm2. The oscillator shares

the same power domain with other circuits on-chip, hence

Fig. 8. Start-up behavior. Upper: VDD ; lower: oscillator output.

Fig. 9. Oscillator output frequency spectrum.

Fig. 10. Simulated oscillator phase noise.

the oscillator power consumption cannot be measured indi-

vidually. Post-layout simulations show the power consumption

(including the bias current generator and buffer amplifier) to

be approximately 36 μW from a supply voltage of 1.2 V.

Fig. 7 shows the fo variation vs. temperature, the variation

is within ±7 ppm from 0 to 70 ◦C. The start-up behavior is

shown in Fig. 8. The start-up time shows to be around 14 ms.

However the start-up time is increased due to the extra probe

parasitic capacitance loads and the actual start-up time should

be smaller.

The output frequency spectrum is measured using a signal

analyzer Agilent N9010A and shown in Fig. 9, notice that

the oscillation frequency is also shifted a bit due to the probe

loading. The oscillator phase noise is buried by the noise from

the testing instruments. To solve this, some other measurement

methods were proposed in [8], however we are not able to do

this because of the lack of needed instruments. The ampli-

tude shown in Fig. 9 (i.e. –38.34 dBm) is heavily attenuated

because of the uses of passive probes. The simulated phase

noise is shown in Fig. 10.

IV. CONCLUSION

A study of low-power parallel-mode crystal oscillator

was presented. Different areas like topologies, trade-offs

between different parameters etc were discussed and

analyzed. Based on the analysis results, a low-power

7.8125 MHz Pierce crystal oscillator targeted for UWB

backscatter RFID system is realized in a TSMC 90 nm

CMOS process. It had a frequency stability of ±7 ppm from

0 to 70 ◦C and drew 36 μW from a 1.2 V supply. The

core area excluding pads is 0.021 mm2.

ACKNOWLEDGMENT

This work has been funded by the European Commission

through the FP7 project SELECT (grant no. 257544). The

authors would like to thank Pericom Semiconductor Corp. for

fabricating the crystal.

REFERENCES

[1] Available online: http://www.selectwireless.eu.[2] N. Decarli, F. Guidi, A. Conti, and D. Dardari, “Interference and clock

drift effects in uwb rfid systems using backscatter modulation,” in Proc.IEEE International Conference on Ultra-Wideband, Sep 2012, pp. 546–550.

[3] E. Vittoz, Low-Power Crystal and MEMS Oscillators: The Experience ofWatch Developments. Springer-Verlag, 2010.

[4] Statek Corp., “The quartz crystal model and its frequencies,” in TechnicalNote, no. 32.

[5] A. Niknejad, EE242 Lecture Notes, U.C. Berkeley, Spring 2007.[6] Y. H. Chee, Ultra Low Power Transmitters for Wireless Sensor Networks.

Ph.D. Dissertation, U.C. Berkeley, 2006.[7] D. Aebischer, H. Oguey, and V. von Kaenel, “A 2.1 MHz crystal oscillator

time base with a current consumption under 500 nA,” IEEE J. Solid-StateCircuits, vol. 32, no. 7, pp. 999–1005, Jul 1997.

[8] O. Rajala, Oscillaor Phase Noise Measurements Using the Phase LockMethod. M.Sc. Disseration, Tampere University of Technology, 2010.