Full Wafer Nanotopography Analysis on Rough

Surfaces Using Stitched White Light Interferometry

Images

Dirk Lewke, Martin Schellenberger, Lothar Pfitzner

Fraunhofer Institute for Integrated Systems

and Device Technology, IISB

Erlangen, Germany

dirk.lewke@iisb.fraunhofer.de

Thomas Fries, Bastian Tröger, Alexander Muehlig

Fries Research & Technology GmbH, FRT

Bergisch Gladbach, Germany

Frank Riedel, Stefan Bauer, Hubert Wihr

Siltronic AG

Burghausen, Germany

Abstract—Feature sizes of transistors manufactured on silicon

wafers in high volume reached 22 nm and will further decrease in

the future. Superior wafer surface quality is mandatory to

produce such small feature sizes. One relevant quality parameter

is the nanotopography of the wafers surface. Applying dedicated

state-of-the-art metrology systems, nanotopography is

characterized end-of-line of wafer manufacturing on wafers with

specular reflectance. In order to continuously improve wafer

quality and identify nanotopography related features early, a

measurement system capable of characterizing rough wafer

surfaces is required. This paper presents a NT analysis approach

using a white light interferometer (WLI) with a field of view of

85 x 85 mm2. An optimized stitching algorithm merges 16

individual WLI measurements to a height map of an entire

300 mm wafer. Nanotopography can be extracted at wafer edge

exclusion below 1 mm by applying flexible Gaussian high-pass

filters. A mathematical analysis of nanotopography

characteristics according to SEMI M43 is implemented. Gauge

repeatability and reproducibility studies provided standard

deviations of less than 1 nm on wafer surfaces as-ground by using

threshold height analysis (THA). This proves the measurement

system’s capability for nanotopography analysis at early states of

wafer manufacturing, which in turn can support improving

wafer surface quality.

Keywords—nanotopography; wafer manufacturing; stitching;

optical measurement; Gaussian filtering

I. INTRODUCTION

Current device feature sizes in the semiconductor industry reached 22 nm and will further decrease in the near future [1]. To manufacture such small features, the flatness of silicon wafers has to be of very high quality. One approach of characterizing this quality is by determining the so-called nanotopography (NT) [2] of wafers at the end-of-line (EoL) of wafer manufacturing [3]. To analyze NT, the topography of the wafer surface has to be measured and subsequently high-pass

filtered in order to unravel only those topography contributions at short spatial wavelengths between 0.2 mm and 20 mm, which typically exhibit amplitudes of few to tens nm [4][5][6].

Most state-of-the-art optical measurement systems analyze NT of surfaces with specular reflectance like those of, e. g., polished wafers [3]. Surface defects contributing to NT, which are generated at early stages of wafer manufacturing, may thus be detected EoL only. For enabling fast feedback loops and process optimization, a monitoring immediately after relevant manufacturing steps is desirable. Benefits are:

Identification of critical, NT related features on wafer surfaces at an early stage of wafer manufacturing.

Continuous improvement of relevant wafering, grinding, and lapping processes.

Fig. 1. The FRT multi sensor metrology tool performing nanotopography

analysis.

This R&D work has been performed within the framework of the European project SEAL (Contract Number: INFSO-ICT-257379). The

consortium acknowledges the European Commission for the support.

243978-1-4673-5007-5/13/$31.00 ©2013 IEEE ASMC 2013

This paper presents an approach dedicated for analyzing NT on rough surfaces like those of, e. g., ground or lapped wafers. The tool is based on the Fries Research & Technology FRT multi sensor metrology platform and equipped with a white light interferometer (WLI) system allowing for reliable topography measurements on rough surfaces, Fig. 1.

II. APPROACH FOR APPLYING NANOTOPOGRAPHY

ANALYSIS

Typical wafer geometry can essentially be subdivided into a bow, warp, NT, and micro-roughness regime. Micro-roughness is probed at very short spatial wavelength scale down to atomic distances, while bow and warp represent contributions to wafer geometry to be obtained at the opposite end of scale. NT is the non-planar deviation of a wafer surface at spatial wavelengths ranging from 0.2 mm to 20 mm [4][5][6], Fig. 2.

Fig. 2. Spatial wavelength regimes of roughness, nanotopography, warp and

bow of silicon wafers [6].

The research and development work reported here for developing a tool capable of measuring NT of rough wafer surfaces can be split into four steps:

Development of a sensor system based on a white light Michelson interferometer with a field of view (FoV) of 85 x 85 mm

2 in order to measure the topography of a

300 mm wafer surface by 16 individual snapshots across the wafer.

Optimizing stitching algorithms to obtain the entire surface topography map of a 300 mm wafer, compensating height offsets of the individual measurements and residual curvature of sensor images.

Implementing a high pass filter algorithm with a minimum filter edge effect in order to extract topography information at NT related spatial wavelengths scale with an edge exclusion less than one millimeter.

Analyzing and reporting the wafer NT according to SEMI M43 [4].

These four steps are now described in detail.

A. Mapping the wafer

The topography of wafer surfaces is obtained by applying a WLI sensor with 85 x 85 mm2

FoV based on a Michelson-interferometer setup [7]. WLI is used to achieve sufficiently high resolution on rough surfaces. In combination with specialized analysis software, lateral and vertical resolutions of 150 µm and < 10 nm, respectively, are achieved.

The wafer to be analyzed rests on an x-y-scanning stage. The stage positions the wafer beneath the WLI sensor. The orientation of the x-y-coordinate systems of sensor and stage are aligned. While sensor alignment and positioning accuracy of the stage are better than the lateral resolution of the WLI, each individual measurement can be exactly located on the global map. 16 single measurements are necessary to cover the entire 300 mm wafer at 85 x 85 mm2

FoV.

In order to perform an NT analysis according to SEMI M43 [4], one map of the whole wafer is required. Hence, the 16 single measurements have to be stitched together.

B. Merging the single measurements

85 x 85 mm² FoV allows for approximately 10 mm overlap between adjoining measurements. The exact position of each single measurement is well known owing to the sufficiently precise mechanical alignment of stage and WLI sensor. Thus, a compensation for x and y displacement and a rotation is not necessary. However, the height data of adjoining measurements must fit to avoid stitching artifacts which may affect NT analysis. An appropriate stitching algorithm has to compensate for basically three types of height deviations: z-offsets, linearly tilted measurements, and nonlinear deformations of single measurements.

The root cause of z-offsets and tilted measurements are offsets between the z-axes of WLI and stage. These lead to inaccuracies in the µm range, whereas amplitudes of NT features to be quantified are in the nm range. Imperfections in the optical system and nonlinearities of z-scanning of the WLI result in nonlinear deformations of the height data in the nm range.

Common stitching algorithms compensate for a rotation of single measurements but not for a deformation of each single measurement. The optimized stitching algorithm developed in this work is based on analyzing the overlap region between adjoining measurements:

Calculation of the deviation in the overlap region of two adjoining measurements.

A three dimensional polynomial of degree up to 3 is fitted to the deviation describing the height mismatch of adjoining measurements.

This function is subtracted from the height date of the measurement to be stitched. Hence the height data of the measurement to be stitched is modified to optimally fit to adjoining measurements.

The height data along the overlapping area is calculated by differently weighted height data of adjoining measurement areas in order to guarantee a smooth transition between both areas. This is done in order to suppress minor residual deviations in the overlap region.

Stitching starts at the wafer center and continues in circular order.

By applying this polynomial deformation to the individual maps, the global wafer geometry is distorted, however, at

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spatial wavelengths much higher than the upper boundary for NT, cf. Fig. 2. This is why determining bow and warp using this stitching approach is not feasible. Subsequent high pass filtering required for the NT analysis though removes such long wavelength contributions and NT results are not significantly affected.

An entire topography map after applying the stitching algorithm prior to high-pass filtering is displayed in Fig. 3. Mainly wafer bow and warp superimposed to the geometry of the wafer stage as well as to distortions caused by the stitching algorithm contribute to the image.

C. High pass filtering

Prior to NT evaluation the complete wafer map has to be high-pass filtered. This step removes global shape contributions. According to SEMI M78 [8] this is done by applying a Double Gaussian (DG) high-pass filter at filter cut-off wavelength of 20 mm, because it suppresses wafer bow and warp related signal more effectively than Single-Gaussian (SG) high-pass filtering at same cut-off wavelength. Nevertheless, in the semiconductor industry also SG with cut-off wavelength reduced to, e. g., 20/√2 mm is used for NT filtering. At such reduced cut-off longer spatial wavelength topography contributions like bow and warp can be suppressed more effectively than with SG at 20 mm cut-off, Fig. 5. A previous investigation on NT filtering by Riedel et al. [9] revealed that various alternative high-pass filtering options are available when applying EoL NT measurement tools.

Height (µm)

Fig. 3. Full 300 mm wafer topography map after applying stitching

algorithm. Such a surface topography image comprises wafer bow and warp,

stage geometry and distortions induced by the stitching algorithm.

Data treatment of the wafer surface near the edge requires special attention. For processing the near edge regions, a radial extrapolation of the measurement data beyond the physical wafer edge is implemented. Known height data within the wafer are used to fill the area outside the wafer. The approach to calculate the height data of a pixel outside the known wafer area as illustrated in Fig. 4 and might be summarized as reflection and inversion. An extrapolated pixel is calculated using the height data at the wafer edge, ze, and the height data zm of the point at the same distance to the wafer edge as the pixel to be filled along a line through the wafer center. With these two data points and (1), the height data zi of the pixel to be extrapolated is calculated:

Fig. 4. Principle of radial surface extrapolation. Extended matrix is filled by

extrapolation of measured height data of the wafer.

mei zzz 2

This approach allows for filtered wafer maps covering the full wafer without near edge artifacts known from, e. g., shrinking filter approaches or from missing data points [9][10].

The SG high-pass filter is defined as

2

1)(

c

x

c

exf

with

2ln

c denotes the cut-off wavelength of the high-pass filter

[9].

According to SEMI M78, the DG high-pass filter response is defined in the frequency domain [8]:

22

456.2228.1

21

cc

eeG

This filter response is obtained by executing the SG filter twice [9]. The normalized transmission characteristic of both the SG high-pass filter for 20 mm and 20/√2 mm cut-off wavelength, respectively, and the DG high-pass filter for cut-off wavelength of 20 mm are plotted in Fig. 5.

Wafer

Extended matrix

Measured height data z

m

Extrapolated height data z

i

Height data at wafer edge z

e

ze

zm

Wafer radius

Distance to mirror wafer edge

Wafer center

Height

zi

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Fig. 5. Comparison of transmission characteristics of a SG and a DG high

pass filter with 20 mm cut-off wave length (λc) and a SG high pass filter with 20/√2 mm cut-off wave length.

Both filters – the SG high-pass and the DG high-pass – are implemented in the equipment software and can be applied at arbitrarily selected cut-off wavelength to adjust the filter technique to the desired analysis. Furthermore, with these flexible filtering options a fair comparison to results obtained with other measurement equipment is possible.

Fig. 6. Threshold @ % area curves of ground wafers according to SEMI M43

[4]. Diameters of the circular analysis areas are 2 mm and 10 mm. Results of a wafer without dimple (Fig. 7) and with dimple (Fig. 10) are shown in top and

bottom plot, respectively.

D. Nanotopography analysis

The SEMI standard M43 [4] specifies an approach for analyzing and reporting NT. The first step after NT filtering is the determination of peak-to-valley (PV) height variation among the pixels included in a predefined analysis area. The value is assigned to the center of the analysis area. This calculation is performed while floating the analysis area pixel by pixel across the whole area of the wafer. The shape of an analysis area can be circular or square, and the size is typically between 2 x 2 mm

2 and 10 x 10 mm

2 (in case of square

analysis area). In the next step, the threshold curve is generated by plotting % area against threshold. % area is calculated from

the number of analysis areas for which the PV value exceeds the threshold value. % area data are provided as percentage of whole wafer area. Two sample threshold curves are displayed in Fig. 6. In a last step, two parameters are calculated from the threshold curves: % area at a specific threshold, and threshold at a specific % area. This approach is also known as threshold height analysis (THA).

III. DISCUSSION OF THE RESULTS ACHIEVED

A. Comparison of linear and polynomial stitching algorithm

Polynomial stitching does not that significantly deteriorate NT due to residual distortions rather it reduces more effectively stitching artifacts. This has been confirmed by applying either linear stitching or polynomial stitching of degree 3 on the same WLI height measurements. Both wafer maps were SG high-pass filtered at cut-off wavelength 20 mm. Fig. 7 clearly shows differences in residual stitching artifacts while the real wafer NT is maintained.

(a)

Height (nm)

(b)

Fig. 7. Two NT height maps of the same 300 mm wafer as-ground.

Individual images were stitched using a linear fit (a) and a polynomial fit of

degree 3 (b), respectively. Both topography maps were SG high pass filtered

at cut-off wavelength 20 mm. It is evident that polynomial fitting does not

affect the NT signal but leads to considerably less significant stitching artifacts.

B. Adjustable filter characteristics

The filter response of the DG high-pass filter is steeper than the filter response of the SG high pass filter, Fig. 5. Consequently, different wafer surface characteristics can be analyzed by applying either filter, Fig. 8.

In order to emulate an EoL NT measurement according to common industry practice [9], a SG high pass filter with

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14.1 mm cut-off wavelength was applied to a wafer map after polynomial stitching, Fig. 9 (a). The center region of the SG filtered map exhibits NT features qualitatively resembling the wafer’s NT map EoL, Fig. 9 (b).

(a) Height (nm)

(b) Height (nm)

Fig. 8. Two NT height maps of the same 300 mm wafer as-ground.

Individual images were stitched using a polynomial fit of degree 3. (a) NT

map after SG high-pass filtering; (b) NT map after DG high-pass filtering.

Both at filter cut-off wavelength 20 mm. More details of high-spatial-

frequency surface structures are visible when applying DG high pass filtering.

C. Minimized edge exclusion size

The filter algorithms with minimized filter edge effect also allow for analyzing NT features near the wafer edge. Two NT features can be seen in the NT map of a 300 mm wafer as-ground at edge exclusion less than 1 mm, Fig. 10, – a dimple and a circumferential feature close to the wafer edge.

D. Repeatability of nanotopography analysis

A complete gauge repeatability and reproducibility (GRR) study has been performed to determine the NT measurement capability of the measurement system. A cassette comprising 25 wafers with different surface qualities (from as-ground to polished) was measured on three days two times per day with raw data saving. Since the measurement repeatability for all surface types is comparable, the measurement of this limited number per wafer type gives significant results.

GRR figures were determined by reprocessing raw data with appropriate NT evaluation recipes. This allows for comparison of different filter and NT analysis settings. As an example, we applied DG high-pass filtering with 20 mm cut-off and determined THA values for 50 % area. Variability data for the 10 x 10 mm2

window size are shown in Fig. 11,

resulting in = 0.32 nm. GRRs for smaller window sizes are even lower [11].

(a) Height (nm)

(b)

Fig. 9. NT map of a 300 mm wafer as-ground after polynomial stitching and

SG filtering at cut-off wavelength 20/√2 mm (a). For comparison the wafer’s

NT map end-of-line using KLA-Tencor’s WaferSight 2 (b). NT features

obtained end-of-line, e. g., in the wafer center can already be sensed on the

wafer as-ground.

Height (nm)

Fig. 10. NT wafer map of a ground 300 mm wafer with a dimple and NT

features close to the wafer edge. Edge exclusion is < 1 mm.

20 nm

-20 nm

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Repeatability figures for smooth and rough surfaces are in the same order of magnitude. Different products separate well regarding characteristic THA values.

Fig. 11. Variability chart of THA at 50 % area for 10 x 10 mm² analysis

window using DG high pass filtering.

IV. CONCLUSION

Topography maps of 300 mm silicon wafer surfaces after mechanical process steps, i. e., with rough surface have been successfully recorded using white light interferometry. Applying optimized stitching algorithms combined with data extrapolation near the wafer edge allows for generating a complete 300 mm wafer topography map from the 16 individual small maps recorded. It is possible to obtain NT height maps upon high-pass filtering exhibiting only minor impact from residual measurement artifacts. The implementation of NT analysis according to SEMI M43 enables characterization of NT early in wafer manufacturing

stages and identically to established EoL measurement systems. This facilitates continuous improvement of relevant wafering, grinding or lapping processes.

ACKNOWLEDGMENT

This R&D work has been performed within the framework of the European project SEAL (Contract Number: INFSO-ICT-257379). The consortium acknowledges the European Commission for the support. Additionally, the authors acknowledge Dr. Andreas Nutsch for his preliminary research in surface extrapolation combined with NT filtering.

REFERENCES

[1] ITRS – “International Technology Roadmap for Semiconductors”, 2011

[2] Ravi, K. V.; Future Fab Report, Volume 7, Page 207, 1999

[3] Paik, Ungyu; Park, Jea-Gun; “Nanoparticle Engineering for Chemical-Mechanical Planarization”; CRC Press; Boca Raton; 2009

[4] SEMI; “Guide for reporting wafer nanotopography”; SEMI Standard M43-1109; 2009

[5] Riedel, Frank; Gerber, H.-A.; Wagner, P.; „Impact of filtering on nanotopography measurement of 300 mm silicon wafers“;Materials Science in Semiconductor Processing, Volume 5, Issues 4–5, August–October 2002, Pages 465–472

[6] Nutsch, A.; Bucourt, S.; Grandin, T.; Lazareva, I.; Pfitzner L.; “Wave Front Sensor for Highly Accurate Characterization of Flatness on Wafer Surfaces”; AIP Conference Proceedings Vol. 1173; Melville, NY 2009

[7] Hecht, Eugene; “Optics”; Addison-Wesley; 2012

[8] SEMI; “Guide for determining nanotopography of unpatterned silicon wafers for the 130 nm to 22 nm generations in high volume manufacturing”; SEMI Standard M78-1110; 2010

[9] Riedel, F.; Gerber, H.-A.; Wagner, P.; “Double Gaussian Filters”; International Advanced Wafer Geometry Task Force SEMICON Europa, München 2004

[10] Muralikrishnan, Bala; Raja, Jay; “Computational Surface and Roundness Metrology”; Springer; London; 2009

[11] Tröger et al., “Automated Tool for Measuring Nanotopography of 300 mm Wafers at Early Stages of Wafer Production” Proceedings of the 11th ISMTII; Aachen, Germany; 2013; to be published

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