A Current Sensing Circuit Using Current-Voltage Conversion for PMOS-Based LDO Regulators

Ho Quang Tay, Vo Tuan Nam, Nguyen Hoang Duc and Bui Ngoc Chau IC Design Research & Education Center (ICDREC)

Vietnam National University – Hochiminh City (VNU HCM), Vietnam Email: tay.hoquang@icdrec.edu.vn

Abstract—In this paper, a standalone output current

sensing module for CMOS low dropout linear voltage (LDO) regulator with PMOS as pass device is proposed. The main purpose of current sensing is to create an over-current protection or to limit the output current value in certain applications. Based on I-V conversion in which the supply voltage varies from 2.7V – 4.2V, the current clamp value varies from 178mA to 270mA in the case of 200mA load limiting. The proposal has been successfully fabricated using a CMOS technology, and verified through the correct operation of a power management prototype chip.

Index term — LDO, current sensing, current limiter, over-current protection, current-voltage conversion.

I. INTRODUCTION

The system on chip (SoC) industry has been rapidly developing. The essential requirements of SoCs are low cost, high integrability and small size. For these reasons, mixed - signal SoCs have recently attracted more and more attention. Power management function in such architectures is very important. The power management block almost takes a basic part of a chip, even a system. The main function of power management is to supply power for the whole system. In a high-cost system, smart functions such as over-load protection, over-heat protection and stabilization are essential features, and these should be considered carefully to guarantee the correct operation of the system.

Because of advantages such as low noise, low dropout voltage and without external components requirement, LDO regulators have been developed in recent years. It is considered as a main part of power management device. There are two topologies for an LDO in which an NMOS or a PMOS is used as pass device, respectively. NMOS LDO has some advantages such as faster response and smaller area. On the other hand, PMOS type has lower output resistance and lower dropout voltage when pass device operates in the active region. Thus, the PMOS type is dominant in LDO designs.

Current sensing is a necessary feature for a power management to implement the over-current protection. It is used to prevent the output current from shooting over a threshold value, thus protecting the loads and the devices. There are some topologies of the current sensing for switching regulator [1, 2], or LDO in which NMOS is used as pass device [3].

The convenient approach of the current limiter is to use current mirrors to monitor output currents, also called proportional technique. However, this architecture is complicated and hard to integrate into a chip. Another method, the scaled down technique, was proposed in [3, 4]. In these methods, the current sensing mechanism is based on the output current, using a resistor and a MOS

transistor. Scaled-down devices cause incorrect threshold current, thus they need an internal compensation. As the result, this makes the system more complicated. Moreover, by using a resistance, the process variation can increase the limit current precision, [5].

In this paper, a proposed current limiter used in LDO regulator employing PMOS as the pass device is presented. The proposed current sensing is a resistor-less architecture in which a current-voltage conversion (I-V conversion) is used. The I-V conversion can be adjusted to adapt different current limitation values.

In this paper, the circuit design is described in section 2. Section 3 shows the simulation results and experimental results measured from the prototyped chip.

II. STRUCTURE OF CURRENT SENSING

The Fig. 1 shows a typical LDO regulator using PMOS

as the pass device. In the architecture, Vref is a bandgap voltage reference integrated inside the chip or comes from an external circuit. The Vref value usually is stable against supply voltage and temperature.

The LDO regulator also consists of an OPAMP working as an error amplifier (EA). The gain of EA must be large and independent of the supply voltage variations.

The two resistors (R1 and R2) in LDO form a feedback network. They are very large for low quiescent current, and also are used to determine the output voltage value (Vout).

Pass device is employed in a common-source PMOS configuration. Its area is proportional to the output current. The simplified output voltage and output current equations of a PMOS-based LDO regulator are described by (1) and (2).

Fig. 1 A typical LDO regulator.

978-1-4673-3033-6/10/$26.00 ©2012 IEEE

2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, KotaKinabalu Malaysia

1

refout VRR

V +=2

11 (1)

2)(2 tpsg

oxppasssd VV

LWC

II +==μ

(2)

where μp, Cox, W, L, Vsg, and Vtp are the mobility of holes, the gate capacitance per unit area, the width, the length, the source - gate voltage, and the threshold voltage of the pass transistor, respectively.

Since the pass device (PMOS) operates in saturation region, from equation (2) the relationship between Vsg and Isd (drain-source current) is rewritten by equation (3).

tp

oxp

sdginsg V

LWC

IVVV −=−=μ

2

tpp

sd VTI −= 2

(3)

For a given LDO, the Tp and Vtp are constant

parameters. With, Tp = L

WCoxpμ .

This equation shows that the difference voltage between Vin (supply voltage) and Vg depends on Isd. When the output current reaches a certain limited value, the difference voltage is fixed at a threshold voltage value (Va in Fig. 2). This threshold voltage can be calculated by hand or by simulators.

To sense the output current, a circuit whose output

voltage is linear with Vin is required. By this manner, the difference voltage between input and output is independent of the input voltage value. It means that Va is changed following to Vin to keep the below relation:

constVV ain =− (4)

In order to satisfy the Eq. 4, the proposed current sensing circuit is depicted in Fig. 2. It consists of only three transistors. Transistor MP3 in this architecture operates as a current source. As a result, the flowing current through all the transistors (Ibias) is stable. Thus, drain-source voltage of transistor MP1 (Vds1) is fixed at a constant value as requested in Eq. 4.

On the other way, we have:

constVVV ainds =−=1 (5)

As can be seen in the equations (3) and (5), the clamp current is created by comparing Vg at the pass device’s gate terminal in Fig. 1 and Va (threshold voltage) in Fig. 2. The mechanism is shown in Fig. 3.

An important issue should be considered in Fig. 2 is

how to create the bias voltage. Such the stable voltage generates the bias current (Ibias) which is independent of temperature. Fortunately, this issue can be resolved by using the certain Vref mentioned above. Conventionally, LDO regulator has an inside bandgap to generate the requested bias voltage value.

III. SIMULATION AND EXPERIMENTAL RESULTS

A. Simulation Results

The operation of LDO was simulated in the following condition:

- Supply voltage: 2.8V – 4.2V (Li-ion battery value). - Output voltage: 2.5V. - Output current: 0mA, 200mA and 500mA.

Fig. 4 shows that the difference voltage between Vin and Vg simulated with various loads (no load, 200mA and 500mA) is a nearly constant value. This result verifies the correct operation as expected in Eq. 3.

Fig. 4 The characteristic of Vg with respect to Vin and Ipass.

Fig. 3 The Over current flag structure.

Fig. 2 The proposed current sensing circuit.

2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, KotaKinabalu Malaysia

2

Fig. 5 shows the results in detail. Dorder effects [6], the difference voltanearly constant.

The second-order effects can increasing the bias current. Unfortuincrease the power dissipation. Thertrade-off between power dissipation anthreshold current. In order to save powchip is designed to work with the biaMoreover, the total current dissipaticircuit and the comparator is 5uA.

It also should be noted that the difference voltage causes a certain racurrent. This issue was described in [3].

The simulation results in Fig. 6 illcurrent range. The supply voltage var4.2V, and the clamp current range is seto 270mA, respectively.

Fig. 6 The clamp current range according suppl

Fig. 5 The difference voltage of Vin and Vg.

Due to the second-age is actually a

be reduced by

unately, this will refore, there is a nd accuracy of the wer, the fabricated as current of 1uA. ion of the sense

variation of the ange of threshold .

lustrate the clamp ries from 2.8V to et at from 178mA

B. Experimental Results

The proposed current limitepower management prototypfabricated in a 0.35um process

When the current load reacover-current flag of the compavoltage variation in this meas1501T equipment. The Fig. 7 scurrent measurements in respec

As expected in simulationresults of the threshold curren281mA according to the supply4.2V, respectively. The range vresults. Table 1 shows some adresults between the proposed circuit.

TABL

THE COMPARATION OF PCONVENTIONA

Name

Architecture Scaled

Voltage range (V)

Deviation of current clamp

Quiescent current (uA)

IV. CONCL

Based on I-V conversionsensing circuit for PMOS-bpresented. As simulated, the circuit has some advantages. Tin a PMOS LDO for widmanagement chips. Due to thprocess variation on the accurminimized. By changing the acurrent, the threshold currentvarious high-load current requir

Regarding the desired threthe supply voltage varies fromcurrent will change from 178m

Fig. 7 The threshold current range.

ly voltage.

er is implemented in the low pe chip. The chip was [7].

hes the threshold current, an

arator will be set. The supply surement is created by PS-shows the result of threshold ct to supply voltage.

n results, the measurement nt clamp is from 172mA to y voltage variation of 2.8V to values are close to simulation dvantages when compare the circuit and the conventional

LE I.

PROPOSED CIRCUIT TO AL CIRCUIT

[3] & [8] This work

d-down device I-V Conversion

1.5 –> 6 2.8 –> 4.2

70 (%) 50 (%)

65 5

LUSION.

n, a novel CMOS current based LDO regulators is resistor-less current sensing

The circuit can be integrated de applications in power e resistor-less, the effect of racy of the current clamp is area of the diodes and bias t can be adjusted to meet rements.

eshold current of 200mA, if m 2.8V to 4.2V, the clamp

mA to 270mA, respectively.

2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, KotaKinabalu Malaysia

3

The prototype chips were designed and fabricated through MOSIS educational program. The results measured from the prototype chip were verified the correct operation.

To reduce the range of the clamp current, it is necessary to increase the bias current flowing through all transistors. This issue will be described in detail in the next publication.

ACKNOWLEDGEMENT

Our first and deepest thanks to Ministry of Science and Technology, Vietnam and VNU HCM for the grant in the form of a state-level research project with Code number: DAKHCN.2011/DT-03

The authors wish to thank Prof. Dang Luong Mo, advisor of VNU-HCM for their helpful comments in revising the manuscript. We also would like to thank Mr. Ngo Duc Hoang, ICDREC director, for his favorable regarding completion of the paper.

REFERENCES

[1] Leung, C., Mok, P. and Leung, K., “A 1.2-V Buck Converter with a Novel On-Chip Low-Voltage Current-Sensing Scheme”, Proc. of IEEE ISCAS, Vol.5, pp.824-827, 2004.

[2] Forghani-Zadeh, H. P. and Rincón-Mora, G. A., “Current-Sensing Techniques for DC-DC Converters”, Proc. of IEEE MWSCAS, pp. 577-580, Vol. 2, Aug. 2002.

[3] Jader A. De Lima and Wallace A. Pimenta, “A Current Limiter for LDO Regulators with Internal compensation for Process and Temperature Variations”, proc. of ISCAS, pp. 2238-2241, 18-21 May 2008.

[4] Lin Chuan and Feng Quan-yuan, “Design of Current Limiting Circuit in Low Dropout Linear Voltage Regulator”, proc. of Asia-Pacific Microwave Conference (APMC), p. 4, Vol. 2, 2005.

[5] S. Heng, W. C. Tung and C. K. Pham, "New design method of low power over current protection circuit for low dropout regulator" International Symposium on VLSI Design, Automation and Test, 2009 (VLSI-DAT '09). pp.47-51, 2009.

[6] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, ed. Mc Graw-Hill, pp. 23-27, 2000.

[7] Ho Quang Tay and Ngo Duc Hoang, “A Low Dropout Linear Voltage Regulator Chip, the TH7150”, Science and Technology Development Journal (ISSN 1859-0128), vol. 12, no. 16, pp.51 – 62, Dec. 2009.

[8] Jader A. De Lima and Wallace A. Pimenta, A current limiter for DC/DC regulators with compensation against process and temperature variations, analog integrated circuits and signal proc., DOI: 10.1007/s10470-009-9394-7, Volume 63, Number 2 (2010), 217-231.

2012 International Symposium on Computer Applications and Industrial Electronics (ISCAIE 2012), December 3-4, 2012, KotaKinabalu Malaysia

4