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IC Yield, Reliability and Prognostic using Nanoscale

Test Structures

Hans ManhaeveCEO

Q-Star Testhans.manhaeve@qstar.be

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Overview

• Setting the scene• Yield: the past, today & tomorrow• Yield & Reliability: The need for Prognostics• Concept of Prognostics• Prognostics and Yield• Conclusions

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The Changing LandscapeSource: Intel

1K4K

64K256K

1M

16M4M

64M

40048080

808680286

i386™i486™

Pentium®Pentium® II

Pentium® III

256M 512M

Pentium® 4Itanium™

1G 2G 4G

128M

MemoryMicroprocessor

1965 Actual Data

1960 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010

16K

1975 ProjectionMOS Arrays

TransistorsPer Die

108

107

106

105

104

103

102

101

100

109

1010

Moore’s OriginalPrediction!

40+ Years of Moore’s Law

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The Changing LandscapeInnovation Enabled Technology Pipeline

Tri-Gate

S

G

D

III-V

S

Carbon Nanotube FET

50 nm35 nm

SiGe S/DStrained Silicon

SiGe S/D2nd generation

Strained Silicon

20 nm 10 nm

5 nm

Nanowire

Metal Gate

High-k

High-kMetal gate

Source: Intel

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The Changing Landscape

Changing Shape of Defects

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The Changing LandscapeDealing with variance and fluctuations

Parameters change across dies and across wafer

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The Need for Test

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The Need for Test

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The Need for Test

• But we still need to test every single transistor

• Test is an important factor of IC manufacturing costs (15 50 ….%)

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Find The Defect

Badwater, Death Valley‐85.5m (‐282ft)

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Find the Defect

Butler, ITC07Madge, ITC04

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Yield – From Past to Present• Yield has a simple definition

• Challenge lies in separating “good” from “bad”

chipstotalchipsgoodYield =

x x

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Yield - Ambiguity

GEORGE THOROGOOD

BAD TO THE BONE

partsallfailuresItypeescapestestpartsgoodYieldMeasured −+

=

Competing definitions of “good”Ideal: works in customer’s application→Can’t measure this until it’s too late!

Is high leakage from a defect or fast transistors?Most chips work at 0.7V, this one doesn’tHow complete are these tests?

Eventually need to agree on “passes the tests we apply”Result: Test can’t be ignored when discussing yield!

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Yield – From Past to PresentHistorically, testing was functional

Does the device do what it is supposed to?Function primarily defined logicallyYield related to function

Next, structural tests were developedIs every circuit structure (e.g. gate) present and working?Coverage metrics are logical (stuck-at fault coverage)Yield related to structure

Defect-oriented testing starts with defectsWhat could go wrong with this device?If it went wrong, what would change about the device?Any measurable behavior could be affected, not just function→ timing, current, voltage, temperature dependence

Yield related to absence of defects

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Yield & ReliabilitySemiconductor evolution enables further integration

Transistors are nearly for freeNew processes are used for mass production long before they are mature

Systematic and random defectsReliability concerns

Increasing device complexityThe “embedded” worldAnalog – Digital – Memory – Software

Market demands for cheaper and better electronicsMarket demands for RELIABLE electronics

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Yield & Reliability• Lifetime reliability becomes a serious concern

Useful life

Failu

re ra

te

Infantmortality

180nm130nm90nm

~ 7 year[T. M. Mak]

< 7 year ~ 10 year

Time

WearoutFailure mechanisms

ElectromigrationNBTITDDB

Reliability-related factors

TemperatureSupply voltageFrequency

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Yield & ReliabilityFailure Mode Physics System Effect

NBTI (PMOS)

• Negative Vt shift• Slower speed

• Timing Faults in Processors• Resettable – but increasing severity over time

TDDB

Soft Breakdown:• Slower speed• Weakened gate oxide• Increased leakage current

• Increased ESD Vulnerability• Non‐resettable timing faults

Hard Breakdown/Punch‐through • Catastrophic Short

Hot Carrier (NMOS)

• Positive Vt shift• Change in sub‐threshold swing

• Increased Off‐state power• Increased current draw• Decreased data retention time in DRAM

Metal Migration

• Higher resistance in Via connections• Open circuits

• Catastrophic Open

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Yield & Reliability• Semiconductor processing

always yield a distribution of parameter values

• Minimum geometries have larger fluctuations

• Smaller feature size & lower voltages increase the impact of variation of transistor properties on chip performance and yield

• Foundry-supplied Process Design Kit (PDK) may not give sufficiently accurate data for critical design parameters

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Yield & Reliability -- Prognostics

• Ways to address Nanoscale design reliability

• Use additional design margin– Increased power

consumption– Impacts overall

circuit performance

• Use degradation monitors– Realtime operating

embedded sensors– Actual State of Health

for critical paths– Early warning of

impending failure

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Prognostics Concept

Prognostic Cell

Host Circuit

Prognostic cell representation on a wafer (a) and a single die (b)

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Prognostics Concept

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Prognostics Concept

Threshold Trigger Points are selectable

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Use of Prognostics

Prognostic Advantages• Safety benefit if actual

usage is more severe than predicted (see the red region, T1).

• Service life can be extended beyond normal replacement time if the actual usage severity is known (see the green region, T2).

MTBF statistical expected life

T1 T2

CBM enables replacement only upon evidence of need

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PDK vs Prognostics• Process Design Kit (PDK) may not be accurate for

particular batch/wafer/die/package• PDK may not have data for particular application

(e.g., temperature)• PDK may not be representative of particular

biasing schemes (e.g., MOSFET matching differs for strong inversion and subthreshold)

• Data is not placement-specific (directional/wafer angle)

• PDK may not give values to insert into random parameter fluctuation simulations

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Prognostic Advantages

DLPM

Scribe LineTransistor

DLPM: test structure on the host dieo Scribe line transistor requires additional test 

fixture

DLPM testing: post‐packagingo Scribe line transistors are lost when wafers 

are sliced

DLPM eanbles quick production testo Scribe line transistor requires delicate probe 

measurement: inaccurate and time‐consuming

DLPM measures parameters that are useful to the designero Scribe line transistor may not directly 

measure important parameters – additional characterization is required

Data is application‐specifico DUTs are extracted from the host designo PDK models may not provide accurate predictions

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Prognostics - Example

PDKChekimbedded in the ADC 

Example of GDSII Layout for the Ridgetop 14‐bit Pipeline ADC

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Prognostics - ExampleRbodysh

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

2

2.5

400 450 500 550 600

Rbodysh（Ω/□）

σ

PDKChek1

PDKChek2

PDKChek3

PDKChek4

PDKChek5Scribe‐line

Scribe‐line Test

Scribe-line Process Control Monitor (PCM) structures from foundry may not directly measure important parameters

High performance designs need DLPM results that accurately track critical paths using Host circuits well structures

Scribe‐line results not in tight Host circuit distribution

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Prognostics & Yield

Parameter Extraction

PDKChek Process Variation

PDK, Models, Variation data

Predicted Yield

Measured Yield

Simulation with process variation

Need Improvement?

Foundry

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Prognostics & Yield - Example

-3

-2

-1

0

1

2

3

-40 -30 -20 -10 0 10 20 30 40σ

ΔVTH（mV）

NMOS (type6) @ PDK1

-3

-2

-1

0

1

2

3

-40 -30 -20 -10 0 10 20 30 40

σ

ΔVTH（mV）

NMOS (type6) @ PDK1

1) Characterize threshold voltage shift in matched pair transistors using PDKChek

2) Characterize yield in flash ADC for given linearity targets (due to comparator offset)

39 dB SINAD yield 90%

45 dB SINAD yield 75%

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Prognostics Solutions Overview

• InstaBIST™ Test Cores– SJ‐BIST BGA Solder Joint Built‐in Test– RingDown™ Power Supply Test– ADC‐BIST Self‐testing Data Converters

• Sentinel Silicon™LibraryReliability/ Prognostics Monitor Cores– TDDB– NBTI– HCI– Metal Migration

• InstaCell™ Mixed Signal Cores– ADC – Analog to Digital Converter– DAC – Digital to Analog Converter– Op Amps and Comparators

• nanoDFM™ Product LineIndependent Foundry Die‐Level Process Monitors– PDKChek® combines

– ∆VT mismatch– ∆I(on) mismatch– ∆R mismatch– ∆C mismatch

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Prognostics Solutions OverviewThird-party

System-level Diagnostic Module(MTBF models)

Hierarchical system modelFailure modes

Constraints

(e.g., safety, reliability, maintainability, cost)

Prognostic sensor attributes- Deployed sensors

(e.g., power supply, interconnect)- Sensor parameters

Prognostic analysis- Precursor signatures

- Remaining Useful Life (RUL)

- State of Health (SOH)

- Enhanced fault dictionary

- Additional graphical displays

Ridgetop Group

Sentinel NetworkTM

Ridgetop interface

Fault coverageDiagnostic metrics

FMEA

Diagnostic test programs

ARULETM Reasoner Calibration

Prognosticcandidates

Prognostic events

Test definition data

SensorsSensors

Hardware MTBF models

Optimization Feedback Loop

Prognostics “wrap around” existing MTBF-based system models

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Conclusions

• Test is critical to identify good and bad devices.

• Although yield has a simple definition, the perspective of yield can be quite different.

• Yields and test are sometimes at odds with each other, but prognostics can help to identify the best compromise.

• Prognostic sensors and test structures are an effective way to assure and improve IC yields.

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About Q-Star Test.• Small Business:

– Incorporated 2000– Headquartered in Brugge, Belgium– DFT & Test solution Industry leader– Prime expert on Current measurement

solutions and test methodologies

• Who We Serve:– Q-Star Test provides innovation in DFT, Test,

Measurement and Prognostics for a wide range of commercial customers.

AutomotiveMedicalTelecommunicationConsumerIndustry PartnersAcademia

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Consulting and Training Services related to Design for Test (DFT) and Test Optimization.Advanced (Current) Measurement Solutions applicable to digital, analog, mixed-signal and RF devices and systemsEngineering Services supporting design, prototyping, validation and test of electronic circuits and systemsTest Engineering Services supporting test program development and test program optimizationElectronic Prognostic Solutions enabling to better monitor healthiness of electronic circuits and systems and to make reliable (remaining) lifetime predictions.

Q-Star Test – Products & Services

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About Q-Star TestMake use of Q-Star’s solutions and :• Reduce your test efforts, test costs and test escape risks• Reduce your production test time without sacrificing quality• Increase your engineering and failure analysis productivity• Improve your product quality and monitor process quality• Extend the use of IDDQ testing into the Deep-Submicron and

Nanotechnology arena• Implement analog IDD, IDDT and ISSQ testing on your

production test floor• Have a guarantee that the device’s operation conditions are

maintained

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About Q-Star TestQ-Star provides solutions to:

– Reduce IC test costs– Improve product quality and reliability– Enable advanced high-speed high-resolution IDDX

test and measurement solutions.

Q-Star’s measurement solutions provide highly repeatable results and allow increased product quality while shortening test time.

Q-Star offers Design for Test (DFT) and test optimization consulting services.

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Q-Star Test MissionOur Mission is:

To help our customers build better electronic products at lower cost

This translates to:

To provide Innovative Solutions Enabling: Test Time (Cost) Reduction and Test Data Quality

Improvement Combined with Product Quality and Reliability Improvement.

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For More Information…Q-Star Test nv

Lieven Bauwensstraat 20B-8200 Brugge, Belgium

Tel: +32 50 319273, Fax: +32 50 312350

USAQ-Star Test / Ridgetop Group Inc.

6595 North Oracle RdTucson, Arizona 85704, USA

Tel: 520-742-3300

info@qstar.be or sales@qstar.behttp://www.QStar.be