IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019 1595

Hybrid SVPWM Scheme to Minimize theCommon-Mode Voltage Frequency and Amplitude

in Voltage Source Inverter DrivesAmeer Janabi , Student Member, IEEE, and Bingsen Wang, Senior Member, IEEE

Abstract—In this paper, a hybrid space vector pulsewidth mod-ulation synthesis is proposed to lower the frequency and ampli-tude of the common-mode voltage (CMV). The conventional spacevector pulsewidth modulation (SVPWM) techniques for invertersgenerate a high-frequency CMV. The CMV causes significant bear-ing current flowing through the path to the ground and leads topremature bearing failure, especially in high switching frequencydrive systems. Furthermore, previously proposed CMV reductionstudies focus on the reduction of CMV amplitude, leaving a high-frequency CMV. The proposed control algorithm divides each sec-tor in the space vector hexagon into three segments based on themodulation index and the angle of the reference voltage vector.In each segment, the space vectors that produce minimal CMVare selected to synthesize the reference voltage vector. A fair com-parison with the conventional CMV reduction methods is made bycomparing the CMV characteristics, harmonic distortion factor, dccurrent ripple, and the switching losses for each method. Both sim-ulation and experimental results have validated the effectivenessof the proposed approach.

Index Terms—Commom-mode voltage (CMV), dc–ac adjustablefrequency drive systems, space vector pulsewidth modulation(SVPWM).

I. INTRODUCTION

VOLTAGE source inverters (VSIs) are widely used in motordrive applications. The use of VSI ranges from high power

(e.g., wind turbines) to medium power (e.g., electric and hybridelectric vehicles). Ever since the invention of the insulated gatebipolar transistor (IGBT), increasing the switching frequencyof the power converter has been a trend due to the reductionof the footprint and the increase of power density [1], [2]. Re-cent development of wide bandgap devices has equipped thepower switches with even faster switching speed [3]. However,the increase in the switching frequency has generated severalunwanted consequences, one of which is the high-frequencycommon-mode voltage (CMV) [4], [6]. The high-frequencyCMV can cause electromagnetic interference that adversely af-

Manuscript received December 26, 2017; revised March 23, 2018; acceptedApril 24, 2018. Date of publication May 7, 2018; date of current version Decem-ber 7, 2018. Recommended for publication by Associate Editor D. O. Neacsu.(Corresponding author: Ameer Janabi.)

The authors are with the Department of Electrical and Computer Engineer-ing, Michigan State University, East Lansing, MI 48824 USA (e-mail:, jan-abiam@egr.msu.edu; bingsen@egr.msu.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2018.2834409

fects the other components of the system [7]. The induced over-voltage stresses the winding insulation of the drives and canalso increase the shaft current [8]. In particular, the shaft cur-rent is the result of the fluctuation of the CMV, which is strictlyrelated to the sequence of the inverter switching states [9]. Sev-eral studies presented in the literature discussed the reductionof CMV effects. They can be classified into hardware solutionsand algorithmic solutions. The hardware ones require either in-creasing the number of switches [10]–[15], passive components[16]–[25], or both [26], [27]. The study in this paper is mostlyrelated to the algorithmic approaches that require no additionalhardware.

The early attempt to reduce the CMV proposed in [9] usesonly the odd or only the even voltage vectors. This approachresults in dc CMV. However, the linear region in this ap-proach is reduced to MI ≤ 4

3√

3. Later, a number of CMV re-

duction methods were proposed such as the active zero-statePWM (AZSPWM1-2 and AZSPWM3), remote state PWM(RSPWM1, RSPWM2, and RSPWM3), and near-state PWM(NSPWM) [28]–[31]. In each one, several active voltage vec-tors are utilized to meet the voltage second requirements andavoid using the zero vectors. The nonzero switching vectorsgenerate lower magnitude CMV but the conventional space vec-tor PWM uses zero vectors as it helps in reducing the THD[32], [35]. The latter methods utilize all of the linear region (ex-cept for NSPWM), which leaves the high frequency of the CMVremaining an issue. The high common-mode dv

dt causes electricdischarge machining (EDM) across the bearing races. Further-more, the CMV reduction methods assume ideal switches andfail when nonlinearities such as the deadtime and line–line volt-age reversal are considered [34].

On the other hand, to further improve the performance ofCMV reduction methods, combined approaches are used indifferent operating conditions. For instance, to make full useof NSPWM, another CMV reduction method is activated atlow modulation index such as AZSPWM1 [36]. The modifiedSVPWM presented in [37] combines both RSPWM and regu-lar SVPWM at low- and high-modulation index, respectively.This method makes a tradeoff between dc-link voltage utiliza-tion and common-mode current (CMC) reduction. However, thedeadtime effect causes CMV amplitude to reach half of dc-linkvoltage [38]–[40].

In this paper, a hybrid approach for minimizing the amplitudeand the frequency of the CMV is proposed. The control concept

0885-8993 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications standards/publications/rights/index.html for more information.

1596 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

Fig. 1. Three-phase VSI.

TABLE IFEASIBLE VOLTAGE VECTORS AND THE CORRESPONDING DMV AND CMV

is based on dividing the space vector hexagon into various seg-ments and synthesizing the reference voltage vector by usingvectors that correspond to a minimal CMV. Full treatment ofthe deadtime effect is presented. The proposed method avoidsany CMV peaks or unwanted variations during the deadtimeintervals.

The rest of the paper is organized as follows. In Section II,the regular SVPWM is briefly revisited. The proposed controlmethod is presented in Section III. Deadtime effect is presentedin Section IV. A complete solution to the deadtime effect ispresented in Section V. Performance analyses including CMVcharacteristics, harmonic distortion factor (HDF), dc currentripple, and the switching losses are presented in Section VI.Hardware results and conclusion are presented in Sections VIIand VIII, respectively.

II. CONVENTIONAL SVPWM

For the two-level, three-phase VSI shown in Fig. 1, the refer-ence value of the inverter output voltage can be represented bythe following space vector:

Vref =23(va + vbe

j 2 π3 + vce

−j 2 π3

)(1)

where va , vb , and vc are the three phase voltages. Since thedc-link should not be shorted, each phase voltage can only attaineither Vdc or −Vdc. This also restricts the feasible switchingstates to only eight states. The eight converter states as well asthe corresponding differential-mode voltage (DMV) and CMVare shown in Table I. The linear combination of the possibleeight vectors span a hexagonal area, as shown in Fig. 2.

Fig. 2. Eight stationary vectors in the complex plane for a VSI.

The reference vector Vref is synthesized at each samplingperiod Ts using the two adjacent active vectors and the zerovectors. This leads to six equal sectors. Because the circular tra-jectory of Vref in the complex plane corresponds to a sinusoidalthree-phase voltage, the maximum achievable sinusoidal outputvoltage amplitude is ≤ 2√

3Vdc. Therefore, the modulation index

MI can be defined as the per unit output voltage vector usingVdc as the base voltage MI ∈ [0, 2√

3].

For instance, when the trajectory of the reference voltage Vref

is passing through the first sector where θ ∈ [0, π3 ], the following

volt-seconds equality holds:

TsVref = tv1V(1,0,0) + tv2V(1,1,0) + tv0V(0,0,0) + tv7V(1,1,1)(2)

Ts = tv1 + tv2 + tv0 + tv7 . (3)

By equating the real part and the imaginary part in (2), thefollowing dwell times can be obtained:

tv1 =34TsMI[cos(θ) − sin(θ)] (4)

tv2 =√

32

TsMI sin(θ) (5)

tv0 = tv7 = Ts − tv1 − tv2 . (6)

The same rules can be applied for calculating the dwell timesof the vectors for sectors 2–6 if the following modified θk is used:

θk = θ − (k − 1)π

3(7)

where k is the number of the sector in which the Vref resides.

III. HYBRID SPACE VECTOR PULSEWITH

MODULATION SYNTHESIS

The method of hybrid space vector pulsewidth modulationsynthesis (HSVPWMS) further subdivides each sector into threesegments. In each segment, a group of active voltage vectors isselected to match the output reference volt-seconds and achieveminimal CMV amplitude and frequency. The location of thereference voltage vector can be defined in correspondence tothe modulation index MI and its angle θ.

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1597

Fig. 3. Sector I is divided into three segments. (a) Odd triangle. (b) Odd–even triangle. (c) Even triangle.

Fig. 4. Vector synthesis for HSVPWM I. (a) Odd triangle. (b) Odd–even triangle. (c) Even triangle.

The total eighteen segments of the space vector hexagon areobtained based on their corresponding CMV. They can be cate-gorized into the following:

1) six odd segments that result in CMV −Vdc3 ;

2) six even segments that result in CMV Vdc3 ;

3) six odd–even segments that result in CMV ±Vdc3 .

To understand the navigation of the reference voltage throughthose segments, the authors thoroughly explain the synthesis ofthe reference voltage vector via the first sector θ ∈ [0, π

3 ) withreference to Fig. 3.

The sector includes three segments (triangles). The refer-ence vector in the bottom triangle (odd-triangle) can be synthe-sized using only the odd vectors {V(1,0,0) ,V(0,1,0) ,V(0,0,1)},as shown in Fig. 3(a). The reference vector in the upperrighttriangle (odd–even triangle) can be synthesized using the oddand even vectors {V(1,0,0) ,V(1,1,0) , ...,V(1,0,1)}, as shownin Fig. 3(b). The reference vector in the upperleft triangle(even triangle) can be synthesized using only the even vectors{V(1,1,0) ,V(0,1,1) ,V(1,0,1)}, as shown in Fig. 3(c).

The line dividing the odd triangle from the odd–even trianglecan be parameterized as follows:

edge =2√3

(1 − θ

π/6

). (8)

When the MI is larger than the value of edge, the referencevoltage vector is in the odd triangle. Similar logic can be fol-lowed to identify all other segments.

The synthesis of the reference voltage vector in the odd tri-angle and even triangle is unique, whereas the synthesis for thereference voltage vector in the odd–even triangle can be real-ized using different groups of vectors. The groups are classifiedinto four groups with each group producing similar harmoniccontent and switching losses. The four groups are delineated inthe following sections.

A. HSVPWMS IThe voltage reference vector passing through the odd–even

triangles can be synthesized by using the two adjacent voltagevectors and the two voltage vectors of the neighboring statesto match the output and reference volt-seconds, as shown inFig. 4(b). For the odd triangle shown in Fig. 4(a), the time inter-vals in which the inverter states {(V(1,0,0) ,V(0,1,0) ,V(0,0,1)}are applied can be calculated by solving the following algebraicequations:

VrefTs = V(1,0,0)tv1 + V(0,1,0)tv3 + V(0,0,1)tv5 (9)

Ts = tv1 + tv3 + tv5 . (10)

1598 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

TABLE IIVECTOR COMBINATIONS USED IN THE THREE SEGMENTS OF EACH SECTOR USING HSVPWMS I

This leads to the following dwell times:

tv1 =Ts

3+

TsMI cos(θ)2

(11)

tv3 =Ts

3− TsMI cos(θ)

4+

√3TsMI sin(θ)

4(12)

tv5 =Ts

3− TsMI cos(θ)

4−

√3TsMI sin(θ)

4. (13)

For the odd–even triangle shown in Fig. 4(b), the timeintervals in which the inverter states {(V(1,0,1) ,V(1,0,0) ,V(1,1,0) ,V(0,1,0)} are applied can be calculated by solving thefollowing algebraic equations:

VrefTs = V(1,0,1)tv6 + V(1,0,0)tv1 + V(1,1,0)tv2 + V(0,1,0)tv3(14)

Ts = tv6 + tv1 + tv2 + tv3 . (15)

To solve the algebraic equations, we assume tv6 is equal totv3 . This leads to the following dwell times:

tv1 =3TsMI cos(θ)

4−

√3TsMI sin(θ)

4(16)

tv2 =√

3TsMI sin(θ)2

(17)

tv6 = tv3 =Ts

2− 3TsMI cos(θ)

8−

√3TsMI sin(θ)

8. (18)

For the even triangle shown in Fig. 4(c), the time intervalsin which the inverter states {(V(1,1,0) ,V(0,1,1) ,V(1,0,1)} areapplied can be calculated by solving the following algebraicequations:

VrefTs = V(1,1,0)tv2 + V(0,1,1)tv4 + V(1,0,1)tv6 (19)

Ts = tv2 + tv4 + tv6 . (20)

This leads to the following dwell times:

tv2 =Ts

3+

TsMI cos(θ)4

+√

3TsMI sin(θ)4

(21)

tv4 =Ts

3− TsMI cos(θ)

2(22)

tv6 =Ts

3+

TsMI cos(θ)4

−√

3TsMI sin(θ)4

. (23)

The similar calculation can be conducted for the other fivesectors by employing the appropriate vectors as listed in Table II.

Fig. 5. Vector synthesis of odd–even triangle for HSVPWMS II.

TABLE IIIVECTOR COMBINATIONS USED IN THE THREE SEGMENTS OF

EACH SECTOR USING HSVPWMS II

B. HSVPWMS II

The voltage reference vector passing through the odd–eventriangles can be synthesized by using the two adjacent volt-age vectors and one voltage vector of either neighboring stateto match the output and reference volt-seconds, as shown inFig. 5. Table III shows the vector combinations used in the threesegments of each sector for HSVPWMS II.

C. HSVPWMS III

The voltage reference vector passing through the odd–eventriangles can be synthesized by using the two adjacent voltagevectors and the two voltage vectors of the far states to match theoutput and reference volt-seconds, as shown in Fig. 6. Table IVshows the vector combinations used in the three segments ofeach sector for HSVPWMS III.

D. HSVPWMS IV

The voltage reference vector passing through the odd–eventriangles can be synthesized by using the two adjacent voltagevectors and one voltage vector of either far state to match the

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1599

Fig. 6. Vector synthesis of odd–even triangle for HSVPWMS III.

TABLE IVVECTOR COMBINATIONS USED IN THE THREE SEGMENTS OF

EACH SECTOR USING HSVPWMS III

Fig. 7. Vector synthesis of odd–even triangle for HSVPWMS IV.

output and reference volt-seconds, as shown in Fig. 7. Table Vshows the vector combinations used in the three segments ofeach sector for HSVPWMS IV.

IV. DEADTIME EFFECT AND NARROW CMVPULSE AVOIDANCE

The implementation of only odd or only even vectors requiressimultaneous switching of two converter legs. In practice, this

TABLE VVECTOR COMBINATIONS USED IN THE THREE SEGMENTS OF

EACH SECTOR USING HSVPWMS IV

Fig. 8. Deadtime effect on CMV. During the deadtimes, the CMV is dependenton the sign of the three-phase load current, CMV ∈ {Vdc,

V dc3 ,− V dc

3 ,−Vdc}.

Fig. 9. During td13 and ia > 0, ib < 0, and ic > 0, the CMV is equalto − V dc

3 .

could be challenging because of the deadtimes and the differ-ences in the gate delay [30]. The deadtime mismatch causes anarrow pulse in the CMV. The narrow pulse frequency increasesas the switching frequency increases. To further assess the situ-ation, consider Fig. 8. During the deadtimes, the resulting CMVis no longer a function of the switching commands. Instead it isstrictly dependent on the signs of the three-phase load currents.In this case, the CMV ∈ {Vdc,

Vdc3 ,−Vdc

3 ,−Vdc}. Therefore, theeffective switching state during the deadtimes must be analyzedfor each transition.

Consider the following three examples.Example 1: Suppose the transition from the odd vector

V(1,0,0) to the odd vector V(0,1,0) is taking place with thethree-phase load currents ia > 0, ib < 0, and ic > 0. The ef-fective switching state during the deadtime td13 will be thesame as the destination vector state (0, 1, 0). This is because ofthe current polarities, as shown in Fig. 9: ia is positive and willflow through the freewheeling diode of S4 when S1 turns OFF; ibis negative and will flow through the freewheeling diode of S2 ;and ic is positive and will flow through the freewheeling diode

1600 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

Fig. 10. During td13 and ia > 0, ib > 0, and ic < 0, the CMV is equalto −Vdc.

Fig. 11. During td13 and ia < 0, ib < 0, and ic > 0, the CMV is equalto V dc

3 .

Fig. 12. There are six regions in which the three-phase load currents do notchange sign.

of S6 . This is equivalent to connecting two of the load phases tothe lower dc rail −Vdc and only one phase to the upper dc railVdc. In this case, the resulting CMV during td13 is as expectedand equal to −Vdc

3 .Example 2: If the same transition occurs with the three-

phase load currents ia > 0, ib > 0, and ic < 0, the effectiveswitching state during the deadtime td13 will not be the same asthe destination vector state (0, 1, 0). Instead it will be (0, 0, 0),and the resulting CMV during td13 will be equal to −Vdc, asshown in Fig 10.

Example 3: If the same transition occurs with the three-phase load currents ia < 0, ib < 0, and ic > 0, the effectiveswitching state at the deadtime td13 will not be the same as thedestination vector state (0, 1, 0). Instead it will be (1, 1, 0), andresulting CMV will be Vdc

3 , as shown in Fig. 11.By considering all of the possible intervals in which the three-

phase load currents do not change sign, six current sectors can bedefined, as shown in Fig. 12. The calculations for the effectiveswitching states during the other deadtimes are performed inthe same manner as illustrated in the examples and listed inTables VII and VIII for odd and even states, respectively. It isimportant to note that the effective switching state is the sameas the effective switching state when the transition is reversed

Fig. 13. Current sectors (in which the three-phase load currents do not changesign) in relation to the voltage vectors. (a) When PF = 1 lagging. (b) WhenPF = 0.866 lagging.

Fig. 14. Modified control block diagram to account for the current sectorsposition.

(tdxy = tdyx ). For this reason, the calculations for this type oftransition are not included in the tables.

It is evident from Tables VII and VIII that the CMV is notlimited to |Vdc

3 | even if only odd or only even states are used.Therefore, to avoid the unwanted CMV peaks (|Vdc|), the controlalgorithm must be modified to use only odd states in S-II, S-IV,and S-VI and only even states in S-I, S-III, and S-V. The currentsectors are shown in Fig. 13(a).

It is important to note the connection between the currentsectors {S-I–S-VI} and the power factor (PF). In machine driveapplications the current space vector (i) is lagging. This causesthe current sectors to rotate clockwise and changes the feasibleregions of using only odd or only even states. Fig. 13(b) showsthe rotated current space vector when the PF = 0.866 lagging.

Modifying the control algorithm to avoid the peak CMV isnot difficult as long as the load current signals are available inthe loop. Fig. 14 shows the modified control block diagram.

The current sectors are determined by measuring the loadcurrents and checking the sign of each phase current. Althoughthis modification allows one to avoid the maximum CMV peaks,high dvcm

dt is still possible during some deadtimes. Furthermore,the availability of only odd or only even vectors is linked tothe PF. When the PF = 1, the current sectors are completelyout of sync. Whereas if the PF = 0.866, the current sectorsare completely in sync. To avoid this limitation, the authorspropose a new commutation method in the next section. The newcommutation method allows a complete decoupling of the effectof PF, and it avoids the narrow CMV pulse during deadtimeintervals.

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1601

Fig. 15. Commutation sequences that do not cause a change in CMV during deadtime intervals. Each current sector has two safe sequences: one for only oddand one for only even syntheses. This allows the use of only odd and only even vectors without any constraints imposed by the PF.

V. PROPOSED COMMUTATION ALGORITHM

As shown in the previous section, by including the load cur-rent signals in the control loop, one can determine when it is safeto use only odd or only even vectors without causing peak CMV.However, there are unwanted transitions in the CMV from Vdc

3to −Vdc

3 or vice versa during some deadtime intervals. As Ta-bles VII and VIII demonstrate, in each current sector there aretwo deadtime intervals in which no change in the CMV occurs.

These two deadtimes can be utilized to make a proper commu-tation sequence among the odd vectors or even vectors. Fig. 15shows the commutation sequences that achieve no change in theCMV during the deadtime intervals. Furthermore, the rotationof the current sectors due to the PF will not affect the availabilityof only odd or only even vectors because in each current sectorthere are two safe sequences: one for only odd states and onefor only even states. The safe sequences also allow us to equal-ize switching losses per fundamental cycle among the IGBTs.

1602 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

Fig. 16. CMV waveforms and their corresponding frequency spectrum using the regular SVPWM. (a) MI = 0.6667. (b) MI = 0.866. (c) MI = 1.

Fig. 17. CMV waveforms and their corresponding frequency spectrum using HSVPWMS I. (a) MI = 0.6667. (b) MI = 0.866. (c) MI = 1.

Therefore, there is no unbalanced temperature distribution ininverter switches.

VI. PERFORMANCE ANALYSIS

HSVPWMS methods utilize different voltage vectors withdifferent possible sequences. Each synthesis and combinationcorresponds to a different number of commutations, output cur-rent quality, CMV characteristics, dc-link current harmonics,and switching losses. Therefore, to understand the full poten-tial of each method, a fair comparison with the CMV reductionPWM methods in terms of CMV characteristics, HDF, dc-linkcurrent, and switching losses is presented next.

A. CMV Characteristics

Common-mode behavior for induction machines is mostlycapacitive [41]. Therefore, it does not require an extensivehigh-frequency machine modeling to determine the relation-ship between CMV characteristics and the resulting CMC.Early studies showed that the parasitic machine capacitancescan be measured [42] or calculated by finite element methods[43], [44]. A machine model for high frequencies is develeopedin [45] and shows that the CMC is directly proportional to thefrequency of the CMV.

Fig. 16 shows the CMV and its spectrum for the conventionalSVPWM. The amplitude of the CMV is Vdc and is high due tothe use of zero vectors. Another fundamental component of theCMV at the PWM carrier frequency (fc ).

All of the other HSVPWMS methods have similar CMVwaveforms for MI ≤ 4

3√

3, where the main harmonic compo-

nents are at 3f1 and 6f1 , where f1 is the system fundmantalfrequency (for instance 60 Hz). These two frequency compo-nents result in a very small CMC because the impedance isvery high prior to the resonance region [41]. HSVPWMS I andHSVPWMS III have harmonic components around the carrierfrequency fc with an amplitude lower than that of the conven-tional SVPWM method. The fc component increases as theMI increases, as shown in Figs. 17 and 19. HSVPWMS II andHSVPWMS IV have high-frequency CMV components around2fc that increase as the MI increases. Most of the CMV harmoniccomponents are concentrated in the fundamental component 3f1and baseband harmonic 6f1 , as shown in Figs. 18 and 20. Gen-erally, HSVPWMS methods have a maximum CMV amplitudeequal to Vdc

3 , which is three times less than the regular SVPWM.More importantly, the amplitudes of CMV at high frequenciesare reduced tremendously, especially at MI ≤ MImax. Therefore,the resulting CMC in the HSVPWMS method is significantlyreduced as compared against the other methods.

Fig. 21 gives a clear representation of how the fundamentalcomponent of the CMV is behaving versus MI within the linearmodulation region. The simulation parameters are: dc-link volt-age 60 V, carrier frequency fc = 5 kHz, and system fundamentalfrequency f1 = 60 Hz. It has been observed through multiplesimulations that the characteristic of each harmonic is relativelyconstant to those parameters. Therefore, the plots are givenin terms of the dc-link voltage, fundamental frequency, andthe carrier frequency. The high-frequency CMV of the regular

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1603

Fig. 18. CMV waveforms and their corresponding frequency spectrum using HSVPWMS II. (a) MI = 0.6667. (b) MI = 0.866. (c) MI = 1.

Fig. 19. CMV waveforms and their corresponding frequency spectrum using HSVPWMS III.

Fig. 20. CMV waveforms and their corresponding frequency spectrum using HSVPWMS IV.

Fig. 21. Fundamental component of the CMV. The fundamental frequency ofthe CMV in SVPWM is equal to fc = 5 kHz. Whereas in HSVPWMS methodsthe frequency of the fundamental component is equal to 3f1 = 180 Hz.

SVPWM has a very high amplitude when the MI is low be-cause of the high duty ratio of the zero vector. The suitableHSVPWMS can be selected based on the level of the MI andthe characteristics of the machine common-mode impedance.

B. Harmonic Distortion Factor

In the motor winding fsw/f ≥ 20, the harmonic current isdirectly proportional to the harmonic flux. Therefore, the cur-rent quality can be studied by using only the information of theapplied voltage vector independent of the load ratings. The con-cept of HDF introduced in [46] is further expanded to accountfor the transitions between different syntheses. The harmonicflux for the N th carrier cycle can be defined as [29]

λh(MI, θ, V(.,.,.)) =∫ (N +1)Ts

N Ts

(V(.,.,.) − Vref)dt (24)

where V(.,.,.) is the applied voltage vector during the samplingtime NTs . Normalizing the harmonic flux results in the har-

1604 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

monic flux voltage vector

λhn =π

VdcTsλh . (25)

Each voltage utilization method results in a unique harmonicvoltage vector trajectory. The normalized harmonic flux rmsvalue over a PWM (duty cycle δ of 0 to 1) is calculated asfollows:

λhn−rms(MI, θ) = K2f

√∫ 1

0λ2

hndδ (26)

where Kf is the ratio of the switching per PWM cycle betweenthe regular SVPWM and the HSVPWMS methods. In order toattain a fair comparison between HSVPWMS methods and theregular SVPWM method, all HSVPWMS methods are set tooperate at the same switching frequency by dividing the carrierfrequency of each method by Kf . Taking the average value ofthe rms harmonic flux function over a full fundamental cycleresults in the HDF, which is a measure of the ac current ripple

HDF =288π2

12π

∫ 2π

0λhn−rmsdθ. (27)

The hybrid harmonic distortion factor HDFH is obtained byaveraging the HDFs of each sequence based on the value of themodulation index as follows:

HDFH =

{HDF(O∨E) MI ≤ 4

3√

3

MpHDF(O∨E) + (1 − Mp)HDF(E∧O) MI > 43√

3(28)

where Mp is the modulation parametric factor defined as

Mp =MImax − MI

23√

3

. (29)

HDF(O∨E) is HDF calculated when only the odd vec-tors {V(1,0,0) ,V(0,1,0) ,V(0,0,1)} are applied or only theeven vectors {V(1,1,0) ,V(0,1,1) ,V(1,0,1)} are applied, de-pending on the location of the segments as describedpreviously for each HSVPWMS. HDF(O∧E) is HDF cal-culated when both odd and even vectors are ap-plied {V(1,0,0) ,V(1,1,0) ,V(0,1,0) ,V(0,1,1) ,V(0,0,1) ,V(1,0,1)},depending on the selected group of vectors. When the MI is lessthan or equal to 4

3√

3, the HDFH is identical to the HDF result-

ing from only odd vectors or only even vectors. When the MI isgreater than 4

3√

3, the HDFF is averaged based on the definition

in (28). Fig. 22 shows the numerical results of HDFH for allHSVPWMS along with the regular SVPWM.

All the HSVPWMS methods present similar HDF in the re-gion where MI ≤ 4

3√

3. Although the HDF for HSVPWMS II

Fig. 22. HDF for the HSVPWMS methods compared with the conventionalPWMS methods.

is lower than the other hybrid methods, it presents higher CMVfrequency as will be seen later in the results.

C. DC-Link Current Harmonics

The rms current on the dc side is important factor in determin-ing the dc-link capacitor sizing [47]. To compare the behaviorof the PWM methods, Kdc is defined in [29] as

Kdc =I2in−h−rms

I21−rms

(30)

where Iin−h−rms is the rms value of the dc-link current andI1−rms is the fundamental component of the output rms current.The calculations for Kdc are performed numerically for differ-ent power factors. Fig. 23(a)–(c) show Kdc for the HSVPWMSmethods compared with the conventional SVPWM and CMVreduction methods. When the PF is high, Kdc for the hybridmethods is higher than the other methods. However, when op-erating at low PF, Kdc for the hybrid methods surpasses Kdc forall of the other CMV reduction methods. In general, Kdc valuesfor the all hybrid methods are almost identical and decrease withdecreasing the power factor.

D. Switching Losses

The switching losses for the VSI using HSVPWMS are calcu-lated analytically by taking into account the effect of changingdifferent vector syntheses over the switching frequency. TheIGBT current and voltage do not abruptly change their val-ues. Instead there is a transition interval in which both the cur-rent and voltage across the IGBT have values larger than zero[48], [50]. The average value of the switching losses can be

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1605

Fig. 23. DC-link current ripple coefficient (Kdc) for various PWM methods. (a) PF = 1. (b) PF = 0.8. (c) PF = 0.6. (d) PF = 0.4.

TABLE VIEFFECTIVE SWITCHING FREQUENCY fs DEFINED AS A FUNCTION

OF THE MODULATION INDEX

calculated as follows:

Psw−IGBT

= fs(MI)[ ∫ t+tr

t

iC (t)vCE(t)dt +∫ t+tf

t

iC (t)vCE(t)dt

]

(31)

where fs is the effective switching frequency that represents thenumber of switching instants for one IGBT in one fundamentalfrequency period, unlike the regular SVPWM. fs in HSVPWMSis a function of the modulation index, as shown in Table VI. iC isthe collector current, and vCE is the voltage across the collector–emitter. tr and tf are the rising and falling times, respectively.The integration explained in Appendix A results in the followingaverage switching losses per IGBT:

Psw−IGBT = fs(MI)[13ILVdctr +

950

ILVdctf

]. (32)

The total switching losses also include the reverse recoverylosses associated with the diode turn-off process

Prr−D =12fs(MI)IrrVdctrr (33)

where Irr is the maximum value of the reverse recovery current,and trr is the reverse recovery time.

Fig. 24. Switching losses for the HSVPWMS methods compared with theconventional PWM methods.

To obtain the effective switching frequency, the number ofcommutations per sampling time is counted, as shown in theTable VI. Fig. 24 shows the switching losses of HSVPWMSmethods compared with the conventional PWM methods.

VII. EXPERIMENTAL RESULTS

The experimental work has been carried out using the fol-lowing parameters and operating conditions: dc-link voltage100 V carrier frequency fc = 5 kHz and an RL load with 5 Ωand 2 mH. The system consists of three inverter legs with eachleg being realized by the IGBT module CM100DY-24A. Thecontrol algorithm is implemented using DSpace CP1103.

Fig. 25(a) shows the resulting CMV with MI = 0.75. Thereference voltage vector is synthesized using only odd and onlyeven states. This results in a square wave CMV with a frequencyequal to 3f1 (three times the fundamental frequency of the sys-tem 180 Hz). Fig. 25(b) shows the fast Fourier transform (FFT)for the CMV with MI = 0.75. All of the CMV is concentratedat 180 Hz. The CMV frequency spectrum is the similar to theone in Fig. 25(b) at any MI ∈ {0, 0.766}.

1606 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

Fig. 25. Experimental results. (a) CMV at MI = 0.75 (1—HSVPWMS I, 2—HSVPWMS II, 3—HSVPWMS III, 4—HSVPWMS IV). (b) FFT of the CMV.

Fig. 26. Experimental results. (a) CMV waveforms at MI = 0.85 for 1—SVPWM, 2—HSVPWMS I, 3—HSVPWMS II, 4—HSVPWMS III, 5—HSVPWMS IV, 6—AZSPWM1-2, 7—NSPWM, 8—AZSPWM3, and 9—DPWM1. (b) FFT of the CMV.

Fig. 26(a) shows the CMV with MI = 0.85 for the pro-posed hybrid approach and several PWM methods. For theMI > 0.766, the reference voltage vector starts entering theodd–even region, leading to a CMV that fluctuates betweenthe values of Vdc

3 and −Vdc3 . However, the CMV spectrum is still

concentrated at 180 Hz frequency, as shown in Fig. 26(b). Thefrequency spectrum for the conventional SVPWM and DPWM1includes high amplitude CMV due to the use of the zero vector.This high amplitude is located at the carrier frequency (nor-

Fig. 27. Experimental results. (a) CMV waveforms at MI = 1 for 1—SVPWM, 2—HSVPWMS I, 3—HSVPWMS II, 4—HSVPWMS III, 5—HSVPWMS IV, 6—AZSPWM1-2, 7—NSPWM, 8—AZSPWM3, and 9—DPWM1. (b) FFT of the CMV.

mally in kHz). The conventional CMV reduction PWM meth-ods have lower CMV amplitudes, but they are still located atthe carrier frequency. The main difference between the proposedmethod and the conventional CMV reduction methods is that theCMV frequency is decreased. A lower frequency CMV has twomain advantages over a high-frequency CMV. First, less CMVfluctuation corresponds to less EDM in the bearings. Second, alow-frequency CMV can help meet the EMC standards becausethe amplitude limit for low frequencies is much higher than theamplitude limit for high frequencies.

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1607

Fig. 28. Experimental results of the load current ia (t). (a) MI = 0.85. (b) MI = 1 for 1—SVPWM+20A, 2—HSVPWMS I+15A, 3—HSVPWMS II+10A,4—HSVPWMS III+5A, 5—HSVPWMS IV, 6—AZSPWM1-2-5A, 7-NSPWM-10A, 8-AZSPWM3-15A, and 9-DPWM1-20A.

Fig. 29. Experimental results. (a) HSVPWMS II without implementing the safe commutation algorithm. During the deadtimes the effective switching state couldbe one of the zero vectors V(0 ,0 ,0) or V(1 ,1 ,1) and the CMV will be similar to type 1, or it could be similar to type 2 when the effective switching state resultin one of the odd or even vectors. (b) HSVPWMS II with implementing the safe commutation algorithm, both types 1 and 2 unwanted transitions are successfullyavoided. MI = 0.85.

Fig. 27(a) shows the CMV at MI = 1 for the proposed hybridapproach and several PWM methods. As the MI increases higherthe implementation of only odd or only even synthesis decreasesleading to high-frequency CMV frequency components. How-ever, the high-frequency CMV components are still less than theones resulting from the conventional CMV reduction methods,as shown in Fig. 27(b).

Fig. 28(a) and (b) show the load currents for the proposedmethods along with the conventional PWM methods. Althoughthe load is mostly resistive with PF = 0.988, current ripplesresulting from the proposed hybrid methods are still comparablewith the current ripples resulting from the conventional PWMmethods. As the MI increases, the HDF of load currents forthe proposed hybrid method improves because the referencevoltage vector synthesis shifts from only odd and only oven toodd–even.

Fig. 30. Switching ON and OFF events for an IGBT.

Fig. 29(a) shows the CMV waveform without implementingthe safe commutation algorithm. There are two types of un-

1608 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

TABLE VIIEFFECTIVE SWITCHING STATES IN CASE OF ONLY ODD MODULATION

wanted transitions during the deadtime intervals: Type 1 resultsin CMV equal to |Vdc|, and Type 2 results in CMV that changessign from Vdc

3 to −Vdc3 or vice versa. These unwanted CMV

pulses can be fully avoided when the proposed commutationsequences is implemented, as shown in Fig. 29(b).

VIII. CONCLUSION

In this paper, a set of new HSVPWMS control methodsare proposed to minimize the amplitude and frequency ofthe CMV. A detailed comparison shows the relative perfor-mance of the conventional PWM methods and the proposedHSVPWMS methods in terms of CMV characteristics, HDF,switching losses, and dc ripples. The conventional PWM meth-ods have a CMV harmonic component with high frequencyequal to the carrier frequency fc . The new HSVPWMS methodproposed in the paper limits the CMV amplitude to Vdc

3 andconcentrates the CMV harmonics to a low frequency equal tothree times the fundamental frequency 3f1 . A new commuta-tion algorithm that avoids nonlinear behavior during deadtimeintervals is proposed. The performance of the proposed HSVP-WMS algorithms has been verified via simulations and validatedby laboratory experiments. The new HSVPWMS method canpotentially enable converters to operate at a very high switch-ing frequency using the newly emerging wide bandgap deviceswhile effectively mitigating the adverse CMV effects associatedwith conventional high-frequency PWM schemes.

APPENDIX ATABLES

Tables VII–VIII show the effective switching states in caseof only odd and only even syntheses deadtimes.

TABLE VIIIEFFECTIVE STATES IN CASE OF ONLY EVEN MODULATION

APPENDIX BAVERAGE LOSSES IN TURN ON AND OFF EVENTS

Fig. 30 shows a typical turn-on and turn-off waveforms char-acteristic for an IGBT switch.

Equation (31) can be expanded by simple linear approxima-tion of iC and vCE, except during turn-off events, in which caseiC can be approximated as an exponentially decaying functionas follows [48]:

iC (t) = ILe−a(t−ti ) (34)

where ti is the initial value of time in which the turn-off eventstarted and a is a constant that can be adjusted to achieve thebest function approximation. To solve (34), it is assumed that att = ti + tf , 95% of the collector current iC vanishes. Therefore,a can be defined as a function of the falling time tf as follows:

a =3tf

. (35)

Therefore, the integral becomes

Psw−IGBT = fs(MI)[∫ tr

0

0tr

iC

(2Vdc − t

tr2Vdc

)dt

+∫ tf

0ILe−at t

tf2Vdcdt

](36)

Psw−IGBT = fs(MI)[13ILVdctr

+2ILVdc

tf

(1 − e−atf (atf + 1)

a2

)].

(37)

JANABI AND WANG: HYBRID SVPWM SCHEME TO MINIMIZE THE CMV FREQUENCY AND AMPLITUDE IN VOLTAGE SOURCE INVERTER 1609

Substituting (35) in (37) leads to

Psw−IGBT = fs(MI)[13ILVdctr +

950

ILVdctf

]. (38)

REFERENCES

[1] H. Chen and H. Zhao, “Review on pulse-width modulation strategiesfor CMV reduction in three-phase voltage-source inverters,” IET PowerElectron., vol. 9, no. 14, pp. 2611–2620, Nov. 16, 2016.

[2] S. Nagai et al., “A 3-Phase AC-AC matrix converter gan chipset withdrive-by-microwave technology,” IEEE J. Electron Devices Soc., vol. 3,no. 1, pp. 7–14, Jan. 2015.

[3] A. Lemmon, R. Cuzner, J. Gafford, R. Hosseini, A. D. Brovont, andM. Mazzola, “Methodology for characterization of common-mode con-ducted electromagnetic emissions in wide-band-gap converters for un-grounded shipboard applications,” IEEE J. Emer. Sel. Topics Power Elec-tron., vol. 6, no. 1, pp. 300–314, Mar. 2018.

[4] D. Busse, J. Erdman, R. J. Kerkman, D. Schlegel, and G. Skibinski,“Bearing currents and their relationship to PWM drives,” IEEE Trans.Power Electron., vol. 12, no. 2, pp. 243–252, Mar. 1997.

[5] S. Chen and T. A. Lipo, “Bearing currents and shaft voltages of an in-duction motor under hard- and soft-switching inverter excitation,” IEEETrans. Ind. Appl., vol. 34, no. 5, pp. 1042–1048, Sep./Oct. 1998.

[6] A. L. Julian, T. A. Lipo, and G. Oriti, “Elimination of CMV in threephase sinusoidal power converters,” in Conf. Rec. 27th Annu. IEEE PowerElectron. Special. Conf., Baveno, Italy, 1996, vol. 2, pp. 1968–1972.

[7] S. Chen, Bearing Current EMI and Soft Switching in Induction MotorDrives. Madison, WI, USA: University of Wisconsin–Madison, 1995.

[8] R. Vargas, U. Ammann, J. Rodriguez, and J. Pontt, “Predictive strategyto control CMV in loads fed by matrix converters,” IEEE Trans. Ind.Electron., vol. 55, no. 12, pp. 4372–4380, Dec. 2008.

[9] M. Cacciato, A. Consoli, G. Scarcella, and A. Testa, “Reduction ofcommon-mode currents in PWM inverter motor drives,” IEEE Trans. Ind.Appl., vol. 35, no. 2, pp. 469–476, Mar./Apr. 1999.

[10] C. T. Morris, D. Han, and B. Sarlioglu, “Reduction of common modevoltage and conducted EMI through three-phase inverter topology,” IEEETrans. Power Electron., vol. 32, no. 3, pp. 1720–1724, Mar. 2017.

[11] D. Han, C. T. Morris, and B. Sarlioglu, “Common-mode voltage cancel-lation in PWM motor drives with balanced inverter topology,” Trans. Ind.Electron., vol. 64, no. 4, pp. 2683–2688, Apr. 2017.

[12] M. D. Manjrekar and T. A. Lipo, “An auxiliary zero state synthesizerto reduce common mode voltage in three-phase inverters,” in Conf. Rec.IEEE Ind. Appl. Conf 34th IAS Annu. Meeting, Phoenix, AZ, USA, 1999,vol. 1, pp. 54–59.

[13] Y. Sun, A. Esmaeli, and L. Sun, “A new method to mitigate the adverseeffects of PWM inverter,” in Proc. 1ST IEEE Conf. Ind. Electron. Appl.,Singapore, 2006, pp. 1–4.

[14] A. Kempski, R. Smolenski, E. Kot, and Z. Fedyczak, “Active and pas-sive series compensation of CMV in adjustable speed drive system,” inConf. Rec. IEEE Ind. Appl. Conf. 39th IAS Annu. Meeting, 2004, vol. 4,pp. 2665–2671.

[15] M. Kikuchi, N. Aizawa, H. Kubota, I. Miki, and K. Matsuse, “Investigationof CMVs of PWM inverter with a small capacity auxiliary inverter,” inProc. Int. Conf. Electric. Mach. Syst., Tokyo, Japan, 2009, pp. 1–6.

[16] H. Akagi, H. Hasegawa, and T. Doumoto, “Design and performance ofa passive EMI filter for use with a voltage-source PWM inverter havingsinusoidal output voltage and zero CMV,” in Proc. IEEE 33rd Annu. IEEEPower Electron. Specialists Conf. , 2002, vol. 3, pp. 1543–1550.

[17] A. L. Julian, T. A. Lipo, and G. Oriti, “Elimination of common modevoltage in three phase sinusoidal power converters,” in Conf. Rec. 27thAnnu. IEEE Power Electron. Specialists Conf., Baveno, 1996, vol. 2,pp. 1968–1972.

[18] K. Euerle, K. Iyer, E. Severson, R. Baranwal, S. Tewari, and N. Mohan,“A compact active filter to eliminate common-mode voltage in aSiC-based motor drive,” in Proc. IEEE Energy Convers. Congr. Expo.,Milwaukee, WI, USA, 2016, pp. 1–8.

[19] S. Takahashi, S. Ogasawara, M. Takemoto, K. Orikawa, and M. Tamate,“Common-mode voltage attenuation of an active common-mode filter ina motor drive system fed by a PWM inverter,” in Proc. 20th Int. Conf.Elect. Mach. Syst., Sydney, NSW, Australia, 2017, pp. 1–6.

[20] D. Hyypio, “Mitigation of bearing electro-erosion of inverter-fed motorsthrough passive common-mode voltage suppression,” IEEE Trans. Ind.Appl., vol. 41, no. 2, pp. 576–583, Mar./Apr. 2005.

[21] T. M. Parreiras, B. M. Pereira do Prado, and B. de J. Cardoso Filho,“Common-mode overvoltage mitigation in a medium-voltage pump motor

transformerless drive in a mining plant,” IEEE Trans. Ind. Appl., vol. 54,no. 1, pp. 848–857, Jan./Feb. 2018.

[22] M. H. Hedayati and V. John, “Filter configuration and PWM method forsingle-phase inverters with reduced conducted EMI noise,” IEEE Trans.Ind. Appl., vol. 51, no. 4, pp. 3236–3243, Jul./Aug. 2015.

[23] M. H. Hedayati, A. B. Acharya, and V. John, “Common-mode filter designfor PWM rectifier-based motor drives,” IEEE Trans. Power Electron.,vol. 28, no. 11, pp. 5364–5371, Nov. 2013.

[24] A. Muetze and B. S. Heng, “Performance of common-mode chokes,” IEEEInd. Appl. Mag., vol. 16, no. 2, pp. 31–38, Mar./Apr. 2010.

[25] A. Muetze and C. R. Sullivan, “Simplified design of common-mode chokesfor reduction of motor ground currents in inverter drives,” IEEE Trans.Ind. Appl., vol. 47, no. 6, pp. 2570–2577, Nov./Dec. 2011.

[26] J. Huang and H. Shi, “A hybrid filter for the suppression of common-mode voltage and differential-mode harmonics in three-phase inverterswith CPPM,” IEEE Trans. Ind. Electron., vol. 62, no. 7, pp. 3991–4000,Jul. 2015.

[27] P. Garg, S. Essakiappan, H. S. Krishnamoorthy, and P. N. Enjeti, “A fault-tolerant three-phase adjustable speed drive topology with active common-mode voltage suppression,” IEEE Trans. Power Electron., vol. 30, no. 5,pp. 2828–2839, May 2015.

[28] E. Un and A. M. Hava, “A near-state PWM method with reduced switchinglosses and reduced common-mode voltage for three-phase voltage sourceinverters,” IEEE Trans. Ind. Appl., vol. 45, no. 2, pp. 782–793, Mar./Apr.2009.

[29] A. M. Hava and E. Un, “Performance analysis of reduced common-modevoltage PWM methods and comparison with standard PWM methodsfor three-phase voltage-source inverters,” IEEE Trans. Power Electron.,vol. 24, no. 1, pp. 241–252, Jan. 2009.

[30] C. C. Hou, C. C. Shih, P. T. Cheng, and A. M. Hava, “Common-modevoltage reduction pulsewidth modulation techniques for three-phase grid-connected converters,” IEEE Trans. Power Electron., vol. 28, no. 4,pp. 1971–1979, Apr. 2013.

[31] K. Y. Chen and M. S. Hsieh, “Generalized minimum common-mode volt-age PWM for two-level multiphase VSIs considering reference order,”IEEE Trans. Power Electron., vol. 32, no. 8, pp. 6493–6509, Aug. 2017.

[32] D. G. Holmes, “The significance of zero space vector placement for carrier-based PWM schemes,” IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 1122–1129, Sep./Oct. 1996.

[33] D. G. Holmes, “The significance of zero space vector placement for carrierbased PWM schemes,” in Conf. Rec. 30th Ind. Appl. Conf. 13th IAS Annu.Meeting, Orlando, FL, USA, 1995, vol. 3, pp. 2451–2458.

[34] R. M. Tallam, R. J. Kerkman, D. Leggate, and R. A. Lukaszewski,“Common-mode voltage reduction PWM algorithm for AC drives,” IEEETrans. Ind. Appl., vol. 46, no. 5, pp. 1959–1969, Sep./Oct. 2010.

[35] D. G. Holmes, “The significance of zero space vector placement for carrierbased PWM schemes,” in Conf. Rec. Ind. Appl. Conf 13th IAS Annu.Meeting, Orlando, FL, USA, 1995, vol. 3, pp. 2451–2458.

[36] A. M. Hava and E. Un, “A high-performance PWM algorithm forcommon-mode voltage reduction in three-phase voltage source invert-ers,” IEEE Trans. Power Electron., vol. 26, no. 7, pp. 1998–2008, Jul.2011.

[37] M. Cacciato, S. D. Caro, G. Scarcella, G. Scelba, and A. Testa, “Improvedspace-vector modulation technique for common mode currents reduction,”IET Power Electron., vol. 6, no. 7, pp. 1248–1256, Aug. 2013.

[38] Y.-S. Lai and F.-S. Shyu, “Optimal common-mode Voltage reductionPWM technique for inverter control with consideration of the dead-timeeffects-part I: Basic development,” IEEE Trans. Ind. Appl., vol. 40, no. 6,pp. 1605–1612, Nov./Dec. 2004.

[39] M. Cacciato, A. Consoli, G. Scarcella, G. Scelba, and A. Testa, “A novelspace-vector modulation technique for common mode emissions reduc-tion,” in Proc. IEEE Int. Aegean Conf. Electric. Mach. Power Electron.,Bodrum, Turkey, 2007, pp. 199–204.

[40] C. C. Hou, C. C. Shih, P. T. Cheng, and A. M. Hava, “Common-modevoltage reduction pulsewidth modulation techniques for three-phase grid-connected converters,” IEEE Trans. Power Electron., vol. 28, no. 4,pp. 1971–1979, Apr. 2013.

[41] M. Schinkel, S. Weber, S. Guttowski, W. John, and H. Reichl, “EfficientHF modeling and model parameterization of induction machines for timeand frequency domain simulations,” in Proc. 21st Annu. IEEE Appl. PowerElectron. Conf. Expo., Dallas, TX, USA, 2006, 6 pages.

[42] F. Zare, “Practical approach to model electric motors for electromagneticinterference and shaft voltage analysis,” IET Elect. Power Appl., vol. 4,no. 9, pp. 727–738, Nov. 2010.

[43] O. Magdun, Y. Gemeinder, and A. Binder, “Prevention of harmful EDMcurrents in inverter-fed AC machines by use of electrostatic shields in the

1610 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 34, NO. 2, FEBRUARY 2019

stator winding overhang,” in Proc. 36th Annu. Conf. IEEE Ind. Electron.Soc., Glendale, AZ, USA, 2010, pp. 962–967.

[44] D. Busse, J. Erdman, R. J. Kerkman, D. Schlegel, and G. Skibinski,“Bearing currents and their relationship to PWM drives,” IEEE Trans.Power Electron., vol. 12, no. 2, pp. 243–252, Mar. 1997.

[45] O. Magdun and A. Binder, “High-frequency induction machine modelingfor common mode current and bearing voltage calculation,” IEEE Trans.Ind. Appl., vol. 50, no. 3, pp. 1780–1790, May/Jun. 2014.

[46] A. M. Hava, R. J. Kerkman, and T. A. Lipo, “Simple analytical and graph-ical methods for carrier-based PWM-VSI drives,” IEEE Trans. PowerElectron., vol. 14, no. 1, pp. 49–61, Jan. 1999.

[47] J. W. Kolar and S. D. Round, “Analytical calculation of the RMS currentstress on the DC-link capacitor of voltage-PWM converter systems,” IEEEProc. Elect. Power Appl., vol. 153, no. 4, pp. 535–543, Jul. 2006.

[48] W. Mazgaj, B. Rozegna, and Z. Szular, “Switching losses in three-phasevoltage source inverters,” Czasopismo Techniczne, vol. 13, pp. 47–60,2016.

[49] M. H. Bierhoff and F. W. Fuchs, “Semiconductor losses in voltage sourceand current source IGBT converters based on analytical derivation,” inProc. IEEE 35th Annu. Power Electron. Specialists Conf., 2004, vol. 4,pp. 2836–2842.

[50] O. Oederra, I. Kortabarria, I. M. de Alegra, J. Andreu, and J. I. Grate,“Three-phase VSI optimal switching loss reduction using variable switch-ing frequency,” IEEE Trans. Power Electron., vol. 32, no. 8, pp. 6570–6576, Aug. 2017.

Ameer Janabi (S’14) was born in Babylon, Iraq. Hereceived the B.S. degree in electromechanical engi-neering from the University of Technology, Baghdad,Iraq, in 2011, the M.S. degree in electrical and com-puter engineering from Michigan State University,East Lansing, MI, USA, in 2016, where he is cur-rently pursuing the Ph.D. degree.

He was an Automation Engineer with Lafarge,Iraq. His research interests include the design of elec-tric machine drives and advanced control of powerconverters.

Bingsen Wang (S’01–M’06–SM’08) is a native ofChina. He received the M.S. degrees from ShanghaiJiao Tong University, Shanghai, China, and the Uni-versity of Kentucky, Lexington, KY, USA, in 1997and 2002, and the Ph.D. degree from the Universityof Wisconsin-Madison, Madison, WI, USA, in 2006,all in electrical engineering.

From 1997 to 2000, he was an Electrical Engineerwith Carrier Air Conditioning Equipment Company,Shanghai, China. He was also a Power ElectronicsEngineer with General Electric Global Research Cen-

ter, New York, NY, USA. While being with GE, he was engaged in variousresearch activities in power electronics, mainly focused in the high-power area.From 2008 to 2009, he was on the faculty of the Department of ElectricalEngineering, Arizona State University, Tempe, AZ, USA. Since 2010, he hasbeen a Faculty Member with the Department of Electrical and Computer Engi-neering, Michigan State University, East Lansing, MI, USA. He has authoredand coauthored more than 40 technical articles in refereed journals and peer re-viewed conference proceedings. His current research interests include reliabilityand dynamic modeling/control of power electronic systems, power conversiontopologies, in particular multilevel converters and matrix converters, applicationof power electronics to renewable energy systems, power conditioning, flexibleac transmission systems, and electric drives.

Dr. Wang holds one Chinese patent and three US patents. He was the re-cipient of the Prize Paper Award from Industrial Power Converter Committee(IPCC) of IEEE Industry Application Society in 2005. He has been an AssociateEditor of the IEEE POWER ELECTRONICS LETTERS since 2009.