Generalized Optimal SVPWM for the Switched-Capacitor Voltage Boost Converter

Shukai Wang, Ameer Janabi, Bingsen Wang

Department of Electrical and Computer Engineering Michigan State University

East Lansing, USA wangshuk@msu.edu; Janabiam@msu.edu; bingsen@egr.msu.edu

Abstract—This paper presents a generalized space vector pulse width modulation SVPWM for the switched capacitor voltage boost converter. The algorithm is based on relaxing the location of the ON time interval within the sampling time. The four switching functions of the SC converter result in four variable that represent the location of the ON time inverter. The optimal solution of the four variable is obtained by using Monte Carlo simulation that is based on minimizing the harmonic distortion factor. Furthermore, the proposed algorithm allows seamless transition between the various SVPWM such as DPWMMAX, DPWMMIN, and regularly sampled SVPWM. The finding of this paper is presented in a form of MATLAB simulation results.

Keywords— Switched-capacitor converter, optimal SVPWM, boost voltage source inverter

I. INTRODUCTION

VSIs are inherently buck converters. Therefore, the dc-link voltage must be higher than the dc or ac input voltage. For applications where the available dc voltage is limited, an additional dc-dc boost converter is needed to obtain the desirable ac voltage [1]. For the commercial traction electric drive, the battery connected to the inverter with an intermediate dc-dc boost stage. The boost stage typically

includes an inductor. This conventional boost stage is not quite perfect. The power rating of the dc-dc converter must match the battery pack power, leading to a proportionally large inductor. The inductor is a heavy and costly component. Furthermore, the inductor copper and core losses increase proportionally with the size of the inductor. When boosted by a high-voltage ratio, the boost converter must operate with a high duty cycle where the efficiency is relatively low [1]. The partial power efficiency is also reduced because the ac losses (switching loss and ac magnetic loss) depend on voltage but are nearly independent of current. At high duty cycles, the rms current applied to the bus capacitor is also quite high, which impacts the size and cost of the capacitor [1].

To overcome the above limitations of the traditional drive trains, this paper presents the switched-capacitor voltage boost (SC) converter and its control methods. Fig. 1 shows one version of the proposed SC converter. It employs a switched capacitor circuit with the inverter to form a unified circuit. The switched capacitor circuit is used to create a multi-leveled dc-link voltage. Therefore, the proposed switched-capacitor circuit differs from the conventional one by not having the reverse blocking diode at the load side or the large filtering capacitor. The regulation of the output current and voltage is realized by unified control of both the inverter and the switched-capacitor stages. Section II will discuss the SVPWM based control algorithm that is being utilized on the Switched-Capacitor design. In addition, a newly proposed Optimal SVPWM method that applies to the switched capacitor device is used to compared with regular SVPWM on how the harmonic distortion factor (HDF) may be affected under the same conditions. Section III explores how transitions among different SVPWM and DPWM methods can be achieved by following the same mechanism that we used to obtain the Optimal SVPWM algorithm which enables us to switch the state of the control algorithms based on the given Modulation Index. Section IV of this paper presents the simulation results of the HDF with different control algorithms. Lastly, section V draws the conclusion for this paper.

II. MODIFIED OPTIMAL SPACE VECTOR PULSE WIDTH

MODULATION OF SC CONVERTER

The switched-capacitor circuit at Fig. 1 can have two possible states: one when the capacitor is charging = = (1)

and one when the capacitor is discharging

= ; = 2 (2)

= + + (3)

In addition to these options, the other phase legs feature the eight known inverter states. There are fourteen overall feasible states in the SC converter, and they are depicted in the space vector hexagon shown in Fig. 2. One can observe that the states of the SC converter resemble a four-level inverter with phase voltage possibilities {± , ±2 }. To derive the dwell time for each vector, a few assumptions are made. First, in each sector, the four adjacent active vectors and the two zero vectors are used to synthesize

Fig.1: The proposed switched-capacitor voltage boostconverter.

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the reference voltage vector. Second, during the discharge time, the capacitor voltage is assumed to be constant and equal to the battery voltage. Therefore, the dwell time during the discharge time needs to be minimized to allow minimum voltage-drop during the capacitor discharge. Assume that the reference voltage vector V ref can be synthesized using the following virtual vectors:

= + + (4)

where = + (5) and

= + (6) also

= + (7)

With some algebraic manipulation, the following dwell time for the four active vectors can be obtained:

= 1 − (8) = (9) Where

= √3 sin − (10)

and = 1 − (11) = (12)

where = √3 sin (13)

The factor A Є [0,1] is the boost factor and is expressed as follows:

= 0,0 ≤ ≤ √√3 − 1 √ ≤ ≤ √ , (14)

where the modulation is defined as:

= (15)

From this result, it easy to see that when the modulation index ≤ √ . = , = and = = 0 . The

capacitor is maintained in parallel with the de source, and no

discharge occurs at any time. The SC converter operation in this case is identical to the operation of a conventional two-level inverter. The authors refer to this operation mode as abstemious mode.

On the other hand, when √ < ≤ √ , then 0 < ≤ 1,

and the capacitor is charged and disc~ged with a rate proportional to the value of A. The authors refer to this operation mode as gluttonous mode.

When = √ , = = 0, = , = , In this

case, the capacitors are only charged during the zero vector implementation. Therefore, the six-step operation cannot be performed in the gluttonous mode, and the minimum zero vector time must be ensured to maintain the capacitor charge level [2]. The same rules in (9) and (12) can be applied for calculating the dwell times of the vectors in sectors II to VI if modified

for the kth sector is used instead of used in the calculations.

= − − 1 (16)

The space vector sequence should assure that the load line voltage has the quarter-wave symmetry to reduce the even harmonics in their spectra. To reduce the switching frequency, it is also necessary to execute the switching sequence in such a way that the transition from one to the next is performed by switching only one inverter leg at a time. For instance, if the reference vector falls in sector I, the switching sequence is shown in Fig. 3. The capacitor discharge intervals are placed in the middle of the active vectors intervals to maintain the switching of only one inverter leg at a time.

R1t000

A

B

C

Ts

AB

AC

BC

D

R2t11/2 T111 (1-R3)t22/2R2t12/2 R3t21/2 R3t22/2 (1-R3)t21/2 (1-R2)t12/2 (1-R2)t11/2 (1-R1)t000

(0000) (1000) (1001) (1101) (1100) (1110) (1100) (1101) (1001) (1000) (0000)

Ripple Current

Ripple Current

Ripple Current

Average Voltage

Average Voltage

Average Voltage

VDC

2VDC

VDC

2VDC

2VDC

VDC

Fig 3. Current ripple in the first sector with the switched-capacitor voltage boost converter. With the SVPWM (HRPWM) implemented into the Switched-Capacitor converter, the relations between T000, Tx and Ty and their symmetrical opponents are controlled by three random variables R1, R2 and R3 on the interval [0,1]. In addition, the random variable R0 which rest on the interval [0,1]. controls the ratio of two zero-vectors T000 and T111 which gives the ratio of as the following:

Fig. 2: Space vector hexagon for SC converter with the annotated switching states in the order of (Sg, , , ).

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= 1 − (17) and

= (18)

The general equation to obtain harmonic distortion factor is stated as:

= + + (19)

where a, b and c are the complicated functions of , , and . Since the goal was to search for the values in R that creates the least harmonic distortion, these four random variables can be experimented with different values in order to achieve the lowest value of F(M). While the system is operating, different values of , , and are constantly varying to seek for the lowest HDF for every modulation index [3]. This method is called Optimal Space Vector Pulse Width Modulation, with SVPWM and DPWM being the special cases for such operation. Specifically, the HDF of the regular SVPWM can be obtained by setting the R0=R1=R2=R3=0.5, and the expression for its HDF can be seen as the following: = 2716 − 81√364 − 4√3 + 32

(20) Similarly, we may also obtain specialized cases such as

DPWMMAX or DPWMMIN by changing the value of R0 to 0 or 1 while maintaining R1, R2 and R3 at the value of 0.5. The HDF expressions are shown as the following:

= 278 + 81√364 − 35√32 + 6

(21) By comparing the result among the HDF of SVPWM as well as DPWM cases, the HDF reaches its minimum value when the value of R0,R1,R2 and R3 are all situated around 0.5 as shown in Fig.4, which is why the SVPWM method is widely applied in all types of operations.

III. TRANSITIONS BETWEEN SVPWM AND DPWM

ALGORITHMS

Simulations and experiments have shown that under lower modulation index, SVPWM method express the lowest HDF. While among the higher modulation indexes, certain DPWM algorithms can achieve lower HDF comparing to SVPWM. Previous applications of control algorithms have all consist of operations with a single type of Pulse Width Modulation. With the implementation of random variable , , and

, the control methods on one converter can transition between SVPWM and DPWM by simply changing the value that is assigned to the four R variables. Theoretically, this can enable inverters to adopt SVPWM at lower Modulation index while DPWM at higher modulation index which achieves the merit of having the best harmonic distortion factor at any modulation index value.

IV. SIMULATION RESULTS

The simulation result was conducted based on MATLAB model of the SC converter shown in Fig. 1. Fig. 5 shows the phase currents and the phase voltage for the symmetrically sampled SVPWM.

Fig 5. Simulation Result for the Naturally Sampled SVPWM.

Fig 6. Simulation Result for the DPWMMAX

Fig 4. Value of four random variables that constructs theOptimal SVPWM with the lowest HDF and the possibilitiesof DPWMMAX with these variables.

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Fig. 6 shows the phase currents and the phase voltage for the DPWM max. Note that the transition can be made continually by changing the valued of R. Fig. 7 shows the simulation waveforms for the proposed optimal SVPWM for the switch capacitor converter. The on-time intervals within the sampling time are adjusted in a way that satisfy the minimization of the harmonic distortion factor of the output current.

V. CONCLUSION

In this paper, a newly proposed generalized optimal SVPWM control algorithm for the switched-capacitor voltage boost converter is presented. First, the switching functions are relaxed based on four variable that describes the location of the of the ON time within the sampling interval. Monti Carlo simulation indicated that a harmonic distortion factor lower than the one obtained by the conventional SVPWM can be achieved. Furthermore, the proposed control method allows the transition between various SVPWM method to maintain improved harmonic distortion factor across the entire load profile. This feature can be very useful for electric vehicle drive application. In the near future, the control algorithm will be implemented in hardware to further support the findings.

REFERENCES

[1] A. Janabi, B. Wang, "Switched-Capacitor Voltage Boost Converter for Electric and Hybrid Electric Vehicle Drives," in IEEE Transactions on Power Applications, in press.

[2] A. Janabi, S. Wang and B. Wang, "Switched-Capacitor Bidirectional Voltage Buck-Boost dc-ac Converter with Single SiC Leg," 2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Raleigh, NC, USA, 2019, pp. 71-74.

[3] Chen, Guoqiang & Zhang, Mingjun & Zhao, Junwei. (2012). Harmonic Distortion Factor of A Hybrid Space Vector PWM Based on Random Zero-vector Distribution and Random Pulse Position. INTERNATIONAL JOURNAL ON Advances in Information Sciences and Service Sciences.

Fig 7. Simulation Result for the proposed Optimal SVPWM

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