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High Speed and Low Power Analog to Digital Data Converters for UWB. By: Ali Mesgarani Electrical and Computer Engineering University of Idaho. Outline. Motivation and goals Background New ADC topologies proposed for high speed, low power and medium resolution - PowerPoint PPT Presentation
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Slide 1
High Speed and Low Power Analog to Digital Data Converters for UWB
By: Ali Mesgarani
Electrical and Computer Engineering
University of Idaho
1
Outline
Motivation and goals
Background
New ADC topologies proposed for high speed, low power and medium resolution
Asynchronous binary search ADC
Pipeline binary search ADC
Conclusion
2
Motivation
ADCs are key design blocks in modern microelectronic systems.
More signal-processing functions are implemented in the digital domain.
Noise immunity
Low power
Easy to design using CAD tools
Reproducibility,
Todays high speed communication systems have increased the demand for increased data rates, small area, and low power consumption.
High speed ADCs have significant importance in todays digital signal processing and communication systems.
Designing energy efficient A/D converters by developing new architectures and circuits to take full advantage of what the modern process technologies have to offer.
3
Outline
4
Motivation and goals
Background
New ADC topologies proposed for high speed, low power and medium resolution
Asynchronous binary search ADC
Pipeline binary search ADC
Conclusion
Why do we need A/D converters?
The real world is analog, but easier to process digital data.
Speech, image,
Digital data needs to be carried on an analog signal
Signal received at the antenna must be digitized.
Analog signals contain too much unnecessary amount of data
ADC samples the data and splits it into finite information
ADC converts analog information to digital information
5
ADC at receiver in a link
6
ADC
DAC
Analog to digital converter (ADC)
7
Quantization
8
1 2 3 4 5 6 7 8
Time
111
110
101
100
011
010
001
000
Digital Output
High speed ADC applications
Ultra Wide Band (UWB) communication
High Speed Serial Links
Digital Oscilloscope
Hard Disk Drive Read-Channel
Digital TV
Wireless Personal Area Network (WPAN)
Software Defined Radio
9
High speed ADC applications
ReferenceResolution (bits)Speed (GS/s)Power (mW)ApplicationPark, CICC065.03.50227.0UWBChan, JSSC087.05.00-UWBVerbruggen, JSSC106.02.602.2UWBHarwood, ISSCC 074.512.50-Serial linksCao, JSSC 106.010.0010000.0Serial linksUyttenhove, JSSC 03 6.01.30545.0Hard disk drive read-channelCao, ISSCC 086.01.30600.0Hard disk drive read-channelPoulton, ISSCC 028.04.004600.0Digital oscilloscopePoulton, ISSCC 038.020.0010000.0Digital oscilloscopeSchvan,ISSCC 810.01.35420.0Digital TVVan der Plas,ISSCC 064.01.252.5WPAN10
ADC topologies
Flash
Pipeline
Successive Approximation Register (SAR)
Sub-ranging
Ramp
Single slope
Dual slope
Delta-Sigma
11
Flash ADC
N-bit flash: 2N -1 comparators
Vin connected with 2N -1 comparators in parallel
Comparators connected to resistor string
12
Flash ADC pros and cons
Pros
Very fast
Cons
Area and power increase exponentially with resolution
Input capacitive loading on Vin
Noise
Offset
Jitter sensitivity
13
Pipelined A/D converters
Widely used where high resolution and high throughput is required
A pipeline A/D converter is a multi-step amplitude quantizer
Cascade of stages of low-resolution analog-to-digital converters
Trades latency for speed
14
Pipeline A/D converters
15
Coarse quantizer
Pipeline A/D converter Pros and Cons
Pros
High throughput
Easy upgrade to higher resolutions
Cons
Latency
High demands on speed and gain of amplifier(s)
High power
16
SAR ADC
Based on binary search
Consisted of a comparator, N-bit DAC, binary search logic
Compare VD/A with input signal Vin
Modify VD/A by D0D1D2DN-1 until closest possible value to Vin is reached
Sequential converter
17
Successive Approximation
Register (SAR) ADC
Successive Approximation Register ADC
17
3-bit SAR ADC example
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SAR ADC pros and cons
Pros
Small area
Low power
Cons
Low speed: N clock cycle for N-bit SAR ADC.
Complex clock generation at high sampling rates:
A 6 bit 300MS/s SAR ADC requires 2.1 GHz clock generator with low skew.
Clock generator consumes more power than the ADC itself!
19
Resolution vs sampling rate of ADCs
SAR ADCs are the most energy efficient ADC topologies but low speed
Can we design ADCs with efficiency of SAR and speed of flash converters.
20
20
Asynchronous SAR ADC
Problems with SAR
The logic delay in the feedback takes up to 75% of clock cycle
Complex clock generation
Solution: Asynchronous SAR/Binary Search ADC
No complex clock gen.
No binary search logic
21
0
1
1
0
4.5/8
0
1
ABS ADC
21
Asynchronous SAR ADC
Unroll feedback loop
N comparators are used.
Asynchronous clock is generated from MSB to LSB.
Speed is limited by N comparator delays and DAC delays
22
Asynchronous SAR pros and cons
Pros
Can operate faster than conventional SAR
No need for high speed clock generation
Cons
Offset between comparators
High resolution cannot be achieved like SAR because of the offset.
Larger area
23
Outline
24
Motivation and goals
Background
New ADC topologies proposed for high speed, low power and medium resolution
Asynchronous binary search ADC
Pipeline binary search ADC
Conclusion
Proposed ADC topologies
Asynchronous topologies
2-bit/stage Asynchronous Binary Search (ABS) ADC
Hybrid topologies
Pipeline Binary Search (PBS) ADC
25
Proposed ADC topologies
Asynchronous topologies
2-bit/stage Asynchronous Binary Search (ABS) ADC
Hybrid topologies
Pipeline Binary Search (PBS) ADC
26
2-bit/stage ABS ADC
In a typical asynchronous SAR/binary search ADC speed is limited by N comparator, N DAC delays
How to speed up?
Resolve two bits in each stage (2-bit flash)
Speed limited by N/2 comparator delays and DAC delays.
Speed improvement by two times
Penalty
Power consumption increases by 1.5 times
27
2-bit/stage ABS ADC Operation
Use a 2bit flash quantizer in each stage (3 comparators)
Break the reference into 4 intervals.
Combines sub-ranging and asynchronous processing ideas.
Break the flash ADC operation into multiple steps
28
=9.5/16
=9.5/16
=9.5/16
=9.5/16
=9.5/16
=9.5/16
Asynch. CLK
Asynch. CLK
Asynch. CLK
0
28
2-bit/stage ABS ADC implementation
29
2-bit/stage ABS ADC simulation result
30
ParametersValueProcessRF CMOS, IBMFeature size (nm)90Resolution (bits)6Supply (V)1.2Sampling rate (MS/s)900SNDR (dB)35.82Power (mW)3.8FoM (fJ/conv.step)75Proposed ADC topologies
Asynchronous topologies
2-bit/stage Asynchronous Binary Search (ABS) ADC
Hybrid topologies
Pipeline Binary Search (PBS) ADC
31
Pipelined Binary Search ADC
How can we further speed up the binary search operation of Successive Approximation Register ADC?
Can we operate the Successive approximation algorithm in pipeline fashion?
By combining SAR and Pipeline architectures better performance than proposed ABS ADC were achieved.
Two new topologies of PBS are developed.
32
Pipeline Binary Search (PBS) ADC
SAR-ADC loop has to be unrolled.
Sampled input signal has to be delayed by an analog delay line.
N-comparators and (n-1) digital to analog converters (DACs) have to be used
Speed is limited to 1 comparator delay and DAC delays
How to delay an analog signal?
33
How to delay the analog signal?
Digital delay can be easily implemented using a D-latch or DFF
Analog delay line is implemented by interleaved sampling of the analog signal
Example: 2-clock cycle analog delay
34
6 bit, PBS ADC Circuit Implementation
No opamp is used in this pipeline ADC
Lower power, higher speed
35
Layout for the PBS1 ADC
36
DACs
Comparator
Sample&Holds
Clock ditribution
R-String
Simulation result for PBS1 ADC
37
ParametersValueProcessLLLVT CMOS, UMCFeature size(nm)65Resolution (bits)6Supply (V)1.2Sampling rate (GS/s)1.5SNDR (dB)35.6Power (mW)5.8FoM (fJ/conv.step)78Comparison with state of the art ADCs
ISSCC8JSSC10TCAS I10CICC 10This work:PBS I ADCThis work:ABS ADCTechnology (nm)1306565406590Resolution (bits)665666# of channels221111Sampling Rate (GS/s)1.201.000.701.251.201.500.90Peak SNDR (dB)35.031.529.030.536.035.836.1SNDR (dB) 28.028.026.926.535.635.635.8Power (mW)32.06.32.06.14.85.84.3Supply (V)1.01.21.01.01.21.2FoM (fJ/cs)98021011617881787438
Summary
High speed and low power analog to digital converters are essential part of many communication and signal processing applications
In this research new ADC topologies that take the advantage of energy efficiency of SAR ADCs while enabling high speed operation compared with conventional SAR ADCs architectures is proposed.
A new 2 bit/stage ABS ADC was introduced
Twice as fast as conventional ABS ADCs
A new ADC concept and implementation (PBS ADC) was introduced
Enables binary search operation in a pipelined fashion
Application of asynchronous ADCs as quantizers for high resolution ADCs
39
Thank you for your attentionQ&A
40
Sample
& Hold
Quantization
f
sample
Analog
Digital
000
001
010
011
100
101
110
111
8refV
D
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in
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V
ref
Over range
D
0
D
1
D
N-1
(2
N
-1) to N
encoder
R/2
R
R/2
R
R
R
R
R
R
S&H
Logic
DAC
D
0
D
1
D
N-1
V
in
V
ref
V
D/A
S&H
Logic
D0
DAC
D1
DN-1
Vin
Vref
VD/A
Iterations
inV8refV48refV78refV
1.2.
final
result
V
D/A
100
110
010
111
101
011
001
111
110
101
100
011
010
001
000
3.
1
1
10/16
9/16
8/16
0
1a
1b
SH
+
-
-
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1a
1b
SH
+
-
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+
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1b
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V
in
V
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V
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48
64
32
64
16
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V
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V
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V
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d5,d4
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2b
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2b
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en3,en3b
d
3
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2
d1,d0
Resistive Ladder
Set1[0..3,0..2]Set2[0..15,0..2]
V
ref,HI
V
ref,LO
1a
1b
en
2
en
3
d
5
d
4
XXXXd
5
d
4
d
3
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2
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5
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