GHz Sampling Design Challenge - SourceForgewelecw2000a.sourceforge.net/docs/datasheets/NI-GHz...LMH6555/6552 LMH6515 /LMH6505 ADC08D1000/A DC08D1500 DAC124S101 Key pad Memory + _ LMH7220

1

GHz Sampling Design

Challenge

2© 2008 National Semiconductor Corporation

Target ApplicationsTest & MeasurementCommunications TransceiversRanging Applications (Lidar/Radar)

Set-top box direct RF down-conversion

Highest PerformanceHighest Dynamic PerformanceLowest Power ConsumptionInnovative Packaging technologyWide Bandwidth

National SemiconductorGhz Ultra High Speed ADCs


ADC081000

ADC08D1000

ADC08D500

ADC081500

ADC083000 3 GHz BWDDR, SBI

ADC08B3000 4K Buffer w/CMOS outputs

ADC08500

ADC08D10202 GHz BW

DES, DDR, SPI

SP

EE

D

Single Channel Dual Channel

ADC08D1500

http://www.national.com/appinfo/adc/ghz_adc.html

ADC08D15202 GHz BW

DES, DDS, SPI

8bit GSPS Family

Today


JFET

Ch 2

JFETCh 1

LMH6702 /3LMH6555/6552

LMH6515 /LMH6505 ADC08D1000/A

DC08D1500

DAC124S101

Key pad

Memory

+_

LMH7220/ LMH7322

DAC

Power Trigger

LMH6570

+_

DAC

DAC

DACTrigger

PLL+VCO

VCM

LMX2531

FPGA

CPUDisplayDiffVGAMuxBuff

Digital Oscilloscope Block Diagram

5

The Clock Circuitry

ADC08DxxxCircuit Design Considerations


Jitter: cycle-to-cycle variation in timing

Clock Jitter

Sample amplitude variation due to Jitter

InputSignal

ADCclock

Result: Output noise

Clock Jitter


Effect of Jitter

Sampled with “clean” Clock Sampled with Jittery Clock


High-Speed ADC Clock Considerations

• Maximum allowable jitter to prevent noise degradation:

• “ADC Resolution” & “Signal input frequency” have directly effect upon jitter-induced noise

tjmax =VIN(P-P)

2(n+1) * VFS * π * fin


0.001

0.010

0.100

1.000

10 100 1000 10000

Fu ll Scale In pu t Frequ en cy (MH z)

Jit

ter

(ps

)

16-Bit

14-Bit

12-Bit

10-Bit

169 MHz Input to ADC

To realize 12-bits of resolution for the ADC12DS065, the total aperture jitter must be less than 0.33 ps.

0.33 ps RMS Jitter

Data Converter ENOBFull Scale Input Bandwidth vs. Total Jitter


System Requirement to Clock Jitter


Spectral Considerations

Spurs that extend to higher frequencies may be visible and directly impact system jitter


* R12 & R13 is populated only for the ADC083000 and the ADC08B3000R15 is zero Ohms, R12 & R13 are open for others like ADC081500, ADC08D1500, ADC08D1520

1:2 Impedance

RatioBalun

C144.7nF

C154.7nF

Y1CLKOSC

3.3V

C31uF

C1100pF

C2100nF

R2150

R3 39

R4150

R549.9

C4100nF

R70.22

C6100nF

C810nF

C90.47uF

LD Control input from FPGA

C150100pF

3.3V

C166100nF

SDATASCLK

PLL_LEPLL_CE

R232.2k

R2014.3k

C25100nF

3.0V

3.0V

C17100nF

C184.7uFR113.3k

C19100nF

C7100pF

R13 *100

C16100pF

3.0V

C10100pF

3.0V

C110.47uF

R80.22

R912K

R101kC12

0.15uF

C13220pF

123456789

272625242322212019373839

10

11

12

13

14

15

16

17

18

36

35

34

33

32

31

30

29

28

U3LMX2531LQ1500E

R12 *100

R15 *71.5

Crystek# CCHD-950-25-60

60 MHz

to ADC CLK+

to ADC CLK-

To ADC

LMX2531LQ1500E Simplifies the PLL+VCO clock system


LMX2531 Phase Noise and jitter Performance

14

Effects of Time Interleaving


Correct Relative Clock Phasing

• Samples are in the proper place.

Sampled Signal

CLOCK forADC1

CLOCK forADC2


Incorrect Relative Clock Phasing

• Incorrect timing results with incorrect relative clock phasing

Sampled Signal

CLOCK forADC1

CLOCK forADC2


Distortion is the Result

• We get distortion when combining the data from time interleaved converters.

Reconstructed Signal

Read CLOCK forADC1 Data

Read CLOCK forADC2 Data


ADC08Dxxxx Block Diagram


Dual-Edge Sampling (Interleaving)


Offset Error Difference

• Spurs produced at fS/M

“M” is 1 to one less than the number of converters

Interleaved ADCs with 3 LSB offset spread (8 bit ADC)


Gain Error Difference

• Spurs atfs ± fIN

Interleaved ADCs with 3 LSB Gain Error spread (8bit ADC)


DNL Error Differences

• DNL differences raises the noise floor

Interleaved ADCs with DNL Error differences (8bit ADC)


Temperature Effect and On Command Calibration

ENOB vs. Junction Temperature, 249 MHz Input in ADC08D1000


• Calibrated ADC08D1500• DES (Dual Edge Sampling) Mode

National’s Ultra High Speed ADCs –Interleaved with Calibration


Circuitry for external

clock is much simplified.

Programmable Clock Phase Adjustment

ADC083000 / ADC08D1520/1020The simplified 6GSPS sampling system


ADC1 Input Clock

ADC1 Sample Edges

ADC2 Input Clock

• In SPI mode, the customer can program a delay on the ADC input clock to shift the sample clock phase relative to another ADC08B3000 so that two ADCs may be board-interleaved for a higher system sample rate. Ex. 1.25 GHz input clock: 2.5 GSPS per ADC (Auto DES), and now 5 GSPS through interleaving.

• The phase shift will only be in one direction, eg. increasing delay. The customer should determine which of two discrete ADCs is "ahead" and adjust its phase so that its sample edges are 180º between the other ADC's sample edges, as shown below:

ADC2 Sample Edges

Interleaved samples (non-adjusted)

Interleaved samples (adjusted)

ADC083000 / ADC08D1520/1020Programmable Clock Phase


Main Interleaving Challenges

• Sampling Clock phase adjustment– Normally for 2X interleaving ADC clocks must be time shifted by ½

clock period. But because the ADC083000 is an interleaved architecture, the clock frequency is half the sample rate, 1.5 GHz for 3GSPS. Therefore ADC input clock must be time shifted by ¼ clock period.

• Gain and offset mismatching– Gain & offset of each ADC input stage must be accurately matched.

• Synchronisation of digital outputs– ADC digital outputs must be synchronised for data capture.


Interleaving Challenges

• Sampling Clock phase adjustment

The clock phase can be adjusted manually through the Coarse & Fine registers (Eh and Dh).

Coarse Adjust Magnitude. Each LSB results in approximately 70ps of clock adjust.

Fine Adjust Magnitude. 9-bit, 512 steps gives 110ps adjustment so each LSB results gives approximately 0.2ps of non-linear clock adjust.

See datasheet for more details…


Interleaving Challenges :Gain and Offset Mismatching

• Gain & offset of each ADC input stage must be accurately matched.

• Up to 512 step adjustments in Full Scale Range over a nominal range of 560 mV to 840 mV. The input full-scale voltage or gain of the ADC can be adjusted linearly and monotonically with a 9-bit data value. The adjustment range is ±20% of the nominal 700 mVp-p differential value.

• Separate ±45 mV adjustments in 512 steps of offset adjustment range. The input offset of the ADC can be adjusted linearly and monotonically from a nominal zero offset to 45 mV of offset. Thus, each code step provides 0.176 mV of offset.


• ADC digital outputs must be synchronised for data capture.

• National Giga-sample series ADCs have the capability to precisely reset its sampling clock input to DCLK output relationship as determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time with respect to the shared CLK input that they all use for sampling.

Interleaving Challenges :Synchronisation of Digital Outputs

31

The Amplifier Front-End



DC Coupled DesignSingle Ended Differential Conversion

The Test & Measurement industry requires a DC coupled front-end design.

The easiest approach is to use a differential amplifier with the appropriate gain bandwidth product and the ability to set the common mode output voltage (VCMO) from an external voltage.

LMH6552, LMH6555


More Gain Needed?Adding a Pre-Amplifier to the design

Two Stage Amplifier Input Stage

Wide band differential Op-Amps usually have limited gain, so depending on the application it may be necessary to add a pre-amplifier to the design to meet the necessary gain requirement as shown in this slide.

Fixed Gain


Features• Current Feedback Amplifier• 1.2 GHz bandwidth• 51 dBc THD at 750 MHz• 15 dB noise figure• 13.7 dB fixed gain• DC-Coupled Operation • 3.3V operation• Ideal match for 8-bit ADCs up to 1.5

GSPS, such as the ADC081000/1500 family

Applications• High BW Instrumentation• Differential ADC driver • Single ended to differential converter• Intermediate frequency (IF) amplifier• Communication receivers• Oscilloscope front end

LMH65551.2 GHz Fully Differential Amplifier


• 1.5 GHz SSBW (Av=1, RL=1kΩ, 0.2 Vpp)

• 1.25 GHz LSBW (Av=1, RL=1kΩ, 2Vpp)

• 450 MHz 0.1dB Flatness

• 500Ω load or lighter

• 3850 V/μs Slew Rate

• 10ns settling time to 0.1%

• −90 dB THD @ 20 MHz

• -74 dB THD @ 70 MHz

• 10 dB Noise Figure

• Single 5V, +/-3V or +/-5V operation

• Ideal Driver for 8 to 14 bit High Speed ADCs

• SOIC-8 and LLP-8 Packages

Gain (V/V) SSBW LSBW2 930 MHz 820 MHz4 810 MHz 740 MHz8 590 MHz 590 MHz

LMH6552 (RL=500Ω)

LMH6552 1.5 GHz Fully Differential Amplifier


Target Specs / Feature• RSPECL Output• Prop Delay (≥100 mV OD) 750 ps• Dispersion (10 mV OD) 75ps• Dispersion (100 mV OD) 5ps• Rise and Fall Times 150 ps• Max Toggle Rate 4Gbps• Supply Current ~17.8 mA/ch• Adjustable hysteresis 1 mv to100 mv• Rail-to-Rail Input• Supply Voltage 2.7V to 12V• Extended Temp Range -40ºC to +125ºC • Package 24-LLP

Separate supplies for level shifting applications --->

Ch. A

Ch. B

Trigger Solution : LMH7322 High Speed Comparator w/RSPECL Output

37

The Digital Data Capture (into an FPGA)



NOTE: Advantages of LVDS…• LVDS allows for faster signals (smaller swing), • Lower EMI and switching noise, • Transmit data further

LVDS Signal Transmission


About Measurement Description in Specification

Sine or Square Wave ClockDefined measured differentiallyDifferential Clock Input Level

OutV=Gndsmaller amplitude

OutV=Vanormal amplitude

Measured differentiallyLVDS Data Output Voltage

LVDS Differential and Single Ended Signal measurements.So for example, 700 mV in differential means 350 mV each side.


ADC08Dxxxx Block Diagram


DDR & SDR


FPGA Internal Clock Manager

Data Capture Implementation Block Diagram

FPGA Data Capture Implementation


ADC08D1020/1520 Block Diagram

1:1 or 1:2 selectable DEMUX FPGA

Provide LVDS test mode

44

Documents

GHz Sampling Design Challenge - SourceForgewelecw2000a.sourceforge.net/docs/datasheets/NI-GHz...LMH6555/6552 LMH6515 /LMH6505 ADC08D1000/A DC08D1500 DAC124S101 Key pad Memory + _ LMH7220