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Fundamentals of Computer SystemsA Single Cycle MIPS Processor
Stephen A. Edwardsand
Martha A. Kim
Columbia University
Fall 2012
Illustrations Copyright 2007 Elsevier
The DatapathThe lw InstructionThe sw InstructionR-Type InstructionsThe beq Instruction
The ControllerInstruction EncodingThe ALU DecoderThe Main DecoderThe j Instruction
Processor PerformanceThe Critical Path
Lets Build a Simple Processor
Supported instructions:
R-type: and, or, addu, subu, slt Memory instructions: lw, sw Branch instructions: beq
Version 2.0:
I-type: addiu J-type: j
MIPS State ElementsThis is the programmer-visible state in the ISA
CLK
A RD
Instruction
Memory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Register
File
A RD
Data
Memory
WD
WEPCPC'
CLK
32 32
32 32
32
32
3232
32
32
5
5
5
ALU Interface and Implementation
ALU
N N
N3
A B
Y
F
F2 F1 F0 Func.
0 0 0 A & B0 0 1 A | B0 1 0 A + B0 1 11 0 0 A & B1 0 1 A | B1 1 0 A B1 1 1 A < B (slt)
+
2 01
A B
Cout
Y
3
01F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
ZeroExtend
Datapath Elements for the lw InstructionFetch instruction from instruction memory:Send the PC to the instruction memorys address
CLK
A RDInstructionMemory
A1
A3WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RDData
MemoryWD
WEPCPC' Instr
CLK
lw rt, offset(base)
LW base rt offset1 0 0 0 1 1
Datapath Elements for the lw InstructionRead the base register
Instr
CLK
A RDInstructionMemory
A1
A3WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RDData
MemoryWD
WEPCPC'
25:21
CLK
lw rt, offset(base)
LW base rt offset1 0 0 0 1 1
Datapath Elements for the lw InstructionSign-extend the immediate
SignImm
CLK
A RDInstruction
Memory
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RDData
MemoryWD
WEPCPC' Instr 25:21
15:0
CLK
lw rt, offset(base)
LW base rt offset1 0 0 0 1 1
Datapath Elements for the lw InstructionAdd the base register and the sign-extended immediateto compute the data memory address
SignImm
CLK
A RDInstruction
Memory
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RDData
MemoryWD
WEPCPC' Instr 25:21
15:0
SrcB
ALUResultSrcA Zero
CLK
ALUControl2:0
ALU
010
lw rt, offset(base)
LW base rt offset1 0 0 0 1 1
Datapath Elements for the lw InstructionRead data from memory and write it back to rt in theregister file
A1
A3WD3
RD2
RD1WE3
A2
SignImm
CLK
A RDInstruction
Memory
CLK
Sign Extend
RegisterFile
A RDData
MemoryWD
WEPCPC' Instr 25:21
15:0
SrcB20:16
ALUResult ReadDataSrcA
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
lw rt, offset(base)
LW base rt offset1 0 0 0 1 1
Datapath Elements for the lw InstructionAdd four to the program counter to determine addressof the the next instruction to execute
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RDData
MemoryWD
WEPCPC' Instr 25:21
15:0
SrcB20:16
ALUResult ReadDataSrcA
PCPlus4
Result
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
lw rt, offset(base)
LW base rt offset1 0 0 0 1 1
Additional Elements for swRead rt from the register file and write it to datamemory
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RDData
MemoryWD
WEPCPC' Instr 25:21
20:16
15:0
SrcB20:16
ALUResult ReadData
WriteData
SrcA
PCPlus4
Result
MemWriteRegWrite
Zero
CLK
ALUControl2:0
ALU
10100
sw rt, offset(base)
SW base rt offset1 0 1 0 1 1
Additional Elements for R-Type InstructionsRead from rs and rt
Write ALUResult to rd (instead of rt)
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PCPC' Instr 25:21
20:16
15:0
SrcB
20:16
15:11
ALUResult ReadData
WriteData
SrcA
PCPlus4WriteReg4:0
Result
RegDst MemWrite MemtoRegALUSrcRegWrite
Zero
CLK
ALUControl2:0
ALU
0varies1 001
addu rd, rs, rt
SPECIAL rs rt rd ADDU0 0 0 0 0 0 1 0 0 0 0 10 0 0 0 0
Additional Elements for beqDetermine whether rs and rt are equal
Calculate branch target address
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
SrcB
20:16
15:11
Add a controller to complete it
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
R-Type Instruction Encodingaddu rd, rs, rt
SPECIAL rs rt rd ADDU0 0 0 0 0 0 1 0 0 0 0 10 0 0 0 0
subu rd, rs, rt
SPECIAL rs rt rd SUBU0 0 0 0 0 0 1 0 0 0 1 10 0 0 0 0
and rd, rs, rt
SPECIAL rs rt rd AND0 0 0 0 0 0 1 0 0 1 0 00 0 0 0 0
or rd, rs, rt
SPECIAL rs rt rd OR0 0 0 0 0 0 1 0 0 1 0 10 0 0 0 0
slt rd, rs, rt
SPECIAL rs rt rd SLT0 0 0 0 0 0 1 0 1 0 1 00 0 0 0 0
The ALU Decoder
RegDst
BranchMemWriteMemtoReg
ALUSrcOpcode5:0
ControlUnit
ALUControl2:0Funct5:0
MainDecoder
ALUOp1:0
ALUDecoder
RegWrite
Part of the control unitresponsible forimplementing the opcodeFunct field.
ALU Funct ALU ALUOp Ctrl. Function
00 010 Add-1 110 Subtract1- 100001 010 Add1- 100011 110 Subtract1- 100100 000 AND1- 100101 001 OR1- 101010 111 Slt
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000lw 100011sw 101011beq 000100
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000 1 1 0 0 0 0 1-lw 100011sw 101011beq 000100
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000 1 1 0 0 0 0 1-lw 100011 1 0 1 0 0 1 00sw 101011beq 000100
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000 1 1 0 0 0 0 1-lw 100011 1 0 1 0 0 1 00sw 101011 0 - 1 0 1 - 00beq 000100
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000 1 1 0 0 0 0 1-lw 100011 1 0 1 0 0 1 00sw 101011 0 - 1 0 1 - 00beq 000100 0 - 0 1 0 - 01
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000 1 1 0 0 0 0 1-lw 100011 1 0 1 0 0 1 00sw 101011 0 - 1 0 1 - 00beq 000100 0 - 0 1 0 - 01
addiu 001001 Can we do this with our datapath?
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Main DecoderInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp
R-type 000000 1 1 0 0 0 0 1-lw 100011 1 0 1 0 0 1 00sw 101011 0 - 1 0 1 - 00beq 000100 0 - 0 1 0 - 01
addiu 001001 1 0 1 0 0 0 00
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
Additional Elements for the j InstructionInst. OP RegWrite RegDst ALUSrc Branch MemWrite MemToReg ALUOp Jump
R-type 000000 1 1 0 0 0 0 1- 0lw 100011 1 0 1 0 0 1 00 0sw 101011 0 - 1 0 1 - 00 0beq 000100 0 - 0 1 0 - 01 0
addiu 001001 1 0 1 0 0 0 00 0j 000010 0 - - - 0 - -- 1
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
Processor Performance
Seconds
Program=
Instructions
Program
Clock Cycles
Instruction
Seconds
Clock Cycle
SecondsProgram How long you have to wait
InstructionsProgram Number that must execute to complete the task
Clock CyclesInstruction CPI: Cycles per instruction
SecondsClock Cycle The clock period (1/frequency)
The Critical Path Here: Load from Memory
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
The Critical Path Dictates the Clock Period
Element Delay
Register clk-to-Q tpcq-PC 30 psRegister setup tsetup 20Multiplexer tmux 25ALU tALU 200Memory Read tmem 250Register file read tRFread 150Register file setup tRFsetup 20
SignImm
CLK
A RDInstruction
Memory
+
4
A1
A3WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
01
01
A RDData
MemoryWD
WE01
PC01
PC' Instr 25:21
20:16
15:0
5:0
SrcB
20:16
15:11
Execution Time for Our Single-Cycle Processor
For a 100 billion-instruction task on our single-cycleprocessor with a 925 ps clock period,
SecondsProgram =
InstructionsProgram
Clock CyclesInstruction
SecondsClock Cycle
= 100 109 1 925 ps
= 92.5 seconds
The DatapathThe lw InstructionThe sw InstructionR-Type InstructionsThe beq Instruction
The ControllerInstruction EncodingThe ALU DecoderThe Main DecoderThe j Instruction
Processor PerformanceThe Critical Path