CSEE 3827: Fundamentals of Computer Systems › ~martha › courses › 3827 › sp09 › slides › lecture1314.pdf(e.g., wifi, iPhone) logic gates, boolean algebra flip-flops,

CSEE 3827: Fundamentals of Computer Systems

Lecture 13 & 14

March 25 & 30, 2009

Martha [email protected]

mailto:[email protected]:[email protected]

CSEE 3827, Spring 2009 Martha Kim

The big picture

2

General purpose processor

(e.g., Power PC, Pentium, MIPS)

CL

D Q

Memory

addr

data_in

data_out

r_en

w_en

Internet router(intrusion detection, packet routing, etc.)

WIreless transceiver(e.g., wifi, iPhone)

logic gates, boolean algebra flip-flops, latches

combinational logicsequential logic,

finite state machinesstorage elements

(next)


The rest of the picture

3

Applicationexecutable (e.g., *.exe)

Source code(e.g., *.java, *.c)

Compiler

(hardware)

(software)




… and the rest of the semester

4

Applicationexecutable (e.g., *.exe)

Source code(e.g., *.java, *.c)

Compiler

(hardware)

(software)



MIPS instruction set architecture

Single-cycle MIPS processor

Performance analysis

Optimization (pipelining, caches)

Topics in modern computer architecture (multicore, on-chip networks, etc.)

Registers (M&K 7.1)


Registers

6

A flip-flop can store 1 bit. A register is a set of n flip flops that stores n bits.


Register w. load control input (v1)

7

Encapsulate logic inside register

Send clock signal to flip-flops only when Load=1

This technique is called clock gating


Register w. load control input (v2)

8

Encapsulate logic inside flip-flop

EN signal selects between current value of register (Q) or new value (D)

Preferable to v1 as it leaves clock signal unadultered.


Shift register

9

A register capable of shifting bits laterally in one or both directions


Shift register w. parallel load

10

Three modes:Serial input

Parallel inputNo input



11

Serial input operation(enabled by Shift)



12

Parallel load operation(enabled by Load AND Shift)



13

Do nothing operation(enabled by Load AND Shift)

Memory Arrays (M&K 8.1-8.7)


Address

Read

Enable

DataIn

DataOut

k

n

n

2 wordsn bits per word

k

MEMORY

Memory interface

• Stores data in word units

• A word is several bytes (16-, 32-, or 64-bit words are typical)

• write operations store data to memory

• read operations retrieve data from memory

15

An n-bit value can be read from or written to each k-bit address


Conceptual view of memory

16


Memory array architecture (1)

17

wordline311

10

2:4Decoder

Address

01

00

storedbit = 0wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

bitline2 bitline1 bitline0

Data2 Data1 Data0

2

Memory is a 2D array of bits. Each bit stored in a cell.

cell

Copyright © 2007 Elsevier



18

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

Address is decoded into set of wordlines. Wordlines select row to be read/written. Only one wordline=1 at a time.




19

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

When writing, contents of word written to bitlines.



Memory cell abstraction

20

stored bit

wordlinebitline


wordline stored bit bitline

0 x Z

1 0 0

1 1 1

Cell is base element of memory that stores a single bit

Implementation of cell varies with type of memory.

Implemented with a tristate buffer. Value “Z” does not drive output wire to either a 0 or 1.


Types of memory

Volatile (no storage when power off)

Fast reads and writes

Historically called RAM because equal time to read/write all addresses (in contrast to serial-access devices such as a hard disk or tape). Somewhat misleading as ROM also can have uniform access time.

21

Non-volatile (retains data when powered off)

Fast reads, writing is impossible or slow (again, misleading name)

Historically called ROMs because written by permanently blowing fuses (so rewriting was impossible). Modern ROMs, such as flash memory in iPod are rewritable, just slowly.

Random access memory (RAM) Read-only memory (ROM)

Dynamic RAM (DRAM) Static RAM (SRAM)Cell stores data w. capacitors

Cell stores data w. cross-coupled inverters

wordline

bitline

storedbit

wordlinebitline bitline

ROMMask-programmed (at chip fab)

PROMFuse- or antifuse-programmed

FLASH

Electrically erasable floating gate with multiple erasure and programming modes


Hard Disk

Flip-flop Register


Volatile storage (RAM) comparisons

22

Flip-flop SRAM DRAM

Transistors / bit ~20 6 1

Density Low Medium High

Access time Fast Medium Slow

Destructive read? No No Yes (refresh required)

Power consumption High Medium Low


Storage hierarchy

23

Main memory

(DRAM)

Non-volatile storage

(Hard disk or

solid-state drive)

CPU Cache

(SRAM)Registers

Fast access to small amount of data

Slow access to large amount of data


Bottom-up examination of SRAM circuits

24

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2



Bottom-up examination of SRAM circuits (2)

25

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2


Bits stored in cells (modeled by an SR latch)



26

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

Cells wired into bitslices.




27

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

Block diagram of a bitslice




28

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

Address decoded to select one row of bitslice

for read/write




29

wordline311

10

2:4Decoder

Address

01

00


wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1


Data2 Data1 Data0

2

To increase word size, add bitslices.



Coincident cell selection

30

• Decode address into both row and column select signals

• How many words in this RAM?

• How many bits per word?


Coincident cell selection w. larger words

31

• How many words in this RAM?

• How many bits per word?


Coincident cell selection saves decode logic

32

32K

wor

ds

1 byte

STORAGECOLUMN

15-b

it ad

dres

s

(32,800 gates)

DECODER

512

wor

ds

1 byte9-

bits

of a

ddre

ss

DECODER#1

STORAGE COLUMNS

...

...64 column selects...

… 3

2,76

8 ro

w s

elec

ts ..

.

… 5

12 ro

w s

elec

ts ..

.

DECODER #2

6-bits of address(608 gates)


Multi-chip memories

• If you need a larger memory than any available chip

• Wire multiple RAM chips together to work in concert as one large memory

33

Programmable Logic Devices (M&K 6.8)


Programmable Logic Devices

• Programmable logic devices (PLDs)

• Structured like memories

• Used to implement combinational logic

• “X” on array logic means wire connected to logic gate (e.g. above)

• Connections can be either permanent (e.g., fuse, mask) or not (e.g., Flash)

35

x


...

General PLD architecture

36

Fixed AND, programmable OR = Programmable ROM (PROM)Programmable AND, fixed OR = Programmable Array Logic (PAL)

Programmable AND, programmable OR = Programmable Logic Array (PLA)


Programmable ROM (PROM)

37

Fixed (X) AND, programmable (X) OR

x x x xx x x x

x x x xx x x x

A B C D

m0

...

m1

m14

m15

xx

x

x

x

x x

E F G H


Programmable Array Logic (PAL)

38

Programmable (X) AND, fixed (X) OR

A B C D

...

x

xx

xxx x

x x

x x

xx

xx

x x x

E F


Programmable Logic Array (PLA)

39

Programmable (X) AND, programmable (X) OR

A B C D

...

x

xx

xx

xxx x

x xx x x

x

x

x

x

E F G H

Documents

CSEE 3827: Fundamentals of Computer Systems › ~martha › courses › 3827 › sp09 › slides › lecture1314.pdf(e.g., wifi, iPhone) logic gates, boolean algebra flip-flops,