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TM
Freescale’s Data Converter
Portfolio and Associated Wizardry
(for embedded applications)
FTF-IND-F0202
A P R . 2 0 1 4
Doug Garrity, Ph.D., IEEE Fellow
Fellow and Director – Freescale Data Converter Center of
Excellence
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External Use 1
Agenda
• Introduction
• Nyquist-rate Analog-to-Digital Converter (ADC)
Portfolio and Development/Evaluation Capabilities
• Sigma-delta (SD) ADC Portfolio and
Development/Evaluation Capabilities
• Digital-to-Analog Converter (DAC) Portfolio and
Development/Evaluation Capabilities
• Conclusions
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External Use 2
Introduction
• Freescale has a rich, decades-long legacy of developing high-
performance analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs) for a broad range of embedded applications ranging
from radio receiver/transmitters to energy meters and automotive engine
control, radar and infotainment.
• After a brief description of the various data converter architectures along
with their associated trade-offs, this presentation will describe Freescale's
extensive portfolio of data converter intellectual property. It includes high-
speed, high-resolution DACs and oversampled/Noise-Shaping and
Nyquist-rate ADCs with sample rates ranging from a few hertz to hundreds
of megahertz and resolutions ranging from 8 bits to 24 bits.
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External Use 3
Session Objectives:
After completing this session, you will be able to:
− Appreciate Freescale’s broad data converter portfolio and data converter
development and evaluation capabilities
− Understand the most commonly used data converter architectures and
their advantages/disadvantages
− For a given application space, identify and select an appropriate data
converter architecture that meets critical requirements with minimal
power and cost
− Know who to contact for additional information
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External Use 4
Quantizer
SAMPLER
OUTPUT (binary)
First consider Nyquist-rate ADCs …
Which ADC Architectures Can I Choose From?
Nyquist-rate ADC guidelines/advantages/disadvantages:
• Typically use Fs > 2*Fmax and can achieve the highest possible input bandwidth
• Usually include a sample-and-hold function so that there is one-to-one correspondence between an
input sample and a digital output word
• Can be readily used in a feedback loop and/or with an input mux
• Precision components or calibration typically required to achieve high resolution
• Anti-aliasing filter required (may be demanding because of low sample rate relative to input
bandwidth)
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Nyquist-rate Architectures: 16-bit SAR ADC
• Features
− Successive approximation (SAR)
− 16b resolution
− 1.15V minimum reference
− Automatic compare function
− Triggering synchronization with DAC
− Configurable sample time
− Configurable speed/power
• Key Benefits
− Successive approximation architecture can achieve conversion rates as fast as 0.666µs in 12-b
mode and 2.1ms in 16-b mode
− With averaging, accuracy approaches 14.6 ENOB. Allows accurate measurement of slower or
settled signals even while interleaved or switching channels
− Low-power calibrated DAC architecture saves power and area vs. most competitors’ ADCs
− Self-test method allows production testing of linearity specs at low cost and complexity
− Differential input allows much better noise rejection and accuracy than single-ended
– Differential or single-ended
– Averaging by 1, 4, 8, 16, or 32
– Typical performance of >14 Effective
Number of Bits (ENOB)
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External Use 6
SAR ADC Block Diagram (Single-Ended)
556 DAC
REF DAC
+
-
VREFH VREFL VIN
Calibration
Engine
Calibration
Memory
SAR
Engine
MUX
Accumulator
Subtractor
MSBs
RESULT
VREFL
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External Use 7
SAR ADC Measured Results (16-b mode):
Integral Non-Linearity (INL) -2.5 lsb to +3.5 lsb
Differential Non-Linearity (DNL) -0.6 lsb to +2.5 lsb
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SAR ADC Measured Results (16-b mode):
Signal-to-Noise-and-Distortion (SINAD)
and
Spurious-Free-Dynamic-Range (SFDR)
vs. Input Frequency
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External Use 9
SAR ADC Architecture Performance Ranges 16-b mode
• Performance without averaging: ~12.5b ENOB, -1 to +4 LSB DNL
One time calibration (at initial power-up or production test) required
− Additional calibration (voltage, temperature) not necessary
• Performance with averaging: ~14.5b ENOB, -1 to +2.5 LSB DNL
• Sample rates from ~20 to ~480 ks/s with currently available
implementations
− Sample rates up to 800 ks/s readily achievable with increased power
− Sample rates in 12-b mode approximately double that of 16-b mode
• Power 0.2-1.2mW from 1.7-3.6V based upon power setting
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External Use 10
Nyquist-Rate ADC Architectures: Cyclic RSD*
• Advantages
− No n-bit DAC needed (only ~1.5-bits)
− Comparators (at least 2) are less critical
− Faster: >=1.5 bits per clock phase
− Moderate resolution (12-bits readily achievable without calibration)
• Drawbacks
− 2x gain stage becomes critical (amplifier performance and capacitor matching)
− Trimming and calibration techniques needed for high resolution
• Recent Freescale cyclic ADC example:
− 12-b (10.1 ENOB)
− 10Ms/s
− 15mW (1.5V)
* Redundant-Signed-Digit (RSD) - from Ginetti et al, IEEE JSSC, vol. 27, no. 7, July 1992
Block Diagram
Input
voltage
Output
bits
Data
ready
Output
logic
SW
control
logic
Clk
Trig Timing & Control Logic
Comparator hi
X 2 amp
sw cap
sw cap
comparator lo
vrefp
vrefn
vref/2
> vrefp ?
< vrefn ?
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External Use 11
Fast-Cyclic RSD ADC Conceptual Block Diagram
111.11ns conversion time (including sampling) with master clock running at 3 X 9 MHz = 27 MHz
2.5-bit switch
network 2.5-bit switch
network
Op-amp
Stage 1 Stage 2
P1
P2
Stage # 1 2 1 2 1 2
number of actual bits
determined per clock phase
2 2 2 2 2 2
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External Use 12
Measured Performance Summary
Architecture 2.5-bit cyclic RSD
Sampling frequency 9 MHz
Resolution 12-b
INL/DNL +/-2 lsb and +/- 0.6 lsb respectively
ENOB > 10.1-b
Input range 1.4Vpp-differential
Latency 1 clock cycle (9 MHz) (3 clock cycles of 27 MHz)
Power supply 1.5V
Temperature range -20°C to 85°C
Total power 15 mW
Technology 90 nm CMOS
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Cyclic RSD ADC Architecture Performance Ranges
• Resolutions of 10-12-bits readily achievable without averaging
or calibration. 14-bit to 16-bit resolution achievable with averaging and/or
calibration
• Sample rates from 1 to 20 MHz (conversion times from 1 ms to
50 ns) readily achievable
• Performance previous example: 10-bits, 1 Ms/s, SINAD = 60dB
− Power 1.38 mW from 2.5V
• Performance recent example: 12-bits, 9 Ms/s, SINAD = 63dB
− Power 15 mW from 1.5V
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• Advantages
− No n-bit DAC needed
− Once pipeline is loaded, a new output appears every clock cycle so sample rate = clock rate
− Moderate resolution (12-bits readily achievable without calibration)
− Sample and hold combined with DAC
• Recent Freescale pipelined ADC example:
− 10-bit , 80 Ms/s, 9.4-bit ENOB
− Often used for video or wide-bandwidth radio receivers
Pipelined ADC Architecture
alignment and synchronization
correction
digital out
digital section
stage 1 stage 2input
stage n +-
vmidsupply
Block diagram of an n-bit pipeline RSD A/D converter.
S/H+
-
+
ADC DAC
outputinputG i
MDAC
Bi
Block diagram of a pipelined A/D converter stage
Pipelined ADC Architecture
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External Use 15
high-level block diagram of I/Q sampling ADC architecture:
channel 1 - digital alignment and synchronization block
channel 2 - digital alignment and synchronization block
channel 1 digital data
channel 2 digital data
channel 1 input
channel 2 input
n-bitinputstage
n-bitinputstage
m-bit delayingholdingand synchronizationstage
k-bitmid-rangestages
j-bit final stage
*See article in June 2008 IEEE Journal of Solid-State Circuits
High-Level Block Diagram of I/Q Sampling ADC
Architecture:
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Measured Results:
I and Q channel ADC SNDR Response vs Input Frequency:
Measured Results:
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I/Q ADC: Measured Performance Summary
I-channel ADC Q-channel ADC
Resolution 10-bits 10-bits
Input voltage range 1Vpp differential 1Vpp differential
Peak SNR/SINAD 58.6/56.5 dB 58.6/56.5 dB
DNL +/- 0.5 lsb +/- 0.5 lsb
INL +/- 1 lsb +/- 1 lsb
Sample rate 40 Ms/s 40 Ms/s
Power consumption 25 mW 25 mW
Technology 90 nm CMOS 90 nm CMOS
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External Use 18
Pipelined ADC Architecture Performance Ranges
• Resolutions of 8-12-bits readily achievable without averaging or
calibration. 14-bit to 16-bit resolution achievable with calibration
• Sample rates from 20 to 200 MHz readily achievable
• Performance recent example: 10-bits, 40 Ms/s, SINAD = 56.5dB
− Power 25 mW from 2.5V
• Performance recent example: 12-bits, 25Ms/s, SINAD = 65dB
(simulated)
− Power 61 mW from 3.3V
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External Use 19
Next, consider oversampled noise-shaping (SD) ADCs …
OUTPUT
Digital filter
H(s)
Which ADC Architectures Can I Choose From?
• Oversampled noise-shaping SD ADC guidelines/advantages/disadvantages:
− Typically use Fs >>> 2*Fmax and typically achieve lower input bandwidth (20 MHz with reasonable dynamic range is about state-of-the-art)
− Anti-aliasing filtering is often trivial
− Achieve highest levels of performance (> 20 bit) over a small (i.e. audio) bandwidth
− No precision components or calibration typically required (just a fast clock)
− Digital filters required to remove out-of-band quantization noise
− Input is represented over time, so no one-to-one correspondence between an input sample and a specific digital output word
− Can be readily used with a mux for DC measurements. For AC signals, using a mux before the ADC is more difficult because the digital filters have to be reset and that takes time (a few clock cycles at the final sample rate)
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External Use 20
Quantization noise floor is essentially flat from DC to Fs
Fs Fin
Digital filter response Quantizer
SAMPLER
OUTPUT
Digital filter
Sigma-Delta ADCs: What Are They?
• If we sample faster, the quantization noise is spread over a wider band
• If we’re only interested in a subset of that band, we can gain SNR through digital filtering
• This is the concept of oversampling
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…But How Much Does This Help?
• If we have a 10-bit, 1 MHz ADC that achieves 60dB from DC to 500
kHz, how fast would we need to sample to achieve 102 dB over the
same bandwidth?
• We need an increase in SNR of 42 dB, which is 14 octaves at 3 dB
per octave
• So the sample rate would have to double 14 times to 16.384 GHz!!!
• Since there’s no such thing as a (real) 10-bit, 16.384GHz ADC,
something more than just oversampling is needed:
Noise shaping!
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External Use 22
quantization noise floor is now shaped!
quantizer
OUTPUT
digital filter
H(s)
Fs Fin
Digital Filter Response
Sigma-Delta ADCs: What Are They?
• For even better in-band SNR, through adding an analog loop filter, we can force the quantization noise to be smaller within our band of interest at the expense of larger quantization noise power outside the band. This is the concept of “noise-shaping.”
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External Use 23
ADC Architectures: SD
Noise-shaped Response vs Conventional Nyquist-Rate Converter Response
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External Use 24
Freescale Metering Analog-Front-End (AFE) Block
Diagram:
• ADC dynamic range (PGA gain
=1, 4x averaging) = 18-bit
• With PGA and averaging, AFE
dynamic range = 24-bits
• Output data rate programmable
from 3 kHz to 24 kHz
• Chopper-stabilized PGA
• Gain 1,2,4,8,16, 32, or 64
• Suitable for current sensing
with shunt resistor, current
transformer or Rogowski coil
2nd Order discrete-time SD
ADC (with correlated-double
sampling)
Either
Shunt
Res. Or
Current
XFMR
ADC sample rate > = 6.144MHz
Programmable gain amplifier (PGA)
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External Use 25
Freescale Metering AFE – Measured Performance at a
Glance
• Total current = 4 mA (PGA = 2.6 mA, ADC = 1.4mA)
• Temperature range = -40°C to 85°C
• Total AFE input dynamic range with NO averaging = 20.2 bits (23.3 bits with 64x averaging)
• PGA gain accuracy (all gain settings) = <0.2 dB
• Input referred noise floor with PGA gain set to 64 ~600 nVrms
• Input offset voltage with PGA gain set to 64 = <20 mV
• ADC (stand-alone) input dynamic range (NO averaging) = 17.1 bits
• ADC (stand-alone) peak SNR = 98dB
• ADC input referred noise floor = 6mVrms
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External Use 26
Measured Results: AFE Input Dynamic Range
External reference
filtered with 0.5 Hz
low-pass filter to
remove 1/f noise
8x averaged data
measured for 1mVrms
– other 8x averaged
data and all 64x
averaged data is
extrapolated
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External Use 27
Measured Results: ADC Input Dynamic Range
External reference
filtered with 0.5 Hz
low-pass filter to
remove 1/f noise
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External Use 28
AFE Measured Results:
Conditions:
− Input signal = 1 mVrms
sine wave
− PGA gain = 64
− Chopping on
− No averaging
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External Use 29
Next, Consider Continuous-Time SD ADCs
Why continuous time?
• Wider input bandwidth
• Reduced power
• Elimination of input sampler
• Inherent anti-alias filtering
• Less capacitor-intensive
• Less sensitive to substrate noise
• Generate less noise
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External Use 30
Noise
Shaping
Filter
DAC
X
CLK
Y ADC N
H(s)X NQ
1 + H(s) 1 + H(s) + Y =
Why Continuous Time SD?
In D-T integrators,
OPAMP BW > 5 X
FSAMP
In C-T integrators,
OPAMP BW > FSIG
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External Use 31
Noise
Shaping
Filter
DAC
X
CLK
Y ADC N
H(s)X NQ
1 + H(s) 1 + H(s) + Y =
In D-T modulators,
noise is sampled
here and aliased
In C-T modulators,
noise is sampled
here and shaped
Why Continuous Time SD?
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External Use 32
Example: Wide-Bandwidth Continuous-Time SD ADC for
Automotive Radar
• Continuous-time SD ADC architecture 2nd order feed-back with a 4-bit (17 level)
quantizer for 10Ms/s (after decimation)
Vin Mbit
NRZ CT Current
Array Mbit
NRZ DACs –Jitter Sensitivity
RC Continuous Time Filters (Improved Linearity)
MM
Shaper
NRZ CT Current
Array Mbit
Output Bits
<15:0>
NRZ CT Current
Array Mbit
Z-1
Z-1
Z-1/2
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External Use 33
Automotive Radar Continuous-Time SD ADC:
Measured ADC Frequency Response from 20kHz to 5MHz
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External Use 34
Automotive Radar Continuous-Time SD ADC:
Measured SNR, SNDR vs input frequency
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External Use 35
Automotive Radar Continuous-Time SD ADC:
Measured Interference-Free-Dynamic-Range
(IFDR) > 107dB
• Test conditions:
− ADC (under test) inputs
shorted
− 8 ADCs running
− (at least) one
microcontroller running
− signal processing
hardware running
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External Use 36
Automotive Radar Continuous-Time SD ADC:
Measured (inherent) Anti-Alias Filter Response
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External Use 37
Automotive Radar Continuous-Time SD ADC:
Measured (inherent) Anti-Alias Filter Response
(zoomed in)
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External Use 38
SD ADC Architecture Performance Ranges
• Resolutions of 12-24-bits readily achievable without averaging or calibration all of the highest resolution ADCs and DACs in the
world are SD based. Area is also extremely small …
• Input bandwidths from DC to hundreds of kHz readily achievable. Continuous-time SD ADCs with input bandwidths in the tens of MHz range have been reported (Freescale has one)
• Performance continuous-time (radar): 12-bits, 10 Ms/s, SNR = 67dB
− Power 15 mW from 1.4V, Area 0.37mm2
• Performance metering AFE: 24-bits (with averaging), 3ks/s,
− Power 6 mW from 3.3V, Area 0.16mm2
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External Use 39
High-Speed DAC Architecture: Segmented + r2r
s11s25
2R
R
T1T15
out
outx
out
outx
Ladder_gnd
Vout
s10 s1
2R R
R
B1B10
out
outx
out
outx
s26s35
C9
out
outx
out
outx
C1
25 identical current sources
2 11-tap R-2R ladders
9 binary calDAC currents
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External Use 40
High-Speed DAC Architectures: Segmented+r2r
DAC
(v out)
CAL
DAC2
(i out)
14 bit binary
9 bit binary
CAL DAC1
V to I ref7 bit binary
CALDAC1 provides gain error / DC offset correction (one-time update)
CALDAC2 provides DNL/INL error correction (actively updating)
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External Use 41
High-Speed DAC – Measured Performance Summary
Parameter 14-bit DAC
Process 90 nm CMOS
Area (mm^2) 0.25
Power (mW) 6.3
Gain/offset correction yes
DNL/INL correction yes
DAC noise (uV)
(integrated 100 Hz to 1 MHz)
120
SFDR (dB) / clock (MHz) 72/ no cal (84/ with cal)
Max operating speed (MHz) /
linearity (dBc)
312/63
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External Use 42
General Purpose DAC Features
• 1.71V to 3.6V operation
• 12-bit DAC conversion − Code to code settling time is 1µs
• 16-word DAC FIFO
• Hardware or software trigger to advance the
DAC FIFO pointer (PDB is used to trigger the DAC)
• DAC FIFO Modes of operation − Swing Mode − One Time Scan mode − Normal Mode (circular buffer)
• DAC FIFO interrupts
− Watermark − Top position − Bottom position
• DAC Watermark configuration
− 1-4 words
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External Use 43
General Purpose DAC DNL Across Temperature and VDD
0
0.2
0.4
0.6
0.8
1
1.2
-40 25 55 85 105
DN
L A
bso
lute
(L
SB
)
DAC12 Module 0 Absolute DNL Max
M33Z_01A - 1.62 - High - Vext
M33Z_01A - 1.62 - Low - Vext
M33Z_01A - 1.71 - High - Vext
M33Z_01A - 1.71 - Low - Vext
M33Z_01A - 1.8 - High - Vext
M33Z_01A - 1.8 - Low - Vext
M33Z_01A - 2.1 - High - Vext
M33Z_01A - 2.1 - High - Vint
M33Z_01A - 2.1 - Low - Vext
M33Z_01A - 2.1 - Low - Vint
M33Z_01A - 2.3 - High - Vext
M33Z_01A - 2.3 - High - Vint
M33Z_01A - 2.3 - Low - Vext
M33Z_01A - 2.3 - Low - Vint
M33Z_01A - 2.7 - High - Vext
M33Z_01A - 2.7 - High - Vint
M33Z_01A - 2.7 - Low - Vext
M33Z_01A - 2.7 - Low - Vint
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External Use 44
Summary and/or Q&A
• Choosing an optimal data converter architecture can have a profound impact on the performance, power consumption and cost of any electronic system
• Freescale has a vast array of data converter IP in a wide range of process technologies from 0.25mm to 28nm CMOS to high-performance BiCMOS and SMARTMOS
• Freescale has a decades-long history of developing high-performance data converters
• Freescale has outstanding data converter development/evaluation capabilities to meet virtually any system/application requirements
• For further information contact
− phone: 480-413-3442
TM
© 2014 Freescale Semiconductor, Inc. | External Use
www.Freescale.com
