Introducing Freescale’s ColdFire-Based Compressed Audio

© Freescale Semiconductor, Inc., 2003, 2004, 2005, 2006, 2007. All rights reserved.

Freescale SemiconductorApplication Note

Document Number: AN2462Rev. 1, 2/2007

1 Is this MP3 Thing a Fad with Computer Geeks that Will Pass?

Although compressed audio (generally referred to as “MP3”) may have started life as a computer application, there are now many emerging markets where it can be found.

The rapid spread of digital audio compression technologies, such as MP3 (MPEG Audio Layers 3), is transforming the way we record, transport, and listen to music. The approximate 10:1 data compression achieved by MP3 makes it practical to transfer music files via the internet or via wireless interfaces, as well as requiring significantly less storage space.

The availability of recordable CD drives at consumer price points is also giving a new lease of life for the compact disc format. Indeed the relatively low cost and high storage capacity of blank CD media, together with its compatibility with existing playback systems in use all over the world may make the CD the ultimate MP3

Introducing Freescale’s ColdFire-Based Compressed Audio SolutionsMCF5249, MCF5249L, SCF5249, SCF5250

by: Ross McLuckie, East Kilbride, Scotland

Contents1 Is this MP3 Thing a Fad with Computer Geeks

that Will Pass? . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Why the MCF5249? . . . . . . . . . . . . . . . . . . . . . . .23 The Trio Software Demonstration . . . . . . . . . . . .84 Hardware Requirements . . . . . . . . . . . . . . . . . .105 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 Appendix A: M5249C3 Schematics . . . . . . . . . .187 Appendix B: Audio Daughter

Card Schematics . . . . . . . . . . . . . . . . . . . . . . . .29

Why the MCF5249?

Introducing Freescale’s ColdFire-Based Compressed Audio Solutions Application Note, Rev. 1

2 Freescale Semiconductor

music medium. A single CD can hold over 100 hours of music in MP3 form.

However the actual storage media used is not important and dependent on the intended application. Hard Disk Drives (HDD) are now small enough, with low power consumption, to provide a battery operated, hand held device capable of storing more than the average person’s entire music collection.

Flash based products, either using discrete chips and/or one of the numerous commercially available flash sticks may not be able to offer the storage capabilities of a CD or HDD, but can provide very small, pen-like products with no moving parts and very long battery life.

MP3 compatibility is very quickly spreading through numerous product ranges, portable audio players, home hi-fi, car audio, DVD players and game consoles are some good examples, but there are also some less obvious areas where MP3 is emerging, elevator music and floor announcements for example.

Although MP3 may be the most commonly known form of audio compression, there are several other algorithms available, such as Windows Media Audio (WMA) and Advanced Audio Codec (AAC), with the story unlikely to end there as new ways to improve quality and/or compression levels are discovered.

2 Why the MCF5249?In terms of their demands on a microprocessor, MP3-based digital audio systems share the requirement for significant amounts of control processing as well as digital audio signal processing. Control processing includes file management, data buffering, system control and user interface control, while the MP3 decode algorithm itself involves roughly 50 percent control-type functions and 50 percent signal processing. Other signal processing tasks include audio effects processing (e.g., dynamic bass boost) and digital volume control.

Typically these systems use separate Digital Signal Processing (DSP) and microcontroller devices to perform the signal processing and control tasks. Clearly a more efficient, lower cost solution would be to implement both tasks on a single microprocessor. The ColdFire 32-bit microprocessor provides a compact engine for control code processing with its variable-length RISC architecture, and the addition of the Enhanced Multiply and ACcumulate (EMAC) unit adds powerful DSP capability to the ColdFire architecture.

The MCF5249 integrated microprocessor combines a Version 2 ColdFire® processor core operating at 140MHz with the following modules:

• DMA controller with 4 DMA channels• Integrated Enhanced Multiply-ACcumulate Unit (EMAC)• 8-Kbyte Direct Mapped Instruction Cache• 96-Kbyte SRAM (A 64 Kbyte and a 32 Kbyte bank)• Operates from external crystal oscillator• Supports 16-bit wide SDRAM memories• Serial Audio Interface which supports IIS and EIAJ audio protocols• Digital audio transmitter and two receivers compliant with IEC958 audio protocol• CD-ROM and CD-ROM XA block decoding and encoding function• Two UARTs

Why the MCF5249?


Freescale Semiconductor 3

• Queued Serial Peripheral Interface (QSPI) (Master Only)• Two timers• IDE and SmartMedia interfaces• Analogue to Digital Converter• Flash Memory Card Interface• Two I2C modules• System debug support• General Purpose I/O pins shared with other functions• 1.8 V core, 3.3 V I/O• 160 pin MAPBGA package (qualified at 140 MHz) and 144 pin QFP package (qualified at

120 MHz)

Why the MCF5249?



2.1 MCF5249 Block Diagram

Figure 1. MCF5249 Block Diagram

Standard ColdFire Peripheral Blocks

32K

64K

UARTInterface

I2CInterface

TimerSupport

Memory Stick/

Interface

Serial AudioInterface

(S)DRAMSRAM

MUX

IDE

SWESRE

IDE–DIORIDE–DIOW

IDE–IORDY

Secure Digital

QSPI_CS[3:0]QSPI_CLK

BUFEN1_B

BUFEN2_B

QSPI_DINQSPI_DOUT

EBUIN3/ADIN0_GP138EBUIN4/ADIN1_GP139RXD2/ADIN2/GP128CTS2/ADIN3/GP131TOUT1/ADOUT/GP135

DebugModule w/

JTAG

InstructionCache

ColdFire V2 Core

(160 BGA140 Mhz)

(144 QFP 120 Mhz)

SRAM1

SRAM0

Clock Multiplied

PLL

DMA

5x08Arbiter

Timer

I2C

DualUART

5x08Interrupt

S/DRAMInterface

ExternalBus

Translator

IDESmartMedia

InterruptController

QSPIInterface

AudioInterfaces

ADC

Flash MemoryCard

Interface

Why the MCF5249?



2.2 ColdFire EMAC UnitThe ColdFire EMAC unit is an enhanced version of the existing MAC unit with additional features to improve signal-processing performance especially for digital audio applications. These new features include:

• Improved performance for 32x32 fractional and integer multiply-accumulate operations, with an effective issue rate of 1 clock cycle per MAC.

• Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the general purpose ColdFire registers. Many algorithms require multiple calculations on a given data set. By applying different accumulators to these calculations, it is often possible to store one accumulator without any stalls while performing operations involving a different destination accumulator.

• Implementation of 48-bit accumulation data path to allow the use of a 40-bit product plus the addition of 8 extension bits to increase the dynamic number range when implementing modern signal processing algorithms. Existing MAC features which are also important for efficient digital audio signal processing include:— Support for signed, unsigned integer and signed fractional operands.— Operand fetch in parallel with multiply accumulates.

2.3 Audio Interface ModuleThe advanced ColdFire audio peripherals that have been developed include IIS-compatible serial ports and an IEC958/SPDIF transceiver. A unique on-chip TDM (time-division multiplexed) bus has been engineered to allow signals to be routed easily between peripherals and CPU. These integrated audio peripherals help to lower overall system costs, as external audio interface devices are not required.

In CD and CD recordable systems, the CPU must be able to route digital audio signals to and from the drive electronics, from analogue-to-digital and to digital-to-analogue converters, and to and from the outside world. In addition, the transmission and reception of CD subcodes must be accommodated. Finally, it should be noted that compressed audio formats, such as MP3, use the CD-ROM file format for storage on CD.

A new Audio Interface Module has been designed to facilitate audio interchange in CD systems with the minimum of CPU intervention. The Audio Interface Module allows the device to receive and transmit digital audio over serial audio interfaces (IIS/EIAJ) and over digital audio interfaces (conforming to the European Broadcast Union (EBU)-IEC958 standard, and compatible with the Sony/Philips Digital Interchange Format).

The device is equipped with four serial audio interfaces, compliant with Philips IIS and Sony EIAJ format, two IEC958 receivers with four multiplexed inputs, and one IEC958 transmitter with two outputs (one for professional sub-code and one for consumer sub-code).

The Audio Interface Module connects all the audio interface ports to an internal 40-bit TDM bus to allow the direct retransmission of an audio signal received on one receiver to another transmitter, without CPU intervention. In parallel, the CPU is able to receive or transmit digital audio to and from any of the audio interfaces.

Why the MCF5249?



2.4 Audio Interface Module Functional Diagram

Figure 2. Audio Interface Module Functional Diagram

The Audio Interface Module includes a hardware CD-ROM encoder/decoder, which optionally applies CD-ROM header detection, scrambling/de-scrambling, and electronic data check functions required for reading and writing CD-ROMs. This allows the device to provide MP3 functionality using only low-cost audio drives, computer CD-ROM-type drives are not required.

2.5 32-Bit Data PathIt is generally accepted in digital audio engineering that to process 16-bit signals with no loss of audio quality requires a processor with greater than 16-bit precision. This is because the internal data path of a 16-bit processor has the same resolution as the desired output and rounding errors, which occur during arithmetic operations, are inevitably transferred to the output. DSPs that are 16-bit often have to use extended precision modes requiring three to four times the number of CPU cycles to achieve acceptable audio quality.

With its 32-bit data paths and 48-bit accumulators, the ColdFire with EMAC architecture is capable of extremely efficient processing of certain audio algorithms. For example, Freescale’s ColdFire MP3 decoder has been tested as having 18 bits of accuracy compared to the ISO standard floating point implementation, equivalent to a signal-to-noise ratio of 108 dB. However, the MP3 decoder requires just 19 MHz* on a ColdFireV2 with EMAC core.

NOTEWorst-case data and assume single cycle memory accesses.

Audio Bus -- 40-bit Time Multiplexed Bus

EBU1Receiver

EBU2Receiver

IIS1Receiver

IIS3Receiver

IIS4Receiver

CPUOutput

CPUOutput

CPUOutput

EBU1Transmit

IIS1Transmit

IIS2Transmit

CPUInput

CPU Input

CDROMDecoder

CDROMEncoder

Select Select SelectSelect Select

FIFO6 Fields

FIFO6 Fields

FIFO6 Fields

FIFO6 Fields

FIFO6 Fields

CPU Bus

CPU Bus

Why the MCF5249?



2.6 Low System Power DissipationIn battery operated systems, such as portable MP3 players, it is important to minimize the system power consumption in order to minimize the inconvenience and expense of changing or recharging the battery. The following factors are identified as significantly contributing to the power dissipation of an electronic system:

• Operating Voltage: This is perhaps the most important factor as power dissipation is proportional to the square of the voltage, thus a reduction of operating voltage from 2.5V to 1.8V reduces power dissipation by approximately one half. The available operating voltage range is essentially a function of the semiconductor process technology used to manufacture the Integrated Circuit (IC) in question. The fully automated, synthesizable design methodology employed for ColdFire-based Is makes the widest range of manufacturing technologies available with the minimum of effort since only standard library elements and compiled memories are used. Also, the design can be easily migrated to new manufacturing processes, as they become available. Existing 0.18micron CMOS logic processes use core supply voltages in the range 1.5 V–1.8 V. Next generation 0.13micron processes will allow supply voltages of around 1.0 V.

• Operating Frequency: Since power dissipation of synchronous digital logic is proportional to the switching frequency, it is important to minimize the operating clock frequency required. Freescale’s ColdFire MP3 decoder requires just 19 MHz on a ColdFireV2 with EMAC core, allowing a ColdFire-based MP3 player to operate from a very low system clock frequency.

• Integration Level: A highly integrated system solution, with most functions included in a single IC, can dramatically reduce system power dissipation because with multiple separate Is, powerful output drivers are required to overcome the large capacitance of the interconnecting Printed Circuit Board (PCB) traces. Freescale’s ColdFire audio solutions combine DSP and MCU functionality with application-specific peripherals and on-chip memory to minimize the number and switching frequency of inter-chip connections.

2.7 Code Density and System IntegrationIn many designs, the cost of memory exceeds the microprocessor cost, so this factor can significantly impact overall system cost. The ColdFire processor architecture addresses these requirements through a variable-length instruction set to maximize code density implemented in a RISC-based approach, providing a very efficient silicon design.

Simple instructions require only a 16-bit instruction length while more complex instructions are implemented in 32 or 48 bits. Each instruction takes only the amount of space required with the result that both memory storage space and memory interface bandwidth are minimized.

With the addition of the EMAC, the ColdFire CPU becomes a very good control-code processor that is also capable of efficient signal processing. For example, Freescale’s MP3 decoder requires just 37 Kbytes of memory, including 17.5-Kbyte ROM and 19.5-Kbyte RAM.

Combining DSP and MCU functionality in the same core together with very efficient use of on-chip and off-chip memory results in lower overall system cost.

The Audio Interface Module provides a high level of digital audio connectivity on-chip, further reducing component count, PCB footprint, and system cost.

The Trio Software Demonstration



2.8 Large Address Range and Cache ArchitectureThe ColdFire architecture’s 32-bit address range and on-chip cache make it well suited for running the large software stacks needed for file management, data buffering, and control in CD and MP3 systems. ColdFire devices can address large continuous address ranges without the need for bank switching required by some 16-bit architectures. On-chip caches deliver good performance and minimize off-chip accesses (and therefore power dissipation) even with slow external memory.

2.9 Programmable FlexibilityThe fact that a software programmable architecture is used, rather than hardwiring certain algorithms, means that the system can be easily upgraded to support new algorithms and standards as they emerge. Competitors to the widely used MP3 compression algorithm, such as AAC and WMA, which claim improved quality and/or compression levels have already emerged and there will surely be others in future. A programmable signal-processing engine also allows customers to implement their own proprietary audio processing algorithms in order to differentiate their product from competitors.

2.10 Tools Support—RTOS and Development ToolsAll ColdFire based devices include a Background Debug Module (BDM) on chip with a common interface to debug tools available from third party vendors and Freescale’s Metrowerks division.

The BDM enables the programmer to directly control the CPU, access its registers, as well as the use of breakpoints, single stepping through code, and real-time trace of application code.

The BDM interfaces to development tools via a standard 26-pin header, so a simple register map change is all that is required for development tools to support new ColdFire family members.

The similarity of the ColdFire programming model to that of the industry standard 68K architecture has made it easy for a wide range of development tools suppliers to support the ColdFire product family. A list of third party development tools can be found on Freescale’s web site at www.freescale.com.

The standard BDM interface and wide range of development tools contribute to the “ease of use” of the ColdFire architecture. Hardware and Software developers have a choice of powerful solutions to meet their development tool needs, and new system-on-chip derivatives can be accommodated by the tools with little or no delay to the time to market of the customer’s end product.

3 The Trio Software DemonstrationThe software demonstration was developed by part of Freescale’s Global Software Group (GSG), based in India. The Trio demonstration, along with several other software packages, can be downloaded from www.freescale.com.

The demonstration is intended for evaluation only, to show how easily MP3 compatibility could be added to any system. If appropriate the Trio code can be supplied as a fully supported library module, via a license agreement.

The Trio Software Demonstration



3.1 Software Features• Audio CD playback• MP3 playback (MPEG-1 Layer 3 and MPEG-2 Layer 3 with lower sampling rates)• WMA playback (high rate, mid rate and low rate)• WAV file playback (16- or 8- bit linear samples; sampling rates supported same as for MP3 and

WMA)• CD-DA, CD-R, CD-RW and CD-ROM discs• 12 cm discs• ISO-9660 Level 3 file system with Joliet extension• ISO-9660 Joliet format for Macintosh• UDF file system, version 1.5, with fixed and variable packets• Multi-session discs (up to five sessions)• Mixed discs (data and audio tracks)• Copy-protected CD-DA discs• Display of ID3 tags V1.1, V2.2, V2.3, V2.4• Disc start-up retry (for open discs and discs with errors)• Servo switch-off after filling up internal buffer• Basic player controls

— Play/Pause/Stop— Next track/Previous track— Fast forward/Rewind— Digital Volume Control— Hold (disable keypad)

• Track/File programming• Flat/Hierarchical/Collapsible file system browsing• Playlist• Shuffle• Repeat (None/One/All/AB)• Pre-set 5-Band Graphical Equalizer (Flat/Rock/Classic/Jazz/Ultra bass modes)• User Definable 5-Band Graphic Equalizer• ESA, with 4X ADPCM compression• Intro-Scan• Lid Open/Close detect, with player stop on Lid Open• Booting from Flash memory• Last three file systems stored during power-down in flash memory for quick start-up• Resume on power-up with previous settings and playing position• Software update from CD

Hardware Requirements



• Additional displays through Menu— Hold/Resume setting— Decoder Information (type, sampling rate, bit rate)— Time (Elapsed/Remaining time for current track)— ID3 and WMA tags display of artist, title, album, genre and year

• Configurable SSC (sub-code and sector controller) and BFM (buffer and file management)• Easy to add new decoders (e.g., Ogg Vorbis, MP3Pro) and additional audio post processing (e.g.,

SRS WOW, QSound Sizzle)

3.2 System TestingThe demo has gone through some basic system tests using various types of disc. In total about 130 discs have been used. Different CD writers (HP and Sony) have been used. In addition, testing has been done using the ABEX test discs from Almedio Japan. These cover a range of tests, including scratches, black dot, black band, fingerprints, multi-session, MP3 and WMA, tones of various frequencies, left and right channel separation, directory structure, nested directories, ID3 tags etc.

For more details, refer to the Almedio web-site at www.almedio.co.jp/english/tmsection_index.phtml.

4 Hardware RequirementsTo run the demo requires a modified M5249C3 evaluation board (EVB), an audio daughter card and a modified CD player based on Philips’s CD10 Servo chipset.

4.1 M5249C3 ModificationsFirst, check expansion connectors (J4 and J5) are fitted, allowing connection to the daughter card. If required to retro-fit the connectors, various height options are available, it is recommended to use the tallest option (13 mm), allowing easier access to the numerous connectors on the daughter card and reducing the risk of component fouling between the two boards. The connectors are available from AMP, part number 5-179010-5.

It is also necessary to remove some components from the board to prevent IO conflicts when running the demo, U13, U14, U19, R109, R110, and R115 to R117 must be removed.

NOTEEnsure short circuits are not introduced when adding and/or removing components.

The demo software can be built to run either from Flash or SDRAM, see software documentation. In order to build and run a suitable image requires a Diab ColdFire Compiler licence (version 4.3f) and WindRivers’s VisionProbe II BDM cable (or suitable alternative).

Alternatively contact your local Freescale representative about acquiring an appropriate ROM image to program the onboard memory with any suitable programming tool, including the M5249C3’s dBUG command line monitor/debugger.




NOTEIf using dBUG, program the Flash memory before modifying the EVB itself.

After successfully running the demo, audio output from the CD player can be heard from the headphone jack plug (J1), with interaction possible through the daughter card’s user interface—LCD and keypad.




4.2 M5249C3 EVB (Required Jumper Configuration and Modification)

Figure 3. M5249C3 EVB Required Jumper Configuration and Modification

ExpansionConnectors

HeadphoneJack Plug

Remove U13, U14,

U19, R109, R110




4.3 Audio Daughter Card (Required Jumper Configuration)

Figure 4. Audio Daughter Card (Required Jumper Configuration)

g

CD PlayerInterface

LCD Contrast(If Required)




4.4 CD Player ModificationsAlthough in theory it should be possible to convert any CD player, based on the CD10 servo chipset, to run the demo, in practice it would be simpler to follow the worked example shown.

Any of the following Philips’s portable CD player model numbers should be suitable, however the one used in the demo, which is known to work, is the AX5015:

AX2000, AX2001, AX2002, AX2003, AX2011, AX5000, AX5001, AX5002, AX5003, AX5004, AX5006, AX5011, AX5012, AX5013, AX5014, AX5015, AX5016, AX5017, AX5018, AX5019

The modifications required, include removing and refitting some components on the CD player circuit board and providing a wired interface between the modified CD player and the daughter card.

NOTEEnsure short circuits are not introduced when removing components from the circuit board.

J13 and J15 on the daughter card are intended to provide the necessary interface, J15 can be used to power the CD player, with a +5 volt DC, centre +ve, power supply. The following table details the minimum required interface between J13 and the CD player.

Table 1. CD Player Interface

J13Pin Number

MCF5249Pin Name

MCF5249Function

CD PlayerConnection

CD PlayerReference

1 SDATAI1 IIS1 SDATAI 7880-11

2 SCLK1 IIS1 SCLK 7880-13

3 LRCK1 IIS1 LRCK 7880-12

4 EF/GPIO19 EF EF 7830-30

5 CFLG/GPIO18 CFLG CFLG 7830-53

6 SCLK4/GPIO50 GPO SDA 3413

7 LRCK4/GPIO46 GPO SCL 3412

8 RTS0/GPO30 GPO RAB 3861

9 RTS1/GPO31 GPO SILD 3860

10 RCK/GPIO51 GPO PORES 3864

11 SFSY/GPIO52 GPO SMUTE 7400-63

12 SUBR/GPIO53 GPO SLEEP 7400-64

13 CTS0/GPI30 GPI WAKE 6400

14 TIN0/GPI33 GPI RESUME 3403

15 TIN1/GPIO23 GPI HOLD 3402




16 RXD0/GPI27 GPI LID SWITCH 3404

17 RESET RESET RESET 2405

18–28 — — — —

29–30 GND GND GND 2257–2250

Table 1. CD Player Interface (continued)

J13Pin Number

MCF5249Pin Name

MCF5249Function

CD PlayerConnection

CD PlayerReference




4.5 Circuit Board Modifications

Figure 5. Circuit Board Modifications

This assembly drawing shows a summary ofall possible versions. For components used inspecific versions see circuit diagram or partslist.

For service testpoints seecircuit diagram “CD-Part”

COPPERSIDE VIEW Remove Is 7400,

7880 and resistor

Move resistor 3289 to location 3290




4.6 Circuit Board Modifications (continued)

Figure 6. Circuit Board Modifications (continued)

This assembly drawing shows a summary ofall possible versions. For components used inspecific versions see circuit diagram or partslist.

For service testpoints seecircuit diagram “CD-Part”

COPPERSIDE VIEW

J13-4J13-10J13-5J13-1J13-3J13-2

J13-16J13-15J13-14J13-7J13-6J13-9J13-8

J13-29J13-13J13-11J13-12J13-17J13-30

Conclusion



5 Conclusion

5.1 Advantages of the MCF5249 for Digital AudioTo achieve high volume sales, consumer audio equipment must have the following attributes:

• Affordability: Low system cost by having control and DSP functions on a single CPU, good code density for efficient use of memory and high levels of integration.

• Ease of Use: Compiler friendly architecture, good development tools, fully automated design methodology for faster time to market and flexibility to changing requirements.

• Long Battery Life (in portable applications): Operation at low voltages and low clock frequencies, high levels of system integration.

The MCF5249 is a low cost, high performance (125 MIPS @ 140 MHz), low power (1.3 mW per MHz), highly integrated processor designed specifically for compressed audio applications, capable of supporting CD, HDD and/or Flash Media stick applications.

The software implemented decoder approach provides excellent performance (MP3 decoder requires only 19 MHz), whilst future proofing designs against new algorithms, by allowing software upgrades.

A fully supported software library, via a license agreement, is readily available.

5.2 Additional InformationThere are numerous CD servo chipsets available, and although this demo is based on Philips’s CD10, support is also available for Sony and Sanyo chipsets, with additional support being added as required.

In addition to the decoder, Freescale has also implemented a real-time MP3 encoder on the ColdFire architecture. A high quality MP3 encoder has been developed, rivalling the best MP3 encoders available in terms of audio quality, this allows the MCF5249 to meet the requirements of CD burner products.

The Trio demo is currently based on the CD platform, the HDD demo is in development.

Although the MCF5249 was originally intended for compressed audio applications, its low cost, high performance is helping it find other markets requiring a similar split between control and signal processing, such as biometric applications, for example, finger print recognition.

6 Appendix A: M5249C3 Schematics

Appendix A: M5249C3 Schematics



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4 4

3 3

2 2

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SDA1/GPIO55SCL1/GPIO3SCL0/QSPICLK

CRIN

XTR

IM/G

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38C

L11/

GP

O39

CL1

6/G

PO

42

QSPI_CS2/GPIO21QSPI_CS1/GPIO24

EF/

GP

IO19

CFL

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PIO

18TI

N1/

GP

IO23

QSPI_DOUT/GPIO26QSPI_CS0/GPIO29

QSPI_CS3/GPIO22

IDE

DIO

R/G

PIO

13ID

ED

IOW

/GP

IO14

IDE

IOR

DY

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IO16

BU

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B1/

GP

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DA

TA1_

BS

1/G

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9S

DA

TA_B

S2/

RST

OS

DA

TA3/

GP

IO56

SC

LKO

UT/

GP

IO15

PS

TCLK

PS

T[3:

0]D

DA

TA[3

:0]

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CM

DS

DIO

2/G

PIO

34

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SE

T

DS

CLK

DS

I-B

KP

T

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R/W

BC

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SD

RA

M_C

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1

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SDRAM_CS1-SDCAS

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BCLKE

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GPIO5

GP

IO6

A[2

4:1]

D[31:16]

TCK

HI-Z

She

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Mem

ory

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BC

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M_C

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MS

DU

DQ

M

-SD

RA

S-S

DC

AS

She

et 2

Aud

ioSD

ATA

O2

CL1

1/G

PO

39C

L16/

GP

O42

SC

LK2/

GP

IO48

LRC

K2/

GP

IO44

SC

LK3/

GP

IO49

SC

LK1

LRC

K1

SD

ATA

I1

She

et4

Deb

ug_T

est P

oint

s

DS

O

DS

CLK

-BK

PT

DS

I

PS

TCLK

-TA

-RE

SE

T

PS

T[3:

0]D

DA

TA[3

:0]

-CS

0R

/W-O

EB

CLK

CRIN

She

et5

Eth

erne

t

A[2

4:1]

D[3

1:16

]

BC

LK

-RE

SE

T

-CS

1

R/W

-TA

_IN

-TA

GP

IO6

-OE

She

et6

Exp

ansi

on C

onne

ctor

s

D[3

1:16

]

A[2

4:1]

SD

RA

M_C

S2

-CS

1

SDRAM_CS1

-CS

0

-SDRAS-SDCAS

-SDWE

SDLDQMBCLKE

R/W -OE

BC

LK

SDUDQM

DS

CLK

-BK

PT

DS

ID

SO

-TA

GP

IO5

GP

IO6

-RE

SE

T

SD

ATA

I1S

DA

TAI3

/GP

I41

SD

ATA

I4/G

PI4

2

SD

ATA

O1/

GP

IO25

SD

ATA

O2

SC

LK1

SC

LK2/

GP

IO48

SC

LK3/

GP

IO49

SC

LK4/

GP

IO50

LRC

K1

LRC

K2/

GP

IO44

LRC

K3/

GP

IO45

LRC

K4/

GP

IO46

DD

ATA

[3:0

]P

ST[

3:0]

PS

TCLK

SC

LKO

UT/

GP

IO15

SD

ATA

3/G

PIO

56S

DA

TA_B

S2/

RS

TOS

DA

TA1_

BS

1/G

PIO

9S

DA

TA0_

SD

IO1/

GP

IO54

SR

E/G

PIO

11S

WE

/GP

IO12

CM

DS

DIO

2/G

PIO

34

BU

FEN

B2/

GP

IO17

BU

FEN

B1/

GP

IO57

IDE

IOR

DY

/GP

IO16

IDE

DIO

R/G

PIO

13ID

ED

IOW

/GP

IO14

QS

PI_

DO

UT/

GP

IO26

QS

PI_

CS

0/G

PIO

29

TIN

1/G

PIO

23C

FLG

/GP

IO18

EF/

GP

IO19

QS

PI_

CS

1/G

PIO

24

QS

PI_

CS

3/G

PIO

22Q

SP

I_C

S2/

GP

IO21

CL1

6/G

PO

42C

L11/

GP

O39

XTR

IM/G

PO

38

CRIN

EB

UIN

1/G

PI3

6E

BU

IN2/

GP

I37

EB

UIN

3/G

PI3

8E

BU

IN4/

GP

I39

EB

UO

UT1

/GP

O36

EB

UO

UT2

/GP

O37

RX

D0/

GP

I27

TXD

0/G

PO

27

-RTS

0/G

PO

30

-CTS

0/G

PI3

0R

XD

1/G

PI2

8

TXD

1/G

PO

28

-RTS

1/G

PO

31

-CTS

1/G

PI3

1

TOU

T0/G

PO

33TO

UT1

/GP

O35

TIN

0/G

PI3

3

RC

K/G

PIO

51S

FSY

/GP

IO52

SU

BR

/GP

IO53

SD

A0/

QS

PID

INS

CL0

/QS

PIC

LK

SD

A1/

GP

IO55

SC

L1/G

PIO

3

-TA

_IN

HI-Z

TCK

She

et9

Seria

l_I2

C_Q

SPI

SC

LK4/

GP

IO50

LRC

K4/

GP

IO46

SD

ATA

I3/G

PI4

1S

DA

TAI4

/GP

I42

TXD

0/G

PO

27TX

D1/

GP

O28

-RTS

0/G

PO

30-R

TS1/

GP

O31

RX

D0/

GP

I27

-CTS

0/G

PI3

0R

XD

1/G

PI2

8-C

TS1/

GP

I31

SD

A1/

GP

IO55

SC

L1/G

PIO

3S

CL0

/QS

PIC

LKS

DA

0/Q

SP

IDIN

QS

PI_

DO

UT/

GP

IO26

QS

PI_

CS

0/G

PIO

29Q

SP

I_C

S1/

GP

IO24

QS

PI_

CS

2/G

PIO

21Q

SP

I_C

S3/

GP

IO22

D[3

1:16

]

A[2

4:1]

D[3

1:16

]

A[2

4:1]

A[2

4:1]

PS

T[3:

0]

D[3

1:16

]

DD

ATA

[3:0

]

DD

ATA

[3:0

]P

ST[

3:0]




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MT0

= L

OW

and

MT1

= H

IGH

prov

ides f

aste

st M

UTE

time

CKS

= LO

W 2

56fs

MCL

KDI

F =

HIG

H so

aud

io int

erfa

ce s

et fo

r I2S

mod

e (2

0-bit

iffs

>40

)

Anal

og g

roun

d

All d

efau

lt ju

mpe

r set

tings

on

this

shee

t are

bet

ween

pin

s 1

& 2

Mot

orola

SPS

TSP

G -

32-b

it Em

bedd

ed C

ontro

ller D

ivisio

n (T

ECD)

Anal

og g

roun

d

Anal

og g

roun

d

Anal

og ri

ght c

hann

el in

put

Anal

og le

ft ch

anne

l inpu

t

All a

nalo

g gr

ound

- sin

gle

grou

nd c

onne

ctio

n to

dig

ital g

roun

d

Jum

pers

13

& 14

are

fitte

d du

ring

asse

mbl

y

MCF

5249

- Au

dio

Inte

rface

s1.

1

MCF

5249

Eva

luat

ion

Boar

d - P

art n

umbe

r RE1

0811

B

B

210

Thur

sday

, Mar

ch 0

7, 2

002

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+5V

+5V

J9

RCA

PHO

NO J

ACK

1

2

J10

RCA

PHO

NO J

ACK

1

2

R119

18R1

2018

J1 STER

EO J

ACK

SOCK

ET S

W 3

.5m

m

1234

JP13

12

JP14

12

U1

AK43

60VF

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

MCL

KPD

NBI

CKSD

ATA

LRCK

MT0

MT1

DEM

MUT

ENBO

OST

CKS

DIF

TST1

TST2

VDD

VSS

VREF

VCO

MTS

T3HP

VCC

HPG

ND NCAO

UTL

AOUT

R

C10

10uF

16V

R107

470

R2 10

C4

10uF

16V

C61u

F 50

V

C116

4.7u

F 25

V

C118

4.7u

F 25

V

C11

330u

10V

C50.

1uF

C119

4.7u

F 25

V

C81uF

50V

C70.1u

F

C120

4.7u

F 25

V

C12

330u

10V

C9 0.1u

F

C122

10uF

16V

C14

0.22

uFC121

10uF

16V

JP3

CKS

Low=

256

fs, H

igh=

384

fs

1 3

2

C13

0.22

uF

C127

0.1u

F

C117

2.2n

F

C126

0.1u

F

C125

0.1u

F

U19

AK53

53VT

1 2 3 4 5 6 7 8910111213141516

AINR

AINL

VREF

VCO

MAG

NDVA VD DG

NDSD

TOLR

CKM

CLK

SCLK

PDN

DIF

TTL

TST

JP4

DIF

Low=

16b

it LS

B ju

stifie

d, H

igh=

I2S

16/1

8/20

-bit

1 3

2

C123

2.2n

F

C3 0.1u

F

R1 10

C124

0.1u

F

R108

470

RP43

4x 4

.7K

12

34

56

78

12

34

56

78

JP2

BOO

ST L

ow =

no

high

pas

s co

rrect

ion,

Hig

h =

high

pas

s co

rrect

ion

1 3

2

JP1

DEM

Low

= n

o de

-em

phas

is, H

igh

= de

-em

phas

is

1 3

2

L3FE

RRIT

E_BE

AD1

2

SDAT

AO2

CL11

/GPO

39CL

16/G

PO42

SCLK

2/G

PIO

48

LRCK

2/G

PIO

44

SCLK

3/G

PIO

49

SDAT

AI1

LRCK

1CL

16/G

PO42

SCLK

1CL

11/G

PO39




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+3.3

V s

uppl

y de

coup

ling

+1.8

V s

uppl

y de

coup

ling

Jum

pers

onl

y re

quire

d if

I2C

cha

nnel

0 is

use

d.Fo

r ass

embl

y fit

to o

ne ju

mpe

r pin

onl

y.

Def

ault

jum

per s

ettin

g be

twee

n pi

ns 1

& 2

,de

bug

mod

e - B

DM

. Set

ting

betw

een

pins

2 &

3 e

nabl

es J

TAG

mod

e

Mot

orol

a S

PS

TS

PG

- 32

-bit

Embe

dded

Con

trolle

r Div

isio

n (T

ECD

)

Mot

orol

a S

PS

Col

dFire

MC

F524

9

MC

F524

9 C

PU

and

Pul

l-ups

1.1

MC

F524

9 E

valu

atio

n B

oard

- P

art n

umbe

r RE

1081

1B

C

310

Tues

day,

Mar

ch 1

9, 2

002

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

PS

T0P

ST1

PS

T2P

ST3

A[2

4:1]

D[3

1:16

]

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

DD

ATA

0D

DA

TA1

DD

ATA

2D

DA

TA3

RP

1-7

RP

1-7

+3.3

VP

+1.8

VP

+3.3

VP

+1.8

VP

+3.3

VP

+5V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V+3

.3V

+3.3

V

+1.8

VP

+1.8

VP

RP

24B

47

RP

21A

47

C34

1nF

RP

40B

47

RP

14x

4.7

K1

23

45

67

8

12

34

56

78

RP

26A

47

RP

30C

47

C17

0.1u

F

RP

39A

47

RP

29A

47

RP

25B

47

RP

29C

47

RP

18C

47

C19

1nF

RP

40C

47

RP

16C

47

RP

37C

47

RP

14D

47

C23

470p

F

RP

33B

47

RP

37D

47

RP

15D

47

JP7

DE

BU

G

1 3

2

RP

84x

4.7

K1

23

45

67

8

12

34

56

78

RP

24x

4.7

K1

23

45

67

8

12

34

56

78

RP

28C

47

RP

25C

47

RP

34C

47

RP

30A

47

RP

26C

47

C21

1nF

RP

16A

47

RP

35A

47

RP

34B

47

RP

31D

47

RP

33D

47

C13

0

470p

F

C16

0.1u

F

RP

26B

47

RP

17C

47

C36

470p

F

RP

30D

47

RP

20A

47

RP

27B

47

RP

24C

47

C15

0.1u

F

U2

MC

F524

9 M

AP

BG

A16

0

D4

A1

D3

G3

K4

B1

C2

C1

E3

D2

D1

E2

F3

E1

E4

F2 F1

F4

G4

G1

G2

H3

H1

H4

H2

J1 J2 K1

K2

L1 L2 M1

M2

N1

N4

N5

P5

J3

J4

K6

K3

K5

L3

L4

M3

N2

M4

P1

P2

N3

P3

P4

L5

P8

N7

P7

N6

P6

L6

L7 K7

L8

K8

N8

P9

L9

N9

K9

P10

N10

L10

P11

P12

N11

P13

N12

M11

P14

N13

K10

K11

M12

L12

N14

M13

M14 L1

3

L14

L11

K13

K12

K14J11

J13J12

J14H11

H12

H14

H13

G11

G14

G12

G13

F14

F11

F13

E9

E14

F12

E13

E10

E12

E11

D14

D13

C14

D12

C13

B14

D11

C12

B13

C11

A14

A13

B12A12

B11

A11

B10

D10

A10B

9

D9

A9

D8

A8

E8

B8

E7

D7

A7

B7

A6

E6

B6

D6

A5

B5

D5

A4

A3

B4

A2

B3

C4

B2

C3

E5

SC

L0/Q

SP

ICLK

CS

0

A21

A22

A23

A11

A10A

9

CMDSDIO2/GPIO34

A18

A17

BC

LK/G

PIO

10

SCLKOUT/GPIO15

BC

LKE

SD

A0/

QS

PID

IN

DA

TA_2

4

SD

UD

QM

/UW

E

EF/GPIO19

SDATA0_SDIO1/GPIO54

DA

TA_2

5D

ATA

_26

SDATA2_BS2/RSTO

DA

TA_2

7

PAD-GND

DA

TA_2

8D

ATA

_29

DA

TA_3

0D

ATA

_31

A13

A14

A15

A16

A19

A20

GPIO5/INT5

QSPI_DOUT/GPIO26

DA

TA_2

1

SDATA3/GPIO56

BUFENB1/GPIO57

CORE-VDD

A25

row

/A24

colu

mn_

GP

O8

CORE-GND

PAD-VDD

QSPI_CS1/GPIO24

TEST2

SD

RA

M_C

S1

SDATA1_BS1/GPIO9

SD

RA

SS

DC

AS

SD

WE

SD

LDQ

M/L

WE

QSPI_CS0/GPIO29

GPIO6/INT6

DA

TA_1

6D

ATA

_17

DA

TA_1

8D

ATA

_19

DA

TA_2

0

QSPI_CS2/GPIO21

DA

TA_2

2D

ATA

_23

QSPI_CS3/GPIO22

PAD-VDD

SD

RA

M_C

S2/

GP

IO7/

INT7

EB

UO

UT2

/GP

O37

CFLG/GPIO18

EB

UO

UT1

/GP

O36

CORE-GND

EB

UIN

3/G

PI3

8E

BU

IN2/

GP

I37

CORE-VDD

SC

L1/G

PIO

3/IN

T3

RS

TI

TOU

T1/G

PO

35

LRC

K2/

GP

IO44

OE

SD

A1/

GP

IO55

SD

ATA

O2/

GP

O41

SC

LK2/

GP

IO48

PAD-GND

BUFENB2/GPIO17

TEST3

SD

ATA

O1/

GP

IO25

LRC

K1

LRC

K4/

GP

IO46

SD

ATA

I4/G

PI4

2

SC

LK1

SC

LK4/

GP

IO50

TA/GPIO20

SD

ATA

I1

EB

UIN

1/G

PI3

6

PLLGVDDPLLGGND

PLL1GNDPLL1VDD

PLLCGNDPLLCVDD

IDEDIOW/GPIO14

CRIN

IDEDIOR/GPIO13

IDEIORDY/GPIO16

CL11/GPO39

SU

BR

/GP

IO53

CL16/GPO42

XTRIM/GPO38

TRST/DSCLK

SFS

Y/G

PIO

52

CORE-VDD

R/W

RC

K/G

PIO

51

TMS/BKPT

CORE-GND

TCK

PAD-GND

DBDCPST3/GPIO62

CNPSTCLK/GPIO63

DBDCPST1/GPIO60

PAD-VDD

DBDCPST2/GPIO61

DBDCPST0/GPIO59

TDI/DSI

TEST0

TIN

0/G

PI3

3

HI-Z

DBDCDDATA3/GPIO4/INT4

TOU

T0/G

PO

33

DBDCDDATA1/GPIO1/INT1DBDCDDATA2/GPIO2/INT2

CTS

1/G

PI3

1

DBDCDDATA0/GPIO0/INT0

RX

D1/

GP

I28

TDSO

RTS

1/G

PO

31

SD

ATA

I3/G

PI4

1

CTS

0/G

PI3

0

TXD

1/G

PO

28

RTS

0/G

PO

30

EB

UIN

4/G

PI3

9

SRE/GPIO11

LRC

K3/

GP

IO45

SWE/GPIO12

TXD

0/G

PO

27

SC

LK3/

GP

IO49

RX

D0/

GP

I27

CS

1/G

PIO

58

CORE-GND

A1

TIN1/GPI023

A2

A3

PAD-GND

A4

A6

A5

A8

A7

CORE-VDD

A12

TEST1

PAD-VDD

RP

19B

47

C27

0.1u

F

RP

29D

47

RP

23B

47

RP

34x

4.7

K1

23

45

67

8

12

34

56

78

RP

27D

47

RP

34D

47

RP

44x

4.7

K1

23

45

67

8

12

34

56

78

RP

39C

47

RP

22C

47

C28

0.1u

F

RP

94x

4.7

K1

23

45

67

8

12

34

56

78

RP

24D

47

RP

39D

47

C30

0.1u

F

RP

35D

47

RP

16D

47

C22

1nF

RP

74x

4.7

K1

23

45

67

8

12

34

56

78

RP

30B

47

RP

27A

47

RP

14C

47

RP

19C

47C24

470p

F

RP

28B

47

RP

25A

47

RP

25D

47R

P23

A47

JP5

SD

A0

12

RP

15B

47

C37

470p

F

RP

32C

47

RP

33C

47

RP

32D

47

RP

17A

47

RP

36A

47

RP

28D

47

RP

38D

47

RP

20B

47

RP

21B

47

RP

64x

4.7

K1

23

45

67

8

12

34

56

78

RP

31B

47

RP

31C

47

C33

1nF

RP

38B

47

RP

38C

47

RP

24A

47

RP

21C

47

C29

0.1u

F

RP

23D

47

RP

20C

47

RP

36C

47

RP

18A

47

RP

40A

47

JP6

SC

L01

2

RP

37B

47

C25

470p

F

RP

39B

47

RP

17B

47

RP

32A

47

RP

36B

47

RP

19A

47

RP

35C

47

RP

28A

47

RP

36D

47

RP

22A

47

RP

22D

47

RP

16B

47

RP

15C

47

RP

18D

47

RP

35B

47

RP

14A

47

RP

18B

47

RP

21D

47

RP

40D

47

RP

29B

47

RP

26D

47

RP

22B

47

RP

34A

47

RP

23C

47

C38

470p

F

C18

0.1u

F

RP

14B

47

RP

19D

47

RP

33A

47

RP

32B

47

C31

1nF

C26

470p

F

RP

37A

47

C20

1nF

RP

31A

47

RP

20D

47

RP

27C

47

RP

17D

47

RP

15A

47

RP

38A

47

C35

470p

F

C32

1nF

RP

54x

4.7

K1

23

45

67

8

12

34

56

78

SD

ATA

I1S

DA

TAI3

/GP

I41

SD

ATA

I4/G

PI4

2

SD

ATA

O2

SC

LK1

SC

LK2/

GP

IO48

SC

LK3/

GP

IO49

SC

LK4/

GP

IO50

LRC

K1

LRC

K2/

GP

IO44

LRC

K3/

GP

IO45

LRC

K4/

GP

IO46

EB

UIN

1/G

PI3

6E

BU

IN2/

GP

I37

EB

UIN

3/G

PI3

8E

BU

IN4/

GP

I39

EB

UO

UT1

/GP

O36

EB

UO

UT2

/GP

O37

SD

ATA

O1/

GP

IO25

RX

D0/

GP

I27

-CTS

0/G

PI3

0

RX

D1/

GP

I28

-CTS

1/G

PI3

1

TXD

0/G

PO

27-R

TS0/

GP

O30

TXD

1/G

PO

28-R

TS1/

GP

O31

TOU

T0/G

PO

33TO

UT1

/GP

O35

TIN

0/G

PI3

3

RC

K/G

PIO

51S

FSY

/GP

IO52

SU

BR

/GP

IO53

SD

A0/

QS

PID

IN

SD

A1/

GP

IO55

SC

L1/G

PIO

3

SC

L0/Q

SP

ICLK

CR

INX

TRIM

/GP

O38

CL1

1/G

PO

39C

L16/

GP

O42

QS

PI_

CS

2/G

PIO

21

QS

PI_

CS

1/G

PIO

24E

F/G

PIO

19C

FLG

/GP

IO18

TIN

1/G

PIO

23Q

SP

I_D

OU

T/G

PIO

26Q

SP

I_C

S0/

GP

IO29

QS

PI_

CS

3/G

PIO

22

IDE

DIO

R/G

PIO

13ID

ED

IOW

/GP

IO14

IDE

IOR

DY

/GP

IO16

BU

FEN

B1/

GP

IO57

BU

FEN

B2/

GP

IO17

SW

E/G

PIO

12S

RE

/GP

IO11

SD

ATA

0_S

DIO

1/G

PIO

54S

DA

TA1_

BS

1/G

PIO

9S

DA

TA_B

S2/

RS

TOS

DA

TA3/

GP

IO56

SC

LKO

UT/

GP

IO15

PS

TCLK

PS

T[3:

0]

DD

ATA

[3:0

]

-TA

CM

DS

DIO

2/G

PIO

34

-RE

SE

T

DS

CLK

DS

I-B

KP

T

DS

O

-OE

R/W

BC

LK

SD

RA

M_C

S2

-CS

1

-SD

RA

S

SD

RA

M_C

S1

-SD

CA

S-S

DW

ES

DU

DQ

MS

DLD

QM

BC

LKE

-CS

0

GP

IO5

GP

IO6

A[2

4:1]

D[3

1:16

]

TCK

HI-Z




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

IMPO

RTA

NT

NO

TE: O

NLY

a 3

.3V

BDM

debu

ggin

g ca

ble

can

be u

sed

with

the

MC

F524

9 pr

oces

sor.

NO

TE: 4

.7K

pul

l up

resi

stor

s ar

e us

ed o

n si

gnal

s -B

KP

T, D

SC

LK,

DS

I, D

SO

, -R

ES

ET

& -T

A.

NO

TE: P

lace

TP

7 &

TP

8 at

the

corn

ers

of th

e P

CB

toal

low

eas

y co

nnec

tion

of 's

cope

pro

be g

roun

d le

ads.

Thes

e te

st p

oint

s ar

e fit

ted

for b

oth

prot

otyp

e an

dpr

oduc

tion

boar

ds.

Mot

orol

a S

PS

TS

PG

- 32

-bit

Em

bedd

ed C

ontro

ller D

ivis

ion

(TE

CD

)

NO

TE: T

est P

oint

s TP

1 to

TP

6 ar

e on

lypo

pula

ted

on p

roto

type

boa

rds.

Ple

ase

use

the

labe

l sho

wn

for e

ach

test

poi

nton

the

silk

scre

en o

f the

PC

B.

JUM

PE

RS

10

& 1

1 S

HO

ULD

BE

INS

TALL

ED

AC

RO

SS

PIN

S 1

&2

DU

RIN

G A

SS

EM

BLY

.

Cor

e V

olta

ge.

I/O o

r Pad

Vol

tage

.

Deb

ug (B

DM

) Por

t & T

est P

oint

s1.

1

MC

F524

9 E

valu

atio

n B

oard

- P

art n

umbe

r RE

1081

1B

A

410

Thur

sday

, Mar

ch 0

7, 2

002

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

DD

ATA

3

DD

ATA

0D

DA

TA2

DD

ATA

[3:0

]

PS

T1P

ST2

DD

ATA

1

PS

T3

PS

T[3:

0]

PS

T0+1

.8V

+3.3

V

+1.8

V+3

.3V

TP7

GR

OU

ND

1

JP11

1

2

3

TP4

CH

IP S

ELE

CT

01 TP

6

CP

U C

LOC

K O

UTP

UT

1TP2

OU

TPU

T E

NA

BLE

1 TP8

GR

OU

ND

1

TP1

TRA

NS

FER

AC

K1 TP

3

RE

AD

/WR

ITE

1

C39

47pF

TP5

CP

U C

LOC

K IN

PU

T1

J2S

hrou

ded

BD

M H

eade

r

1 3 5 7 9 11 13 15 17 19 21 23 25

2 4 6 8 10 12 14 16 18 20 22 24 26

JP10

1

2

3

DS

O

DS

CLK

-BK

PT

DS

I

PS

TCLK

-RE

SE

T

-CS

0R

/W

-OE

BC

LKC

RIN

PS

T[3:

0]

DD

ATA

[3:0

]

-TA




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

NOTE

: sep

arat

ene

twor

k gr

ound

.

NOTE

: sep

arat

ene

twor

k gr

ound

.

NOTE

: sep

arat

ene

twor

k gr

ound

.

NOTE

: Pla

ce v

ia's

on a

ll unu

sed

U5I/O

pin

s. U

5 is

an is

pGAL

whi

chal

lows

re-p

rogr

amm

ing

via J

12.

Mot

orola

SPS

TSP

G -

32-b

it Em

bedd

ed C

ontro

ller D

ivisio

n (T

ECD)

OSC

ILLA

TOR

LAYO

UT F

OO

TPRI

NT F

OR

8 &

14 D

IL O

SC. P

ACKA

GES

NOTE

: JP1

5 is

norm

ally

fitte

d.Re

mov

e to

allo

w us

e of

CS1

with

exp

ansio

n co

nnec

tors

.

10/1

00ba

seT

Ethe

rnet

Por

t & M

agne

tics

1.1

MCF

524

Eval

uatio

n Bo

ard

- Par

t num

ber R

E108

11B

B

510

Mon

day,

Mar

ch 1

8, 2

002

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

A1A2A3A4A5A6A7A8A9A10

A11

A12

A13

A14

A15

A[24

:1]

D16

D17

D18

D19

D20

D21

D22

D23

D27

D28D29D30D31

D26

D24D25

D[31

:16]

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+5V

+3.3

V

+3.3

V

U5isp

GAL

22LV

10-5

LJ P

LCC

28pi

n

1234

5 6 7 8 9 10 11

12131415161718

19202122232425

262728 TCLK

CP/I0I1I2

I3 I4 I5 MO

DEI6 I7 I8

I9I10VSSTDII11I/O9I/O8I/O

7I/O

6I/O

5TD

OI/O

4I/O

3I/O

2

I/O1I/O0VCC

RP10

4x 7

5

12345678

12345678

R86

49.9

U3

25M

hz

1 7814

411

NC GND

CLK

VDD

NCVD

DR8

749

.9

U4

SMSC

LAN

91C1

11-N

E

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

3334353637383940414243444546474849505152535455565758596061626364

6566676869707172737475767778798081828384858687888990919293949596

979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128

VDD

nCSO

UTIO

S0IO

S1IO

S2EN

EEP

EEDO

EEDI

EESK

EECS

AVDD

RBIA

SAG

NDTP

O+

TPO

-AV

DDTP

I+TP

I-AG

NDnL

NKLB

KnL

EDA

nLED

BG

NDM

DIM

DOM

CLK

nCNT

RLIN

TR0

RESE

TnR

DnW

R

VDDnDATACSnCYCLEW/nRnADSARDYGNDnVLBUSAENLCLKnSRDYVDDnLEDVnRDYRTNX25OUTD31D30D29D28GNDD27D26D25D24GNDD23D22D21D20VDDD19D18D1

7D1

6G

NDD15

D14

D13

D12

GNDD1

1D1

0D9D8VD

DA1A2A3A4A5A6A7A8A9A10

A11

A12

A13

A14

A15

GND

nBE0

nBE1

nBE2

nBE3VDD

D7D6D5D4

GNDD3D2D1D0

GNDTX25VDD

TXEN100COL100

TXD3TXD2TXD1TXD0GNDRX25

CRS100VDD

RXD3RXD2RXD1RXD0

RX_DVRX_ERXTAL1XTAL2

C42

0.1u

F

R85

1K

T1

HALO

TG

110-

S050

N5

1 2 3 6 7 891011141516

R121

1K

J12

iSP

Prog

.

1 2 3 4 5 6 7 8

R91

24.9

JP15

12

R92

24.9

C43

1nF

V1 VIA

1

R93

11K

1%

R88

1K

C40

1nF

RP11

4x 1

0K1

23

45

67

8

12

34

56

78

V2 VIA

1C4

40.

1uF

R94

10K

C45

0.1u

FC4

60.

1uF

C47

1nF

C48

1nF

C49

1nF

C41

10nF

J3

Amph

enol

RHJ

S-53

81 R

J45_

LED

1 2 3 4 5 6 7 8

9

13

1112

10

14

1 2 3 4 5 6 7 8 9

13

1112

10

14

RP12

4x 1

0K 12

34

56

78

12

34

56

78

RP45

4x 4

.7K

12

34

56

78

12

34

56

78

RP13

4x 1

0K 12

34

56

78

12

34

56

78

R89

24.9

R90

24.9

A[24

:1]

D[31

:16]

BCLK

-RES

ET

-CS1

R/W

-TA_

IN

GPI

O6

-OE-T

A




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Mot

orol

a S

PS

TS

PG

- 32

-bit

Embe

dded

Con

trolle

r Div

isio

n (T

ECD

)

NO

TE: P

leas

e pl

ace

D13

thro

ugh

D21

dio

des

toge

ther

in a

line.

Analogue Ground

MC

F524

9 E

xpan

sion

Con

nect

ors

1.1

MC

F524

9 E

valu

atio

n B

oard

- P

art n

umbe

r RE

1081

1B

C

610

Thur

sday

, Mar

ch 2

1, 2

002

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

D[3

1:16

]

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

A[2

4:1]

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

DD

ATA

3

DD

ATA

1

PS

T1

PS

T0

DD

ATA

2

DD

ATA

[3:0

]

PS

T2

PS

T[3:

0]P

ST3

DD

ATA

0

+1.8

V+1

.8V

+1.8

V+1

.8V

+3.3

V+3

.3V

+5V

+5V

+3.3

V+3

.3V

+5V

+5V

+3.3

V

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V

+5V

+1.8

V

+3.3

V

D14

RE

D L

ED

R11

747

0R

109

470

D21

RE

D L

ED

D17

RE

D L

ED

C66

470p

F

J5

AM

P 1

7798

3-5

120w

ay S

MT

Rec

epta

cle

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

R11

3

470

J4

AM

P 1

7798

3-5

120w

ay S

MT

Rec

epta

cle

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

C64

470p

FC

6310

nFC

6210

nFC

6547

0pF

R12

3

4.7K

C61

470p

FC

6047

0pF

C59

470p

FC

5847

0pF

R11

447

0

C57

10nF

R11

547

0

C56

10nF

D19

RE

D L

ED

D18

RE

D L

ED

C53

0.1u

FC

5410

nFC

5510

nFC

501n

F

R11

647

0

D15

RE

D L

ED

C51

1nF

D20

RE

D L

ED

R11

147

0

C67

470p

FC

520.

1uF

D13

RE

D L

ED

D16

RE

D L

ED

R11

047

0R

112

470

D[3

1:16

]

A[2

4:1]

SD

RA

M_C

S2

SD

RA

M_C

S1

-CS

0

-SD

RA

S

-SD

CA

S-S

DW

E

SD

LDQ

M

BC

LKE

R/W -O

E

BC

LK

SD

UD

QM

DS

O

-TA

GP

IO5

GP

IO6

-RE

SE

T

SD

ATA

O1/

GP

IO25

SD

ATA

O2

SC

LK1

SC

LK2/

GP

IO48

SC

LK4/

GP

IO50

LRC

K1

LRC

K2/

GP

IO44

LRC

K3/

GP

IO45

LRC

K4/

GP

IO46

DD

ATA

[3:0

]

PS

T[3:

0]

PS

TCLK

SC

LKO

UT/

GP

IO15

SD

ATA

3/G

PIO

56

SD

ATA

_BS

2/R

STO

SD

ATA

1_B

S1/

GP

IO9

SD

ATA

0_S

DIO

1/G

PIO

54

SR

E/G

PIO

11

CM

DS

DIO

2/G

PIO

34B

UFE

NB

2/G

PIO

17

BU

FEN

B1/

GP

IO57

IDE

IOR

DY

/GP

IO16

IDE

DIO

R/G

PIO

13

IDE

DIO

W/G

PIO

14

QS

PI_

DO

UT/

GP

IO26

QS

PI_

CS

0/G

PIO

29

TIN

1/G

PIO

23

CFL

G/G

PIO

18

EF/

GP

IO19

QS

PI_

CS

1/G

PIO

24

QS

PI_

CS

3/G

PIO

22Q

SP

I_C

S2/

GP

IO21

CL1

6/G

PO

42

CL1

1/G

PO

39X

TRIM

/GP

O38

CR

IN

EB

UIN

1/G

PI3

6E

BU

IN2/

GP

I37

EB

UIN

3/G

PI3

8

EB

UIN

4/G

PI3

9

EB

UO

UT1

/GP

O36

EB

UO

UT2

/GP

O37

RX

D0/

GP

I27

TXD

0/G

PO

27

-RTS

0/G

PO

30

-CTS

0/G

PI3

0

RX

D1/

GP

I28

TXD

1/G

PO

28

-RTS

1/G

PO

31

-CTS

1/G

PI3

1

TOU

T0/G

PO

33

TOU

T1/G

PO

35

TIN

0/G

PI3

3

RC

K/G

PIO

51S

FSY

/GP

IO52

SU

BR

/GP

IO53

SD

A0/

QS

PID

IN

SC

L0/Q

SP

ICLK

SD

A1/

GP

IO55

SC

L1/G

PIO

3

-TA

_IN

SD

ATA

I4/G

PI4

2

SD

ATA

I3/G

PI4

1

-CS

1

HI-Z

SD

ATA

I1

TCK

SC

LK3/

GP

IO49

SW

E/G

PIO

12

DS

I

DS

CLK

-BK

PT




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Mot

orola

SPS

TSP

G -

32-b

it Em

bedd

ed C

ontro

ller D

ivisio

n (T

ECD)

Flas

h m

emor

ySD

RAM

mem

ory

DEFA

ULT

SETT

ING

- JU

MPE

R 12

SHO

ULD

BE IN

STAL

LED

ACRO

SS P

INS

1&2

Flas

h &

SDRA

M m

emor

y1.

1

MCF

5249

Eva

luat

ion

Boar

d - P

art n

umbe

r RE1

0811

B

B

710

Thur

sday

, Mar

ch 0

7, 2

002

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

D24

D20

D18

D22

D16

D29

D27

D23

D19

D25

D22

D29

D31

D23

D27

D16

D20

D19

D17

D18

D26

D31

D28

D17

D21

D30

D28

D24

D30

D26

D[31

:16]

D25

D21

D[31

:16]

A[24

:1]

A[24

:1]

A17

A7A8

A20

A1

A18

A10

A18

A19

A[24

:1]

A20

A14

A6A11

A17

A19

A22

A11

A13

A9 A2A5

A12

A16

A12

A[24

:1]

A16

A21

A15

A15

A4

A14

A13

A10

A9

A3

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V

C72

0.1u

FC7

10.

1uF

R103

4.7K

C73

1nF

C74

1nF

U7 K4S6

4163

3D-G

(4M

x16)

52P

BGA

(4x1

3)

A6

A5 B6

F5

C6 D6

E5

D5 E6 G6

B5 H5 H6J6 J5 J2

L6L5 M6

M5 N5

G2

G5

N2 M2

M1 L2 L1 K2

J1H1H2N1

G1 F1

C5

E1 D2

F2

D1 C1E2

B1 A2

A1K6 K5

B2

F6

N6 C2

K1

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

DQ7

VDDQ

DQM

L

WE#

CAS#

RAS# CS

#

A10

A0 A1 A2 A3

VDD

VSS

A4 A5 A6 A7 A8 A9CK

ECL

K

DQM

H

VSS

DQ8

DQ9

VSSQ

DQ10

DQ11

VDDQ

DQ12

DQ13

VSSQ

DQ14

DQ15

VSS

BA0

BA1

VSSQ

DQ6

VDD

VDDQ

A11

C75

1nF

C76

1nF

C70

0.1u

F

R95

4.7K

JP12 16

MBi

t Fla

sh B

oot

1

2

3

U6

AM29

LV16

0DB9

0EC

(1M

X16

bit)

48pi

n TS

OP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24252627282930313233343536373839404142434445464748

A15

A14

A13

A12

A11

A10

A9 A8 A19

NC WE#

RESE

T#NC NC RY

/BY#

A18

A17

A7 A6 A5 A4 A3 A2 A1A0CE

#VS

SO

E#DQ

0DQ

8DQ

1DQ

9DQ

2DQ

10DQ

3DQ

11VC

CDQ

4DQ

12DQ

5DQ

13DQ

6DQ

14DQ

7DQ

15/A

-1VS

SBY

TE#

A16

C69

0.1u

F

D[31

:16]

A[24

:1]

-CS0

-OE

R/W

-RES

ET

BCLK

EBC

LK

SDRA

M_C

S1-S

DW

E

SDLD

QM

SDUD

QM

-SDR

AS-S

DCAS




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3.3V

Reg

ulat

or

Auga

t 25V

-02

2-wa

y Ba

re W

irePo

wer

Conn

ecto

r

NOTE

: Sch

ottk

y Di

ode

prev

ents

exc

essiv

edi

ffere

nce

betw

een

3.3V

& 1

.8V

rails

, at p

ower

dow

n

5.0V

Reg

ulat

or

Powe

r Jac

k Co

nnec

tor -

2.1m

m d

iam

eter

1.8V

Reg

ulat

or

JP8

SHO

ULD

BEIN

STAL

LED

DURI

NGAS

SEM

BLY

NOTE

: Dio

des

prev

ent e

xces

sive

diffe

renc

e be

twee

n 3.

3V &

1.8

Vra

ils, a

t pow

er u

p

All c

aps

less

than

1uF

are

0805

bod

ysiz

e

All r

esist

ors

are

0805

bod

y siz

e.

JP9

SHO

ULD

BEIN

STAL

LED

DURI

NGAS

SEM

BLY

HARD

_RES

ET

Mot

orola

SPS

TSP

G -

32-b

it Em

bedd

ed C

ontro

ller D

ivisio

n (T

ECD)

DC v

olta

ge in

put r

ange

+7

to +

14V

Debo

unce

d IR

Q7

Sign

al

NOTE

: the

pos

itive

term

inal

of e

ach

powe

rco

nnec

tor i

s sh

own

on th

e sil

kscr

een

ofth

e PC

B

+

+

-

-

Abor

t/IRQ

7

Powe

r Sup

ply,

Res

et &

Clo

ck O

scilla

tor

1.1

MCF

5249

Eva

luat

ion

Boar

d - P

art n

umbe

r RE1

0811

B

B

810

Thur

sday

, Mar

ch 2

1, 2

002

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

+1.8

V+3

.3V

+5V

+1.8

VP

+5V

+3.3

V+1

.8V

+3.3

V

+3.3

V

+3.3

V

+3.3

VP

+3.3

V

+3.3

V

+5V

+1.8

V

+3.3

V

+1.8

V

+3.3

V+3

.3V

C81

0.1u

F

P2

1 2

C82

0.1u

F

D7

MBR

S340

T3

21

C83

1nF

C88

0.1u

F

C84

1nF

U8LT

1086

CM

3

1

2VI

N

ADJ

VOUT

D5 RED

LED

D12

+5V

GRE

EN P

OW

ER L

ED

D1 MBR

S340

T3

21

C92

22pF

R98

120

R106

560

C85

1nF R1

0056

C90

330u

F

L1 25uH

U10

NC7S

ZU04

1 2 3

5 4

OE

A GND

VCC Y

C91

0.1u

F

C97

330u

F

S1

KS11

R23C

QD

RESE

T

P1 Switc

hcra

ft RA

PC71

2123

JP9

12

D6 MBR

S340

T3

21C86

10uF

U11

LM25

96S-

3.3

12

5

3

4

6

VIN

VOUT

~ON/

OFF

GND

FB

TAB

R97

270

C94

0.1u

F

X111

.289

6 M

Hz 12

C115

1nF

D2

MBR

S340

T3

21

C98

0.1u

F

S2 KS11

R22C

QD

C93

22pF

D8 MBR

S340

T3

21

R96

1K

J11

PC p

ower

1 2 3 4

+12V

GND

GND +5

V

JP8

12

C87

330u

F

R99

3K

U9

MAX

6355

LSUT

-T

1 2 3456

RST

GND M

RVc

c3RS

TIN

Vcc5

D3 MRA

4003

T3

D10

RED

LED

D11

+3.3

V G

REEN

PO

WER

LED

C96

1000

uF

R105

270

R104

270

R101

1M

D4

MRA

4003

T3

D22

+1.8

V G

REEN

PO

WER

LED

L2

25uH

R118

22

U18

TLC7

733I

D

8 7 5 6 1

432VC

CSE

NSE

RESE

T

RESE

T

CONT

ROL

GND

CTRESI

N

F1

5A F

ast b

low.

C95

1nF

R122

4.7K

U12

LM25

96S-

5

12

53

46

VIN

VOUT

~ON/

OFF

GND

FBTAB

CRIN

-RES

ET

SDRA

M_C

S2




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TERM

INAL

PO

RT9-

WAY

D-T

YPE

(Fem

ale)

AUXI

LLAR

Y PO

RT9-

WAY

D-T

YPE

(Fem

ale)

NOTE

: The

I2C/

Mbu

s on

the

MCF

5249

will

supp

ort b

oth

3.3V

& 5

V de

vices

.

NOT

POPU

LATE

D AT

ASS

EMBL

Y.

NOT

POPU

LATE

D AT

ASS

EMBL

Y.

Mot

orola

SPS

TSP

G -

32-b

it Em

bedd

ed C

ontro

ller D

ivisio

n (T

ECD)

RS23

2 Tr

ansc

eiver

.

RS23

2 Tr

ansc

eiver

.

RS23

2 Se

rial,

I2C

& Q

SPI I

nter

face

s1.

1

MCF

5249

Eva

luat

ion

Boar

d - P

art n

umbe

r RE1

0811

B

B

910

Thur

sday

, Mar

ch 0

7, 2

002

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

+3.3

V

+3.3

V

+5V

+3.3

V

+3.3

V

+3.3

V+5

V

+5V

C110

0.22

uF

C104

0.22

uF

C99

0.22

uF

C105

0.22

uF

J6

QSP

I con

nect

or 0

.1 p

itch

1 2 3 4 5 6 7 8 9 10

C106

0.22

uF

P45 9 4 8 3 7 2 6 1

RP44

4x 4

.7K

12

34

56

78

12

34

56

78

C100

0.22

uFC1

011n

F

U13

MAX

3225

CAP

1 2 3 4 5 6 7 8 9 101112131418 1516171920

READ

YC1

+V+ C1

-C2

+C2

-V- T2

OUT

R2IN

R2O

UTIN

VALI

DT2

INT1

INFO

RCEO

N

GND

R1O

UTR1

INT1

OUT

VCC

FORC

EOFF

U14

MAX

3225

CAP

1 2 3 4 5 6 7 8 9 101112131418 1516171920

READ

YC1

+V+ C1

-C2

+C2

-V- T2

OUT

R2IN

R2O

UTIN

VALI

DT2

INT1

INFO

RCEO

N

GND

R1O

UTR1

INT1

OUT

VCC

FORC

EOFF

C109

0.22

uF

C107

1nF

C103

0.22

uF

P35 9 4 8 3 7 2 6 1

C108

0.1u

F

C102

0.1u

F

J7 I2C

Mol

ex C

onn.

715

65

1 2 3 4

SCLK

4/G

PIO

50

LRCK

4/G

PIO

46

SDAT

AI3/

GPI

41

SDAT

AI4/

GPI

42

TXD0

/GPO

27

TXD1

/GPO

28-R

TS1/

GPO

31

RXD0

/GPI

27

-CTS

0/G

PI30

RXD1

/GPI

28

-CTS

1/G

PI31

SDA1

/GPI

O55

SCL1

/GPI

O3

SCL0

/QSP

ICLK

SDA0

/QSP

IDIN

QSP

I_DO

UT/G

PIO

26Q

SPI_

CS0/

GPI

O29

QSP

I_CS

1/G

PIO

24Q

SPI_

CS2/

GPI

O21

QSP

I_CS

3/G

PIO

22

-RTS

0/G

PO30




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Mot

orola

SPS

TSP

G -

32-b

it Em

bedd

ed C

ontro

ller D

ivisio

n (T

ECD)

Bi-d

irect

iona

l

Uni-d

irect

iona

l

IDE

Inte

rface

1.1

MCF

5249

Eva

luat

ion

Boar

d - P

art n

umbe

r RE1

0811

B

B

1010

Thur

sday

, Mar

ch 2

1, 2

002

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

A[24

:1]

A1 A2 A3 A4 A5

IDE_

D11

IDE_

CS1

IDE_

A2

IDE_

D1

IDE_

D13

IDE_

D14

IDE_

A1ID

E_A0

IDE_

D12

IDE_

D15

IDE_

D10

IDE_

D2

IDE_

CS0

IDE_

D8

IDE_

D12

IDE_

D14

IDE_

D13

IDE_

CS0

IDE_

A2ID

E_A0

IDE_

D15

IDE_

D8ID

E_D7

IDE_

D4ID

E_CS

1

IDE_

D3

IDE_

D9

IDE_

D11

IDE_

D5

IDE_

D10

IDE_

D6

IDE_

D9

IDE_

RESE

T

IDE_

D0

IDE_

D1ID

E_D2

IDE_

D3ID

E_D4

IDE_

D5ID

E_D6

IDE_

D7

IDE_

IOW

IDE_

IOR

IDE_

IOCH

RDY

IDE_

IRQ

IDE_

ACTI

VITY

IDE_

D0

IDE_

A1

+3.3

V +3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

D9 RED

IDE

LED

C113

1nF

RP41

4x 4

.7K

12

34

56

78

12

34

56

78

RP42

4x 1

0K

12

34

56

78

12

34

56

78

R102

270

C111

1nF

U17 MC7

4LCX

1624

5DT

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1 48 25 24 4 10 15 21

28 34 39 4547 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 7 18 31 42

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1DIR

1OE

2OE

2DIR

GND

GND

GND

GND

GND

GND

GND

GND1A

11A

21A

31A

41A

51A

61A

71A

82A

12A

22A

32A

42A

52A

62A

72A

8

VCC

VCC

VCC

VCC C1

140.

1uF

U16 MC7

4LCX

1624

5DT

2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1 48 25 24 4 10 15 21

28 34 39 4547 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 7 18 31 42

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

1DIR

1OE

2OE

2DIR

GND

GND

GND

GND

GND

GND

GND

GND1A

11A

21A

31A

41A

51A

61A

71A

82A

12A

22A

32A

42A

52A

62A

72A

8

VCC

VCC

VCC

VCCC1

120.

1uF

J8

HDR2

0 X

2 Sh

roud

ed

252321191715131197531

2624222018161412108642

2728

2930

3132

3334

3536

3738

3940

252321191715131197531

2624222018161412108642

2728

2930

3132

3334

3536

3738

3940

R/W

BUFE

NB2/

GPI

O17

D[31

:16]A[

24:1

]

EF/G

PIO

19

GPI

O5

IDEI

ORD

Y/G

PIO

16ID

EIO

R/G

PIO

13ID

EIO

W/G

PIO

14

Appendix B: Audio Daughter Card Schematics



7 Appendix B: Audio Daughter Card Schematics




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Hier

arch

ical B

lock

Dia

gram

1.2

MCF

5249

Eva

luat

ion

Boar

d - A

udio

Dau

ghte

r Car

d

B

17

Wed

nesd

ay, O

ctob

er 2

3, 2

002

Mot

orol

a SP

S TS

PG -

32-b

it Em

bedd

ed C

ontro

ller D

ivis

ion

(TEC

D)Ti

tle

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

Shee

t 4

Audi

oSDAT

AO2

CL11

CL16

SCLK

2LR

CK2

SCLK

1LR

CK1

SDAT

AO1

EBUI

N1EB

UIN2

EBUI

N3EB

UIN4

EBUO

UT1

EBUO

UT2

SMUT

E

Shee

t7

CD In

terfa

ce A

dapt

ers

Shee

t 3

Flas

h M

edia

CLK

CMD

CDWP

DAT0

DAT1

DAT2

DAT3

Shee

t 5

USBA[

24:1

]D[

31:1

6]

CS1

RD WR

INT1

INT2

BUFE

NB1

RESE

T

Shee

t 6

Trio

Inte

rface

ADIN

0AD

IN1

ADIN

2AD

IN3

ADO

UT

SDAT

AISC

LKLR

CKEF CF

LGSD

ASC

LRA

BSI

LDPO

RES

SMUT

ESL

EEP

RESU

ME

HOLD

DOO

RSW

RESE

T

PLAY

SID

LCDC

LKRS LC

DRST

CS2

FOK

RF-

PWR

RW/R

OM

/OFF

1X/2X

CD-S

QCK

CD-D

EM

CD-S

QSO

Shee

t 2

M52

49C3

Inte

rface

EBUI

N1/G

PI36

EBUI

N2/G

PI37

EBUI

N3/A

DIN0

/GPI

38EB

UIN4

/ADI

N1/G

PI39

EBUO

UT1/

GPO

36EB

UOUT

2/G

PO37

SDAT

AO1/

GPI

O25

LRCK

1SC

LK1

SDAT

AO2/

GPO

41LR

CK2/

GPI

O44

SCLK

2/G

PIO

48

CL11

/GPO

39CL

16/G

PO42

RXD1

/ADI

N2/G

PI28

CTS1

/ADI

N3/G

PI31

TOUT

1/AD

OUT

/GPO

35

SCLK

4/G

PIO

50LR

CK4/

GPI

O46

EF/G

PIO

19CF

LG/G

PIO

18

RTS0

/GPO

30RT

S1/G

PO31

RCK/

GPI

O51

SFSY

/GPI

O52

SUBR

/GPI

O53

TIN0

/GPI

33TI

N1/G

PIO

23RX

D0/G

PI27

RESE

T

CTS0

/GPI

30

SDAT

A0_S

DIO

1/G

PIO

54SD

ATA1

_BS1

/GPI

O9

SDAT

A2_B

S2/R

STO

SDAT

A3/G

PIO

56

SRE/

GPI

O11

CMD_

SDIO

2/G

PIO

34

SWE/

GPI

O12

SCLK

_OUT

/GPI

O15

A[24

:1]

D[31

:16]

BUFE

NB1/

GPI

O57

OE

R/W

QSP

IDO

UT/G

PIO

26SC

L0/Q

SPIC

LKQ

SPIC

S0/G

PIO

29Q

SPIC

S1/G

PIO

24Q

SPIC

S2/G

PIO

21

TXD0

/GPO

27TX

D1/G

PO28

TOUT

0/G

PO33

SDAT

AI3/

GPI

41

SCLK

3/G

PIO

49

LRCK

3/G

PIO

45

QSP

ICS3

/GPI

O22

SDAT

AI1

SDAT

AI4/

GPI

42

DDAT

A0/G

PIO

0DD

ATA1

/GPI

O1

CS1

A[24

:1]

D[31

:16]




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SDAT

AI1

is c

onne

cted

to

the

ADC

on t

he m

othe

rboa

rd

IIS2

als

o dr

ives

the

hea

dpho

neDA

C on

the

mot

herb

oard

DAC

conf

igur

atio

n op

tion

s

AK43

93 i

n pa

rall

el m

ode,

IIS

com

pati

able

or 2

0-bi

t LS

B ju

stif

ied

via

DIF1

Do w

e ne

ed a

ny m

ore

sign

al c

ondi

tion

ing

befo

re t

he j

acks

AK43

93 i

n pa

rall

el m

ode,

IIS

com

pati

able

or 2

0-bi

t LS

B ju

stif

ied

via

DIF1

Audi

o In

terfa

ce1.

2

MCF

5249

Eva

luat

ion

Boar

d - A

udio

Dau

ghte

r Car

d

B

27

Wed

nesd

ay, O

ctob

er 2

3, 2

002

Mot

orol

a SP

S TS

PG -

32-b

it Em

bedd

ed C

ontro

ller D

ivis

ion

(TEC

D)Ti

tle

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

CKS2

CKS1

CKS0

DFS

DEM

0DE

M1

MCL

KPD

N

MUT

E

DEM

0

CKS2

DFS

CKS1

PDN

DFS

DEM

0

CKS0

DEM

1

CKS0

DEM

1

CKS1

CKS2

MUT

E

MCL

K

PDN

MCL

K

DIF1

DIF1

MUT

EDIF1

+3.3

V

+3.3

V

+3.3

V

+5V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+5V

-VS

+VS

-VS

+VS

+VS

+VS

-VS

-VS

+VS

+VS

-VS

-VS

+5VD

+5VD

+5VD

+5VD

+5VD

+5VD

-VS

+VS

+3.3

VVC

C

C27

0.1u

FC2

810

uF 1

6V

C23

0.1u

F

C29

1nF

R30

13K

R28

22K

R27

18K

R25

22K

C21

0.1u

F

C37

100p

F

C19

0.1u

F

C46

1nF

R26

13K

R29

18K

C20

4.7u

F 25

V

C47

100p

F

C22

4.7u

F 25

V

JP2 123 R40

470R

JP4 1 2 3

R33

18K

R31

22K

R32

13K

R35

18K

R36

13K

R34

22K

C54

100p

F

R38

1K

C52

100p

F

C53

1nF

U7A

74HC

U04

12

U7B

74HC

U04

34

R2O

UT1

RCA

PHO

NO J

ACK

1

2

L2O

UT1

RCA

PHO

NO J

ACK

1

2

C24

10uF

16V

R37

4K7

C50

1nF

DCDC

1

NMA0

512S

1 2 4 5 6

VCC

GND

-V 0V +V

C48

0.1u

F

U5 AK43

93

1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728

DVSS

DVDD

MCL

KPD

NBI

CKSD

ATA

LRCK

SMUT

E/CS

NDF

SDE

M0/

CCLK

DEM

1/CD

TIDI

F0DI

F1DI

F2BV

SSVR

EFL

VREF

HAV

DDAV

SSAO

UTR-

AOUT

R+AO

UTL-

AOUT

L+VC

OM

P/S

CKS0

CKS1

CKS2

C35

10uF

16V

C36

0.1u

F

C44

0.1u

F

L4 FERR

ITE_

BEAD

12

C49

10uF

16V

C45

10uF

16V

JP3

HEAD

ER 6

X2

12

34

56

78

910

1112

JP1A

1 4 7 10 13 16 19 22

1 4 7 10 13 16 19 22

JP1C

3 6 9 12 15 18 21 24

3 6 9 12 15 18 21 24

JP1B

2 5 8 11 14 17 20 23

2 5 8 11 14 17 20 23

U7C

74HC

U04

56

U7F

74HC

U04

1312

U7E

74HC

U04

1110

U7D

74HC

U04

98

LK73

12 R7

010

K

C34

0.1u

F

C42

4.7u

F 25

VC4

34.

7uF

25V

C58

47pF

LK25

12

C16

10uF

16V

C17

0.1u

F

LK22

12

LK26

12

LK27

12

C59

0.1u

F

LK24

12

U10

GP1

FA55

0TZ

1 2 3

VIN

VCC

GND

R1O

UT1

RCA

PHO

NO J

ACK

1

2

L1O

UT1

RCA

PHO

NO J

ACK

1

2

LK23

12

LK29

12

LK28

12

C60

4.7u

F 16

V

C57

0.1u

FU6 OPA

2134

/SO

123 45 6

7

8

OUT

A-IN

A+I

NA

V-+INB

-INB

OUT

B

V+

L1 FERR

ITE_

BEAD

12

C55

10nF

U4 OPA

2134

/SO

123 45 6

7

8

OUT

A-IN

A+I

NA

V-+INB

-INB

OUT

B

V+

U3 AK43

93

1 2 3 4 5 6 7 8 9 10 11 12 13 141516171819202122232425262728

DVSS

DVDD

MCL

KPD

NBI

CKSD

ATA

LRCK

SMUT

E/CS

NDF

SDE

M0/

CCLK

DEM

1/CD

TIDI

F0DI

F1DI

F2BV

SSVR

EFL

VREF

HAV

DDAV

SSAO

UTR-

AOUT

R+AO

UTL-

AOUT

L+VC

OM

P/S

CKS0

CKS1

CKS2

R14

13K

R17

18K

R18

13K

L3 FERR

ITE_

BEAD

12

R16

22K

R15

18K

EBUO

UT1

RCA

PHO

NO J

ACK

1

2

L2 FERR

ITE_

BEAD

12

R13

22K

EBUI

N1RC

A PH

ONO

JAC

K1

2

C18

100p

F

C25

1nF

T1 TTW

B101

0

16

34

C26

100p

F

C39

4.7u

F 25

VC4

00.

1uF

C38

0.1u

FC4

14.

7uF

25V

T2 TTW

B101

0

16

34U8 G

P1FA

550R

Z

1 2 3

VCC

GND

VOUT

R22

22K

R21

18K

R19

22K

R20

13K

R23

18K

R24

13K

C32

1nF

C33

100p

F

C31

100p

F

C56

1uF

R41

180R

R42

110R

R39

110R

EBUO

UT1

EBUO

UT2

EBUI

N1EB

UIN2

EBUI

N3EB

UIN4

SDAT

AO1

LRCK

1

SCLK

1

CL11

SCLK

2

LRCK

2

CL16

SDAT

AO2

SMUT

E




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Note

s :

CMD,

DAT

1, C

D an

d WP

sig

nals

dri

ve L

ED's

on

the

moth

erbo

ard.

It i

s po

ssib

le t

o co

nnec

t to

eit

her

the

SD o

r Me

mory

Sti

ckin

terf

ace,

but

not

bot

h si

mult

aneo

usly

.

The

Writ

e Pr

otec

t an

d Ca

rd D

etec

t si

gnal

s on

the

SD

inte

rfac

e ca

n be

con

figu

red

as e

ithe

r ac

tive

hig

h or

low

.

Memo

ry S

tick

car

d in

sert

ion/

extr

acti

on i

s no

rmal

ly u

sed

topr

ovid

e th

e ap

prop

riat

e po

wer

cycl

ing,

but

it

is a

lso

poss

ible

to

over

ride

thi

s us

ing

the

CD s

igna

l.

Flas

h M

edia

Inte

rface

1.2

MCF

5249

Eva

luat

ion

Boar

d - A

udio

Dau

ghte

r Car

d

B

37

Wed

nesd

ay, O

ctob

er 2

3, 2

002

Mot

orol

a SP

S TS

PG -

32-b

it Em

bedd

ed C

ontro

ller D

ivis

ion

(TEC

D)Ti

tle

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

+3.3

V

+3.3

V+3

.3V

+3.3

V

+3.3

V+3

.3V

+3.3

V+3

.3V

+3.3

V+3

.3V

J10

Mem

ory

Stick1 2 3 4 5 6 7 8 9 10

VSS BS

VCC

SDIO

RSVD IN

SRS

VDSC

LKVC

CVS

S

J9 FPS0

09-2

203-

10

1 2 3 4 5 6 7 8 9101112

CD/D

AT3

CMD

VSS

VDD

CLK

VSS

DAT0

DAT1

DAT2

CDCD/W

P-CO

MW

P

R72

68K

R74

68K

R73

68K

R76

68K

R75

68K

R46

4K7

R47

1KQ

1BC

807

R45

4K7

LK30

12

C62

4.7u

F 16

V

LK32

12

LK31

12

LK35

12

LK34

12

LK33

12

LK37

12

LK36

12

C61

4.7u

F 16

V

R43

10K

DAT0

DAT1

DAT2

DAT3

CMD

WP

CDCLK




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Anal

ogue

Gro

und

M52

49C3

Inte

rface

1.2

MCF

5249

Eva

luat

ion

Boar

d - A

udio

Dau

ghte

r Car

d

B

47

Frid

ay, S

epte

mbe

r 13,

200

2

Mot

orol

a SP

S TS

PG -

32-b

it Em

bedd

ed C

ontro

ller D

ivis

ion

(TEC

D)Ti

tle

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

D[31

:16]

A[24

:1]

+3.3

V+3

.3V

+5V

+5V

+3.3

V+3

.3V

+5VD

+5VD

BUFE

NB2

1

SDRA

MCS

21

TA1

J5

AMP

1779

83-5

120

way

SMT

Rece

ptac

le

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

J4

AMP

1779

83-5

120

way

SMT

Rece

ptac

le

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

5152

5354

5556

5758

5960

6162

6364

6566

6768

6970

7172

7374

7576

7778

7980

8182

8384

8586

8788

8990

9192

9394

9596

9798

9910

010

110

210

310

410

510

610

710

810

911

011

111

211

311

411

511

611

711

811

912

0

GPI

O5

1

SDA0

1

GPI

O6

1

SCL1

1

SDA1

1

XTRI

M1

DDAT

A21

DDAT

A31

PST0

1

IDEI

ORD

Y1

PST1

1

IDED

IOR

1

PST2

1

IDED

IOW

1

PST3

1

PSTC

LK1

SDAT

A0_S

DIO

1/G

PIO

54

SDAT

A1_B

S1/G

PIO

9

SDAT

A2_B

S2/R

STO

SDAT

A3/G

PIO

56

SWE/

GPI

O12

SRE/

GPI

O11

CMD_

SDIO

2/G

PIO

34

SCLK

_OUT

/GPI

O15

EBUI

N1/G

PI36

EBUI

N3/A

DIN0

/GPI

38

EBUI

N4/A

DIN1

/GPI

39

EBUO

UT1/

GPO

36

EBUO

UT2/

GPO

37

SDAT

AO1/

GPI

O25

LRCK

1

SCLK

1

SDAT

AO2/

GPO

41LR

CK2/

GPI

O44

SCLK

2/G

PIO

48

CL11

/GPO

39

CL16

/GPO

42

RXD1

/ADI

N2/G

PI28

CTS1

/ADI

N3/G

PI31

EF/G

PIO

19

CFLG

/GPI

O18

TOUT

1/AD

OUT

/GPO

35

SCLK

4/G

PIO

50

LRCK

4/G

PIO

46

RTS0

/GPO

30

RTS1

/GPO

31

RCK/

GPI

O51

SFSY

/GPI

O52

SUBR

/GPI

O53

TIN0

/GPI

33

TIN1

/GPI

O23

RXD0

/GPI

27

RESE

T

CTS0

/GPI

30

A[24

:1]

D[31

:16]

R/W OE

EBUI

N2/G

PI37

QSP

ICS0

/GPI

O29

QSP

ICS1

/GPI

O24

QSP

ICS2

/GPI

O21

QSP

IDO

UT/G

PIO

26

SCL0

/QSP

ICLK

TXD0

/GPO

27

TXD1

/GPO

28

TOUT

0/G

PO33

LRCK

3/G

PIO

45

SCLK

3/G

PIO

49

SDAT

AI3/

GPI

41

QSP

ICS3

/GPI

O22

SDAT

AI1

BUFE

NB1/

GPI

O57

SDAT

AI4/

GPI

42

CS1

DDAT

A0/G

PIO

0DD

ATA1

/GPI

O1







5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DMA

inte

rfac

e

500m

A pe

r ch

anne

l

Host

OTG

Mini

-AB

Rece

ptac

le

Devi

ce

USB

Inte

rface

1.2

MCF

5249

Eva

luat

ion

Boar

d - A

udio

Dau

ghte

r Car

d

B

67

Wed

nesd

ay, O

ctob

er 2

3, 2

002

Mot

orol

a SP

S TS

PG -

32-b

it Em

bedd

ed C

ontro

ller D

ivis

ion

(TEC

D)Ti

tle

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

A1 A2 D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

A[24

:1]

D[31

:16]

+3.3

V+3

.3V

+3.3

V+5

VD

+3.3

V

+3.3

V+3

.3V

+5VD

+3.3

V+3

.3V

+3.3

V

U1 ISP1

362

156 51554950 545345

3224 25 28 29 31

364647 33 34 35 39 94

21 20 22 30

4861 62

52 58

23 59

1914

603863 64

2726

2 3 5 6 7 8 10 11 12 13 15 16 17 18

40

4443

3742 41 57

DGND

VCC(

5.0)

AGND

VBUS

OTG

_DM

1O

TG_D

P1

CP_C

AP2

CP_C

AP1

OTG

MO

DE

RESE

T

DREQ

1DR

EQ2

DACK

1DA

CK2

INT2

H_P

SW2

H_DM

2H_

DP2

H_SU

SPD/

WUP

D_SU

SPD/

WUP

H_P

SW1

GL

DGND

VCC(

3.3)

CS RD WR

INT1

IDA0 A1

VCC(

3.3)

VCC(

3.3)

TEST

0TE

ST1

DGND

VCC(

3.3)

TEST

2

CLKO

UT

D0 D1

DGND

VCC(

3.3)

D2 D3 D4 D5 D6 D7 D8 D9 D10

D11

D12

D13

D14

D15

VCC(

3.3)

X2X1

DGND

H_O

C1H_

OC2

DGND

J6 MIN

IAB

1 2 3 4 5

R622

R

R522

R

J8 USB-

CONA

1 2 3 4

C10

1nF

C11

0.1u

FC8 1n

FC9 0.

1uF

C7 0.1u

FC6 1n

F

U2 MIC

2026

1 2 3 45678

ENA

FLG

AFL

GB

ENB

OUT

BG

NDINO

UTA

R10

10K

GL1

R91K

C3 10nF

R11

10K

C4 0.1u

FC5 10

uF 1

6VC1

30.

1uF

C12

1nF

LK77

12

LK76

12

LK75

12

C1 22nF

C51

10uF

16V

R310

K

R110

K

JP7 1 2 3

DACK

11

DREQ

21

DREQ

11

DACK

21

CLKO

UT1

OTG

ENB

1 2

C30

10uF

16V

R71

10K

C98

47pF

C97

47pF

VBUS

1

ID1

OTG

MO

DE1

R12

1M

J7 USB-

CONB

1 2 3 4

R722

R

R822

R

LK20

12

LK3

12

LK21

12

LK6

12

LK5

12

LK4

12

LK10

12

LK9

12

LK8

12

LK7

12

LK13

12

LK12

12

LK11

12

LK16

12

LK15

12

LK14

12

LK1

12

C96

47pF

LK18

12

C95

47pF

LK17

12

LK2

12

R210

K

Y1 12M

Hz

R410

K

HW

UP1

1D

WU

P11

C14

22pF

C15

22pF

D[31

:16]

A[24

:1]

RD WR

BUFE

NB1

RESE

T

INT1

INT2

CS1




5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Conn

ecti

ons

to P

hili

ps C

D10

base

d player

Adap

ter

PCB

to p

rovi

de b

ackw

ard

comp

atab

ilit

y to

exi

stin

g Tr

iosy

stem

s

GND

GND

SDAT

AISC

LKLR

CKEFCF

LGSD

ASC

LRA

BSI

LDDM

_PWM

PORE

SSM

UTE

SLEE

PEB

UIN

GND

+AV

GND

2.7V

RESE

TDO

ORSW

HOLD

RESU

METE

MPBA

TT_L

VLCH

G_DE

TCH

G_ON

DC_I

NAC

CUWA

KE

116

P3

116

P2

P1

1

P1 m

ount

ed o

n th

e un

ders

ide

of t

he P

CB.

The

top

of t

he b

oard

sho

uld

be f

lush

with

P1

to a

void

fou

ling

wit

h J1

5 on

the

C3 b

oard

.

CD_D

ATA

CD_B

CKCD

_LRC

KCD

-SCL

KCD

-SEN

SCD

_DDA

TCD

_DCL

KCD

_DXL

TCD

_XRS

TCD

-SCO

RCD

-C2P

OCD

-XRO

F

GND

GND

+5V

+5V

CD-E

MPH

STOP

DOOR

SW

CD-F

OKCD

-AGC

CD-L

DON

CD-E

SPS

CD-S

QSO

CD-S

QCK

PLAY

GND

GND

+5V

SDAT

AI1

SCLK

1LR

CK1

EF/G

PIO1

9CF

LG/G

PIO1

8SC

LK4/

GPIO

50LR

CK4/

GPIO

46RT

S0/G

PO30

RTS1

/GPO

31RC

K/GP

IO51

SFSY

/GPI

O52

SUBR

/GPI

O53

PLAY

KEY

TIN0

/GPI

33TI

N1/G

PIO2

3RX

D0/G

PI27

RESE

TQS

PICS

3/GP

IO22

TXD0

/GPO

27TX

D1/G

PO28

TOUT

0/GP

O33

SDAT

AI3/

GPI4

1LR

CK3/

GPIO

45SD

ATAI

4/GP

I42

SDAT

AI1

SCLK

1LR

CK1

EF/G

PIO1

9CF

LG/G

PIO1

8SC

LK4/

GPIO

50LR

CK4/

GPIO

46RT

S0/G

PO30

RTS1

/GPO

31RC

K/GP

IO51

SFSY

/GPI

O52

SUBR

/GPI

O53

PLAY

KEY

TIN0

/GPI

33TI

N1/G

PIO2

3RX

D0/G

PI27

RESE

TQS

PICS

3/GP

IO22

TXD0

/GPO

27TX

D1/G

PO28

TOUT

0/GP

O33

SDAT

AI3/

GPI4

1LR

CK3/

GPIO

45SD

ATAI

4/GP

I42

Conn

ecti

ons

to S

ony

chip

set

bas

ed player

S1

1S1

mou

nted

on

the

unde

rsid

e of

the

PCB

.

The

top

of t

he b

oard

sho

uld

be f

lush

with

S1

to a

void

fou

ling

wit

h J1

5 on

the

C3 b

oard

.

S2

1

CD In

terfa

ce A

dapt

ers

1.2

MCF

5249

Eva

luat

ion

Boar

d - A

udio

Dau

ghte

r Car

d

B

77

Mon

day,

Oct

ober

28,

200

2

Mot

orol

a SP

S TS

PG -

32-b

it Em

bedd

ed C

ontro

ller D

ivis

ion

(TEC

D)Ti

tle

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

LK72

12

S1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

J14

12345678910111213141516

J11

12345678910111213141516

S2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

J12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NOTES



Document Number: AN2462Rev. 12/2007

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