FPGA Implementation of RBSD or

8/6/2019 FPGA Implementation of RBSD or

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Abstract

In this project a comparator is designed using Redundant Binary Signed Digit (RBSD) Number System.

Radix-2 or signed binary digit number representations are of particular interest here. The redundant

number system can be implemented by a digit set which has more digits in the set than the value of the

radix and the set consists of digits{1, 0, +1}.This allows a given number to have more than one

representation. Each digit within these digit sets with the exception of zero is present in both positive

and negative polarities. The RBSD comparator is designed by HDL and its RTL view is generated by

its FPGA implementation. Keeping in view the low power VLSI design, the gate level circuit is

implemented by CMOS and simulated. The FPGA Implementation is done on CycloneII, a product of

Altera Inc. The CMOS level design is done by the high end EDA tool ICFB.

Keywords:

Redundant Binary Signed Digit (RBSD), comparator, VERILOG,FPGA implementation, CMOS etc.

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1. Introduction

1.1 RBSD

A redundant binary representation (RBR) is a numeral system that uses more bits than needed to

represent a single binary digit so that most numbers have several representations. RBR unlike

usual binary numeral systems, including two's complement, which use a single bit for each digit. Many

of RBR's properties differ from those of regular binary representation systems. Most importantly, RBR

allows addition without using a typical carry. When compared to non-redundant representation, RBR

makes bitwise logical operation slower, but Arithmetic operation are faster when large bit width are

used. Usually, every bit has a sign that is not necessarily the same as the sign of the number

represented. When digits have signs, the RBR is also a signed-digit representation.

1.1.1 Conversion from RBR

RBR is aplace-value notation system. In RBR, digits arepairs of bits i.e. For every place, RBR uses a

pair of bits. The value represented by an RBR digit can be found using a translation table. This table

indicates the mathematical value of each possible pair of bits.

1.1.2 Translation table

Interpreted Value Digit

-1 0 0

0 0 1

0 1 0

1 1 1

Table 1.1: Translation table

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http://en.wikipedia.org/wiki/Numeral_systemhttp://en.wikipedia.org/wiki/Numerical_digithttp://en.wikipedia.org/wiki/Binary_numeral_systemhttp://en.wikipedia.org/wiki/Two's_complementhttp://en.wikipedia.org/wiki/Bitwise_operationhttp://en.wikipedia.org/wiki/Arithmetic_operation#Arithmetic_operationshttp://en.wikipedia.org/wiki/Signed-digit_representationhttp://en.wikipedia.org/wiki/Signed-digit_representationhttp://en.wikipedia.org/wiki/Positional_notationhttp://en.wikipedia.org/wiki/Numerical_digithttp://en.wikipedia.org/wiki/Numeral_systemhttp://en.wikipedia.org/wiki/Numerical_digithttp://en.wikipedia.org/wiki/Binary_numeral_systemhttp://en.wikipedia.org/wiki/Two's_complementhttp://en.wikipedia.org/wiki/Bitwise_operationhttp://en.wikipedia.org/wiki/Arithmetic_operation#Arithmetic_operationshttp://en.wikipedia.org/wiki/Signed-digit_representationhttp://en.wikipedia.org/wiki/Positional_notationhttp://en.wikipedia.org/wiki/Numerical_digit


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Also the translation table can be from any of the following. In this project the above translation table is

used for further computations. The other translation tables are given below

Table 1.2: Other Translation tables

As in conventional binary representation, the integervalue of a given representation is a weighted sum

of the values of the digits. The weight starts at 1 for the rightmost position and goes up by a factor of 2

for each next position. Usually, RBR allows negative values. There is no single sign bit that tells if a

RBR represented number is positive or negative. Most integers have several possible representations in

an RBR.

An integervalue can be converted back from RBR using the following formula, where n is the number

of digit and dk is the interpreted value of the k-th digit, where kstarts at 0 at the rightmost position:

1.2 Significance of RBSD Comparator

Data path components in modern high performance super scalar processors employ a significant

amount of associative addressing logic based on the use of comparators that dissipate energy on a

mismatch. These comparators are used to detect a full match, but as mismatches are much more

common than full matches in some components of the CPU, considerable energyinefficiencies occur

within the associative logic. The high-speed comparator is a fundamental computation element for most

digital systems, such as the state-of-the art microprocessor and DSP design. Wang et al. proposed the

use of a tree structure with all-n-transistor (ANT) dynamic CMOS logic to build a fast comparator.

Heavy pipelining is used for this design and it can achieve a very fast clock speed. For applications that

need a single cycle comparison, this design may not be suitable.

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Here a RBSD comparison algorithm is developed with the help of Karnaugh Map,

which does not need a priority encoder. The algorithm facilitates the use of nor

gate logic in the implementation and hence results in high performance when

dynamic logic is used. Todays world requires faster processor for the computation

purposes for any digital system. With the constant growth of computer

applications in every field of engineering such as signal processing,

communications and Neural Networks, fast arithmetic logic units (ALU) are

increasingly required.

The ALU of any processor perform many functions such as Addition, Subtraction,

Multiplication, Division and Logical Comparison etc. Use of non-conventional

number systems in designing comparator is gaining attention in recent yearsbecause of their facility to provide carry free addition thus enhancing the

achievable processing speed. For making the processing faster a carry free

addition technique is adopted by using Redundant Binary Number System. The

property of carry propagation chain elimination tends to make the processing

faster.

To design a RBSD arithmetic logic unit, it is necessary to design a RBSD

comparator. Advances in VLSI technology have made it possible for the designers

to integrate many complex components in a single crystal Silicon, which was not

possible earlier. Various high-speed Comparators have been proposed and

realized. Keeping in view the various factors of VLSI Technology such as Speed,

Area, Power and Cost, its required to design a high-speed processor, which meets

all the factors for the welfare of mankind.

The methodology involves an extensive study of Redundant Binary Signed

Digit Number System & the design of Comparator circuit by using this number

system with the help of HDL Based Language & its FPGA Implementation followed by

synthesis process. In this project a digital system is designed by solving various possible combinations

using Karnaugh Map and its description in verilog. The above said objective is achieved with the help

of simulation by using the Simulator QuartusII 8.1. The mask level CMOS Layout Design can also be

implemented.

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2. Tools Used

QuartusII 8.1

CycloneII FPGA

Cadence ICFB

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3. Design of RBSD Comparator

3.1 Design of RBSD Comparator

The two input vectors A (P1 P2) and B (P3 P4) are taken into consideration. The one digit

RBSD comparator is designed by Verilog in which outputs O1, O2 & O3 corresponding to the signals

Greater, Equal and less than correspondingly are treated as bit vector and inputs as a vector having

width of two. The simulation results are verified with its corresponding logic diagram

The HDL coding for the RBSD comparator is done using QuartusII 8.1. The following figure

shows the RTL view of RBSD comparator

Fig 3.1: RTL view of RBSD Comparator

The Technology schematic of the above RBSD comparator is generated using the QuartusII 8.1 tool.

The following figure represents the same.

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Fig 3.2: Technology Schematic of RBSD Comparator

3.2 Results observed on QuartusII 8.1

3.2.1 When both the inputs are equal

Fig 3.3: Output of RBSD Comparator When the inputs are equal

3.2.2 When the first input is less than second

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Fig 3.4: Output of RBSD Comparator When the first input is less than second

3.2.3 When the first input is greater than second

Fig 3.5: Output of RBSD Comparator When the first input is greater than second

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4 Implementation of RBSD Comparator

4.1 Introduction to FPGA

An FPGA is a Field Programmable Gate Array which is a type of programmable integrated circuit

known as a Programmable Logic Controller (PLC). It is very much similar to a microcontroller where it

can be used to perform desired actions, on digital data or signals.

The FPGA differs from a microcontroller however because it is basically a massive array of the basic

logic functions (AND, OR, NOT) connected together into an array with programmable fuses. The

board can be programmed for the desired functionality. Each of the AND, OR & NOT functions can

then be combined into whats known as logic blocks, and these can be combined into flip-flops and

other combinational digital logic functions. These can then also be combined into memory registers to

store data and state machines, which can perform actions one by one like a microcontroller.

The key operational difference between a microcontroller and a FPGA is that a microcontroller

executes one program line by line, whereas a FPGA can perform thousands of complex mathematical

tasks at the same time as long as there are enough logic blocks available.

The RBSD Comparatorthat is designed in QuartusII 8.1 using Verilog is implemented on a CycloneII

FPGA

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4.2 Features of CycloneII

Up to 1.1 Mbits of RAM

4,096 memory bits per block

Variable port configurations

True dual-port operations(one read and one write, two reads, or two writes)

Up to 260-MHz operation

Up to 150 (1818-bit) multipliers

Up to four PLLs per device provide clock multiplication and division, phase shifting and

programmable duty cycle

Up to 16 global clock lines

Supports multiple configuration modes: active serial, passive serial, and JTAG-based

configuration

4.3 Block Diagram of CycloneII

Fig 4.1 Block Diagram of CycloneII EP2C20

4.4 Results on CycloneII FPGA

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Fig 4.2: Result on the FPGA when the inputs are equal


Fig 4.3: Result on the FPGA when the first input is less than second


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Fig 4.4 Result on the FPGA when the first input is greater than second

4.5 CMOS level design of RBSD Comparator

The CMOS level design of RBSD comparator is done using Cadence ICFB tool. The following figure

shows the gate level representation of the RBSD Comparator designed in Cadence ICFB.

Fig 4.5: CMOS Gate Level Schematic of RBSD Comparator

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4.6 Results Observed on Cadence ICFB


Fig 4.6: Output of Comparator When the inputs are equal


Fig 4.7 Output of Comparator When the first input is less than second


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Fig 4.8 Output of Comparator When the first input is less than second

5. Conclusion

The RBSD Comparator is designed using verilog. The functionality of the comparator is verified and

the RBSD comparator is implemented on the CycloneII FPGA. The performance of the RBSD

comparator and conventional comparator are compared. It is observed that the total delay of RBSD

comparator is 6.233ns (5.117ns logic, 1.116ns route) (82.1% logic, 17.9% route) and that of the

conventional comparator is 6.077ns (5.117ns logic, 0.960ns route) (84.2% logic, 15.8% route). From

these results it is observed that the logic delay of the RBSD comparator is same as the conventional

comparator inspiteof the large number of gates present in it as against the conventional comparator.

Also from [2] the total delay of RBSD comparator remains the same irrespective of the bit width, which

is not the case in conventional comparator. Hence at higher bit widths RBSD comparator has an upper

hand over conventional comparator. In practice where ALU operates at higher bit widths use of RBSD

comparator reduces the overall delay of ALU and processor thereby improving the performance of the

processor as a whole.

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Future Scope

RBSD comparator can be extended to higher bit widths.

The mask level layout design can be done by the high end EDA tool i.e. Cadence Virtuso LayoutEditor

References

[1] FPGA Implementation and Mask Level CMOS Layout Design of Redundant Binary Signed Digit

ComparatorIJCSNS International Journal of Computer Science and Network Security, VOL.9 No.9,

September 2009

[2] http://www.louif.com/rbin/

[3] Logical Design of a redundant binary adder Catherine Y. Chow, James E. Robertson

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FPGA Implementation of RBSD or