Follow-up meeting of the Administrative Agreement between FCT and CERN Vicente Leitão, Pedro (PH/ESE-ME, joined in May 2013) Supervisor: Moreira, Paulo

Follow-up meeting of the Administrative Agreement between FCT and CERN

Vicente Leitão, Pedro(PH/ESE-ME, joined in May 2013)

Supervisor: Moreira, Paulo

November 5, 2014

Outline

• Radiation Hard Optical Link Project

• GBT Project Framework

• GBTX ASIC Project

• eCDR-PLL ASIC Project

• Further Work

http://cern.ch/proj-gbt [email protected]

Radiation Hard Optical Link Project

• Radiation Hard Optical Link Project– Aims to develop a radiation hard bi-directional optical link between on-

detector and off-detector electronics– Can serve simultaneously applications such as data acquisition, timing,

trigger and experimental control– It is divided in two parts: GBT chipset (radiation hard ASICs) and

Versatile link optoelectonics components


On-DetectorCustom Electronics & Packaging

Radiation Hard

Off-DetectorCommercial Off-The-Shelf (COTS)

Custom Protocol

GBTX


Radiation Hard


Custom Protocol

GBTX

GBT Project Framework

• GBT Project Framework– Stands for “Giga Bit Transceiver” (4.8 Gb/s bidirectional high-speed link)– GBT radiation-hard Chipset:

• GBTX ASIC• GBLD (gigabit laser driver) ASIC• GBTIA (gigabit trans-impedance amplifier) ASIC• SCA (slow control adapter) ASIC• eCDR-PLL (Clock-and-Data-Recovery and Phase-Locked-Loop) ASIC



Radiation Hard


Custom Protocol

GBTX


Radiation Hard


Custom Protocol

GBTX

GBTX ASIC Project

• GBTX ASIC Overview (in numbers)– High-speed data rate: 4.8 Gb/s– Design in 130 nm CMOS technology using radiation-hard techniques– ½ million gates– Custom flip-chip BGA 20x20 pin package = 200 pins– Onboard crystal– > 350x 8-bit configuration registers (All triplicated)

• Can be programmed through I2C• Or through high-speed serial link

– Up to 40 bidirectional e-links• Differential lines

– Data input, data output and clock output– Can work at 40/80/160/320 MHz and 80/160/320 Mb/s

– 7 PLLs, 17 master DLL, 56 replica delay lines, 7 power domains, …– First prototypes arrived in June 2013


GBTX ASIC Project

• GBTX ASIC Project summary (my work)– Preliminary functional tests using the IC tester– Functional validation and performance characterization using the Stand-

Alone Test (SAT) board– Radiation tests campaigns using the SAT board

• Total Ionizing Dose, at CERN, Dec. 2013• Single Event Upsets, in Louvain-la-Nueve, Belgium, Feb. 2014

– Current:• Production testing• User support• GBTX ASIC user application support

– Results presented at TWEPP’14• Test Bench Development for the Radiation Hard GBTX ASIC

– In the Topical workshop on electronics for particle physics, Aix-en-Provence, FR, Sept (2014)


GBTX ASIC Project

• Preliminary functional tests using the IC tester– Performed with an industrial IC tester at CERN

• CREDENCE Sapphire


VHDL/Verilog representation of the

ASIC

Create/load the test vectors onto the IC

tester

Test vectors generated from the simulations

Perform the testValidade the

ASIC performance

GBTX ASIC Project

• Functional validation and performance characterization using the Stand-Alone Test (SAT) board


40x e-link in

40x

e-lin

k ou

t

TX RX

FE emulation FE

em

ulati

on

GBTX

TXRX

BERT BERT

LOGGER

Opti

cal l

inkse-links bus e-

links

bus

GBTX ASIC Project

• Functional validation and performance characterization using the Stand-Alone Test (SAT) board


40x e-link in

40x

e-lin

k ou

t

TX RX

FE emulation FE

em

ulati

onGBTX

TXRX

BERT BERT

LOGGER

Opti

cal l

inkse-links bus e-

links

bus

Unlocked(counter = 0)

Locked(counter = threshold)

Locking(counter < threshold)

counter++

Unlocking(counter < threshold)

counter--

No errors;counter > 0counter = 0

No errors;counter = thresholdfound errors

No errors

found errors

• The total number of received frames, number of frame errors and bit errors;• An histogram of the number of times a certain bit of the received frame was wrong;• “SnapeShot” capability, logging up to 256 wrong frames, enabling to understand if

a burst of errors occurred and where the errors are located inside the frame; • Monitoring of internal GBTX registers;• Power consumption monitoring;• etc

GBTX ASIC Project

• Single Event Upsets, in Louvain-la-Neuve, Belgium, Feb. 2014


22Ne 7+ at θ = 0°, 30°, 45° and 60°40Ar 12+ at θ = 0°, 30°, 45° and 60°58Ni 18+ at θ = 0°, 30° and 45° 83Kr 25+ at θ = 0°

00:00 22:30 45:00

10-10

10-8

Fra

me

Err

or

Ra

te

Time (min:sec)00:00 22:30 45:000

100

200

300

28-b

it co

un

ter

Time (min:sec)

SEU register

FEC-RX

0 20 40 60 80 100 1200

2

4

6

8

10

Nr

of o

ccu

ren

cie

s

Nr of errors per frame

GBTX ASIC Project

• Total Ionizing Dose, at CERN, Dec. 2013• X-rays up to 100 Mrad at 100 krad/s


post-rad transmitter eyeTJ = 85.28 ps (+7.7% pre-rad)

RJ(rms,narrow) = 2.65 ps (-4.9 % pre-rad)

pre-rad transmitter eye

GBTX ASIC Project (current stage)

• User Support– Creation and management of two CERN e-groups

– GBTX-news to broadcast all important updates relative to the project– GBTX-support to serve as a feedback channel from users to developers

– Provide technical support

• Production testing• Part of the development of the new SAT board which will enable

production testing– Automated testing of all working modes– Automated GBTX ASIC characterization– Expected ~1k GBTX to test early 2015– End of full production expected in Q4 2015 (expected > 50k for production testing)

[email protected] 12http://cern.ch/proj-gbt

eCDR-PLL ASIC Project

• eCDR-PLL ASIC overview– Based on the eCDR IP block (F. Tavernier, 2013) using 130 nm techn.– Two operation modes:

• CDR (clock and data recovery circuit)• PLL (clock multiplying PLL)

– My work:• Development of digital blocks: Control block, I2C slave, frequency divider, phase-shifter,

lock monitoring, …


Control Block

I2C slave

MEMORY BLOCK

Phase Shifter

40MHz

60/80MHz

120/160MHz

240/360MHz

dataOut

VCO240/320

MHz

WienBridge

CP 1

CP 2

FD

Frequency Divider

clkIn

dataIn

PD

PFD

retimedData

I

Q

40MHz60/80MHz120/160MHz

Control Signals

Status Signals

SCL

SDA

eCDR-PLL core

eCDR-PLL ASIC Project

• eCDR-PLL ASIC overview– Based on the eCDR IP block (F. Tavernier, 2013) using 130 nm techn.– Two operation modes:

• CDR (clock and data recovery circuit)• PLL (clock multiplying PLL)

– My work:• Development of digital blocks: Control block, I2C slave, frequency divider, phase-shifter,

lock monitoring, …


Control Block

I2C slave

MEMORY BLOCK

Phase Shifter

40MHz

60/80MHz

120/160MHz

240/360MHz

dataOut

VCO240/320

MHz

WienBridge

CP 1

CP 2

FD

Frequency Divider

clkIn

dataIn

PD

PFD

retimedData

I

Q

40MHz60/80MHz120/160MHz

Control Signals

Status Signals

SCL

SDA

eCDR-PLL core

ASIC presented at TWEPP’14The eCDR-PLL IC, a Radiation-Tolerant ASIC for Clock and Data Recovery and Deterministic Phase Clock Synthesis

In the Topical workshop on electronics for particle physics, Aix-en-Provence, FR, Sept (2014)

Further work

• Finish the eCDR-PLL ASIC– Prototype fabrication expected in Q1 2015

• Continue with the GBTX project• Finish the development of the production tests• Test all GBTXs during the production stage

• Upcoming project: Low-power GBTX (LpGBTX)• “Replica” of the GBTX but using 65 nm CMOS technology• Low-power mode

– 4.8 Gb/s bidirectional high-speed link– e-links @ 80, 160 and 320 Mb/s (uplink)

• High-speed mode– 9.6 Gb/s for the uplink, 4.8 Gb/s for the downlink– e-links @ 160, 320 and 640 Mb/s (uplink)


Further work

• Finish the eCDR-PLL ASIC– Prototype fabrication expected in Q1 2015

• Continue with the GBTX project• Finish the development of the production tests• Test all GBTXs during the production stage

• Upcoming project: Low-power GBTX (LpGBTX)• “Replica” of the GBTX but using 65 nm CMOS technology• Low-power mode

– 4.8 Gb/s bidirectional high-speed link– e-links @ 80, 160 and 320 Mb/s (uplink)

• High-speed mode– 9.6 Gb/s for the uplink, 4.8 Gb/s for the downlink– e-links @ 160, 320 and 640 Mb/s (uplink)


Thank you for your time and attention!

Documents

Follow-up meeting of the Administrative Agreement between FCT and CERN Vicente Leitão, Pedro (PH/ESE-ME, joined in May 2013) Supervisor: Moreira, Paulo