FLASH MEMORY RELIABILITY - Intranet DEIBhome.deib.polimi.it/spinelli/corsi/nano/flash.pdf · † Introduction to Flash Memory † Intrinsic cell reliability: – Cycling Endurance

FLASH MEMORY RELIABILITYCorso di Laurea in Ingegneria ElettronicaPolitecnico di Milano, 10 Dicembre 2009

Angelo ViscontiNumonyx

R2-Technology CenterNon Volatile Memory Technology Development

Agrate Brianza (MB), Italy

Page 2 Copyright © 2008 Numonyx B.V.

Outline

• Flash memory market and applications• Introduction to Flash Memory• Intrinsic cell reliability:

– Cycling Endurance– Data retention

• Single-bit failures:– Process defects– Over-erasure and erratic cells– Data retention after cycling

• Summary• References


Outline






Memory Regaining Momentum??Memory Percent of Total IC Market

0

50

100

150

200

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

B$

0%

5%

10%

15%

20%

25%

30%

MOS Memory Non-Memory IC Memory % of Total IC

DRAM Dominates, Flash Gains

0

10

20

30

40

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008

B$

DRAM SRAM Flash Other Memory

Source: WSTS, IC Insights

• Memories going to climb back to 30% of IC Market– DRAM $ growth 17%– FLASH $ growth 23%

~30B$ in 2008!

And what about 2009?The black Swan…


NOR / NAND Flash Vendors

2007


Flash Applications

Code Only

Code +Parameter

Code + Data

Data

HDD, Add-on boards,CD-ROM

Printer, DVD, PDAOA, Games, TV

Modem

PC Automotive

Industrial

Mobile

DVD

STB

Networking

CAMERAS MP3

Function Application

NOR

NAND

Current mass productionNOR: 1Gb, 65nm tech. NAND: 32Gb, 32nm tech

USB SSD

eMMCSD/uSD


Outline






OUTPUTSIGNALS

INPUTBUFFERS

X ADDRESSSIGNALS

Y ADDRESSSIGNALS

OUTPUTBUFFERS

SENSEAMPLIFIERS

COLUMNSELECTORS

MEMORYCELL

ARRAY

ROWDECODERS

COLUMNDECODERS

INPUTBUFFERS

Flash memory device

Cell Array: designed attechnology limits (high density)

Control circuits: a bit relaxedwith respect to the same logicgeneration (Flash process, notlogic process!)

Flash memory device:Cell Array+controls

Flash Memory datasheet:>100k Program/Erase>10Y data retention


CHIP OVERVIEW, NOR 130nm technology

Chip size 36mm2

Array efficiency >60-70%

Flash cell

memoryArray

Control circuits


Stacked Gate Flash Cell

Floating Gate

Control Gate

x-pitch

DrainSource

Control GateInterpoly

DrainSource

Control Gate

DrainSource

Floating Gate

Control Gatedielectric

Tunneloxide

CHARGESTORAGEELEMENT

130nm Technology Node

y-pitch

G

FG

DS

0.32um

0.50um

DS S


ID – VG Characteristics of the Cell

ΔVT = – QFG/CPP

VFG = αG(VG – ΔVT) + αDVD + ...

αG = CPP/(CPP + CD + ...)iFG = CPP dVT/dtdrainsubstrate

floating gate

control gate

CPP

source

CS CB CDCP

Dra

in C

urre

nt

Gate Voltage

“1” “0”

IREF

VT,P

VT,E

• The cell VT depends linearly on the total charge in the floating gate

Cell static equivalent circuit

CP represents the lateral coupling with other FGs

∗ We will use the empirical VT definition:VT = VG for a given ID

G

FG

DS

Typ. Vd=1V


Array Architectures

NOR NAND

Source

Bit line

Word line

Bit line

Word line

Source sel.Source

Bit line sel.

�Sector size: 64-128 KB �Sector size: 64-1024 KB


CHIP OVERVIEW, NOR/NAND Technology

512Mb, 65nm, 1.8V, 2b/c 16Gb, 48nm, 3.0V, 2b/c

NOR NAND


Program/Erase Conditions

NOR NAND

�Fowler-Nordheim erase

CONTROL GATE

DRAINSOURCE

−8 V

8 V

CONTROL GATE

DRAINSOURCE

−8 V

8 V

�Fowler-Nordheim erase

CONTROL GATE

DRAINSOURCE

20 V

GND

CONTROL GATE

DRAINSOURCE

20 V

GND

CONTROL GATE

DRAINSOURCE

8 V

4.5 VGND

GND

CONTROL GATE

DRAINSOURCE

8 V

4.5 VGND

GND

�Channel Hot Electron program

CONTROL GATE

DRAINSOURCE

19 V

GND

GND

GNDCONTROL GATE

DRAINSOURCE

19 V

GND

GND

GND

�Fowler-Nordheim program

�Program: ~0.2ms at page level (0.5-8 KB)�Erase: ~2ms at sector level (1-8Mb)

�Program: ~5μs at word level (1-8 B)�Erase: ~200ms at sector level (1-2Mb)


Impact of Architecture on Reliability

• Focusing on reliability, the most important difference between NAND and NOR is the tunnel oxide thickness:– to achieve fast program/erase times NAND has thinner

tunnel oxide (typically 8nm versus 10nm for NOR)• A less important role is played by the differences in

programming mechanisms and VT distributions• From here follows, NOR Flash are considered, unless

otherwise stated.


Reading Operation,Distributions and Working Range

�NOR Flash�Read current: I=10uA�Random access: t=70-100ns"1" "0"

Vcg

Id

ΔVt = - Q / Cpp

Vread

"1" => Iread > 0"0" => Iread = 0

PVRDV

EV

Voltage

BitDistribution

“1” “0”Working range: Vt > 1.5V

Vt shift 1-0: ΔVt>3V

VG

VFG

VD

VB

VS

Cpp, CG

CS CDCB

Vg=4.5VVd=1.0V

Flash cellEq. Capacitive model


Intrinsic vs Single-Bit Failure Modes• We call intrinsic those failure mechanisms affecting all the cell in a uniform way:

– They can be studied on single cells in test structures.– Related to materials properties

• Single-bit failure mechanisms affect few cells of a large sample set (e.g. several 100Mb):– They require a real device or a test chip for investigations– Can be related either to extrinsic defects (e.g. particles) or to specific configurations of intrinsic

point defects of materials.

Example: retention test results

4 5 6 71E-3

0.115

204060809599

99.9

99.999

t=0 7=2.1x104 hr

Per

cent

of c

ells

Threshold Voltage (V)

Single-bit tail

dOX=8nm T=25oC

5 6 7 81E-3

0.115

204060809599

99.9

99.999

t=0 t=500h

Per

cent

of c

ells


Intrinsic shift

dOX=8.5nm T=250oC


Outline






Negative Charge Trapping on Flash

During F-N erase (and F-N program in NAND):• Generation of oxide traps by high-field conduction• Generation of interface states at Si/SiO2 interface• The generation rate is field dependent• Electrons captured by traps into the oxide

• QT α (Number of cycles)1/2Floating gate

Tunnel oxide

Si substrate

QT

electrontrap

−

−

−

−

−

Typ. Erase Electric field:10MV/cm (1GV/m!)

Fowler-Nordheim erase

CONTROL GATE

DRAINSOURCE

−8 V

8 V

CONTROL GATE

DRAINSOURCE

−8 V

8 V


Cycling-Induced Cell Gain Degradation

• Degradation is due to interface states generated in the channel• Transconductance degradation causes a VT increase• Sub-threshold slope degradation causes bit-line leakage after erase (the leakage of

all the cells in a bit line is summed)

10-12

10-11

10-10

10-9

10-8

10-7

10-6

cycles 1 10k 100kI D

(A)

Gate Voltage0

10

20

30

40

50

60

ID (μA)


Floating gate

Drain

Floating gate

DrainSource1 10 100 1,000 10,000 100,000

1

2

3

4

5

6

7

8

Programmed VT Erased VT

VT(

V)

Cycles

Flash Cell Endurance

• Interface states generation and charge trapping in the oxide occurs along the whole channel during Program/Erase

• The window closure is the result of three contributions :– Variation of the transistor VT, measured at the floating gate– Oxide conduction variation– Transconductance degradation, leading to higher VG for the same ID

• Optimized cell design & operation are necessary to prevent Program/Erase window closure

BadP/E window Good

P/E window

“0”

“1”


Program/Erase Time Degradation

• Write algorithms prevent VT window closing, but P/E times increase• Beyond 1 Mcycle oxide breakdown may occur

100 101 102 103 104 105 1060.0

0.5

1.0 Program time Erase time

Tim

e (s

)

Number of Cycles

10-6 10-4 10-2 1Qinj (C/cm )2


Outline






Data retention: basic data

Flash Cell, 65nm Tech.X=0.05um Tox= 9.8nmY=0.14um TONO= 14.5nmCpp = 0.08 fF = 80 aF

Q(0)= Cpp ΔVt =- 80aF 4V = - 320aC = ~2000 e-

(1e-�2mV)

Let's suppose that a memory cell losts its data if the threshold falls by 1V

Qleak= - 80 aC = ~500 e-

The memory cell has to guarantee 10 years of data retention, then:

Max I leak ~ 10-25 A ~ 1 e-/week


stato programmatostato cancellato

Struttura a bande della cella


Data Retention on Fresh Status

• Intrinsic data retention for fresh devices can be well beyond 10 years• Most of the failure mechanisms are thermally activated• Process qualification includes 250oC retention bake for few weeks

5.5 6.0 6.5 7.0 7.5 8.01E-3

0.115

204060809599

99.9

99.999

Per

cent

age

of c

ells

VT (V)

Prog 27/5/1996 Bake 511hr @ 250oC Read 19/12/2003 (25oC storage)

dOX=11nm

⎟⎠⎞

⎜⎝⎛−∝

kTEI a

leakage exp

20 22 24 26 28 30 32 3410-1

100

101

102

103

104

105

170°C

200°C

220°C

250°C

125°C

10 Y

t @ Δ

Vt=

0.25

V (h

r)

1/kBT (1/eV)

Arrhenius plot


Data Retention after cycling:Charge Detrapping

Thermal emission

QOUT

electrontrap

−

Si substrate

Floatinggate Tunnel oxide

−

−

− −

−−

Tunnel

• Thermal emission or tunneling (for traps close to the interface)

• High thermal activation (Ea = 1.1-1.3 eV)• Logarithmic in time• Slightly electric field dependent• Accumulated charge dependent• QOUT = f(T, log t, VT, Number of cycles)


Tech. node


• After P/E cycling, a finite amount of negative charge is accumulated (QACC)in tunnel oxide depending on– Number of P/E cycles– Average time between P/E cycles– Operating Temperature

• During bake treatment performed after cycling, QACC is released based on 1.1-1.3 eV activation energy mechanism

• Released charge originates a finite negative ΔVT

• ΔVT is not related to electronic charge loss from floating gate

High Temperature Retention after Cycling

QACC = QT(number of cycles) - QOUT(T, log t, VT, number of cycles)


Implications to Reliability Evaluation

Typical laboratory trial

QACC= QT - QOUT(T, log t, VT, cycles)

Fast 10-100k P/E cycle at 25°C

HT Retention Test

Cycle

recovery

Cycle

recovery

Cycle

Storage

Cycle

rec.Real-use cycling

QACC= QT - QOUT(T, log t, VT, cycles) < QT• A significant charge detrapping will occur in the time period during which the device is

cycled, especially if the device is operated at high temperature.


Emulation of Real-Use Cycling

25k (cycle and wait) at different temperatures:

25°C

79°C (10s = 40min @ 25°C)

110°C (10s = 40min @ 55°C)

cycle25k

timeswait 10s

Less QACC in real-use conditions

20 40 60 80 100 1200.0

0.2

0.4

0.6

0.8

1.0

Rel

ativ

eΔV

T afte

r bak

e

Cycling Temperature (oC)

ΔVT after high-temperature storage normalized to RT, no wait-time case

• Cycling at high temperature can emulate real-use conditions, assuming that trapping is not dependent on temperature

2YearEquivalentCyclingdistribution


Outline






Early failures - Single-Bit Failures

• the impact of extrinsic defects have been dramatically reduced through the improvements ofprocess technology and screening effectiveness (electrical stresses, retention bakes)

After more than 15 years of high volume manufacturing and continuous learning:

Extrinsic, process-related defects may affect reliability, but ...


Extrinsic phenomena - defects• Impacting customer field application (Muroke – IRPS 2006)


Charge sharing – example of Physical defect

Note: single bit due to P1-P1 soft short. ECC able to correct. Screening possible by dedicated pattern able to activate single bit between wafer level test and assy


Evidence of physical defect

Note: single bit failure, covered by media management (ECC). See Mielke IRPS 2006


Root cause: metal interruption

• “Soft” metal interruption justified temperature sensitivity

• Hot temperature test step known to be worst case for several failure modes (parametric: Iccsdby,leakages, …)

• Note: Room temperature check to be always present in a “Golden” testflow


Outline






VT Distribution after FN Erase

• More than 99% of the cells are normally distributed …• … but there are cells erasing much faster than normal.

1 Mbit array

Gaussian fit


Over-Erasing

• Fast-erasing cells can cause bit-line leakage• Fast-erasing cells can be screened at EWS level

DV

EV Voltage

BitDistribution

“1” “0”

VT

0 log t

erase verify VT

typical cell

fast-erasing cell

slowest cell

t E


Erratic Erase

• Fast-erasing cells sometimes show an erratic behavior and they may appear only after several p/e cycles

• The cause of the erratic behavior is trapping/detrapping of positive charges in the oxide

0 1000 2000 3000 4000 5000 60000

0,5

1

1,5

2

2,5

3

0

0,5

1

1,5

2

2,5

3

Number of Cycles

Eras

ed V

t (V)

Population

Floating gate

Source


Over-erased Bits Recovery

• After erase, an algorithm is run that detects and re-programs the over-erased bits into the bulk of the distribution

1E-41E-3

0.1

15

20406080

9599

99.9

99.999 after erase after recovery

Per

cent

of c

ells

VT (V) EV

DV0V


Outline






Effect of Cycling on Data RetentionData retention tests at room temperature

Tunnel oxide thickness = 8 nm

3 4 5 6 7

1E-3

0.115

204060809599

99.9

99.999

UV t=0 90 hr 600 hr 2.4 yr 7.0 yr

Per

cent

age

of c

ells

VT (V)

3 4 5 6 7

1E-3

0.115

204060809599

99.9

99.999

t=0 740 hr 2000 hr 2.4 yr 7.0 yr

Per

cent

age

of c

ells

VT (V)

10 cycles 105 cycles

SILC: stress induced leakage currentTyp. SILC currents: 10-18-10-21A

SILC strongly depends on number of P/E cycle


Tunnel oxide thickness dependence

3 4 5 6 7 8 90.001

0.115

204060809599

99.9

99.999

dOX=7nm

t=0 t=3h t=48h t=430h t=3800h

Per

cent

of c

ells

Threshold Voltage (V)7.5 8.0 8.5 9.0 9.5

0.001

0.115

204060809599

99.9

99.999

dOX=9.5nm

t=0 t=48h t=456h t=1968h t=4056h

Per

cent

of c

ells

VT (V)

� VT distributions for two samples from the same lot, but different dox

10k cycles – RT retention

SILC strongly depends on tunnel oxide thickness


Tunnel oxide electric field dependence

10k cycles – RT retention

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.51E-41E-3

0.1

15

20406080

9599

99.9

99.999

Perc

ent o

f cel

ls

VT (V)

The long-time trend is independent of VT(0).

SILC strongly depends on tunnel oxide electric field (i.e. cell Vt)

Different Vt(0)Same tail

Tox 7nmt=3Y


Temperature Dependence

Storage experimentsdox= 8.5 nm - 100k P/E cycles

� No tail is observed athigh temperature

5 6 7 80.001

0.115

204060809599

99.9

99.999T=25oC

t=0 t=500h

T=250oC t=0 t=500h

Per

cent

of c

ells


Intrinsic shift

The high temperature anneals the defects responsible for SILC


Statistical Nature of Tail Cells

1E-41E-3

0.1

1

5

20406080

95

99

99.9

99.999 3Y of LTB retention

dox

7nm - 10k cycle

Perc

ent o

f cel

ls

VT(V)

Tail cells map

VT distribution

• Tail cells have a random spatial distribution


-4 -5 -6 -7 -8 -9 -1010-22

10-21

10-20

10-19

10-18

10-17

10-16

10-15

10-14

10-13

VFG

(V)I FG

(A)

Typical

Fast erasing

SILC

10-5 10-4 10-3 10-2 10-1 100 101 102 103 104 105 1061

2

3

4

5

6

7

8

9

V T (V

)

Time (s)

TypicalFast erasing

SILCNeg. gate stress

I-V Characteristics

• Fast-erasing cells do not have SILC-type I-V characteristic• SILC often shows an erratic behavior, similar to that of fast-erasing cells

SILC

VFG = αG(VG – ΔVT)iFG = CPP dVT/dt


Physical Model: TAT

Trap-assisted tunneling (TAT, 1 defect/cell) accounts for “normal” SILC

1 2 3 4 5 6FG Voltage [V]

10-12

10-11

10-10

10-9

10-8

10-7

10-6

J[A

cm-2

]

Bit#1Bit#2

J1

J2


Physical Model: 2TAT

TAT cannot account for anomalous SILC ⇒ tunneling assisted by 2 traps

1 2 3 4 5 6FG Voltage [V]

10-12

10-11

10-10

10-9

10-8

10-7

10-6

J[A

cm-2

]

Bit#1Bit#2

J1J12

J2


Statistical Model

• Calculate the probability of defect clustering• Calculate the SILC due to the defect clusters (Jn, n=1, 2, 3, ...)

TAT TAT2TATDefect configurationdetermines theSILC distribution


SILC Distribution

• Consistency between calculated defect density for different dOX

10-18

10-16

10-14

10-12

10-10

10-8

10-6

10-4

10-2

J [A cm -2 ]

0.510-110-210-310-410-6

10-910-12

1 -F

MeasuredCalculated

tox=6.5nm

1014

1015

1016

1017

1018

-410

-210

-1810

-1610

-1410

-1210

-1010

-810

-610

J [A cm -2 ]

0.510 -110-210-310-410-6

10-910-12

1-F

MeasuredCalculated

tox=8.8nm

1014

1015

1016

1017 10

18

• The typical reliability risk assessment needs extrapolation to 1dpm=> Modeling of cell fail probability down to 1E-18!


Design Solutions

Example: 128Mb - 8 ECC cells every 128correction power: 1 failure every 128 cells

• Reduction of programming window to reduce field in storage– Requires improved sensing

accuracy• Error Correction Code

– Array overhead– Program flexibility

1

10

100

1000

10000

100000

1000000

1E-12 1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 1E-04

Cell failure probability

Chi

p fa

ilure

pro

babi

lity

(ppm

)

w/o ECCwith ECC

10–12 10–11 10–10 10–9 10–8 10–7 10–6 10–5 10–4

5 decadi


Outline






Summary

• Intrinsic reliability of Flash memory:– Endurance limit 105 - 106 cycles– No major issues for retention (> 10 years)– Important role is played by relaxation phenomena

• Over-erasing problem solved by design:– Over-erase verify and reprogramming

• Major issue is single-bit charge loss after cycling:– Tunnel oxide thickness > 9 nm for NOR– ECC for NAND, because of thinner tunnel oxide– Process solutions to decrease the oxide defect density– Design solutions to reduce the electric field in storage



Contact

Angelo ViscontiNVM Multilevel and Reliability - Principal Engineer

NumonyxR2-Technology Center

Non Volatile Memory Technology DevelopmentAgrate Brianza (MB), Italy

[email protected]


Outline






References (1)General and intrinsic reliability•P. Cappelletti and A. Modelli, “Flash Memory Reliability,” in Flash Memories edited by P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Kluwer 1999, pp 399-441.•R. Shiner, J. Caywood, and B. Euzent, “Data retention in EPROMs,” IRPS 1980, p. 238.•N. Mielke, “New EPROM data-loss mechanisms,” IRPS 1983, pp. 106-113.•S. Yamada et al, “Degradation mechanism of Flash EEPROM programming after program/erase cycles,”IEDM 1993, pp. 23-26.•R. Yamada, Y. Mori, Y. Okuyama, J. Yugami, T. Nishimoto, and H. Kume, “Analysis of detrap currentdue to oxide traps to improve flash memory retention,” IRPS 2000, pp. 200-204.•G. Ghidini , G.A. Sebastiani, and D. Brazzelli, “Stress induced leakage current and bulk oxide trapping: Temperature evolution,” IRPS 2002, pp. 415-416.•N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Q. Meng, N. Righos, and J. Wu, “FlashEEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling,” IEEE Trans. Dev. and Mat. Reliability Vol 4 No 3, Sep 2004 pp. 335-344.•P. Cappelletti, R. Bez, A. Modelli, and A. Visconti, “What we have learned on Flash Memory Reliability in the Last Ten Years,” IEDM 2004, pp. 489-492.


References (2)Fast erase, erratic bits•J.M.Z. Tseng, “Observation of Fast Erase Due to Enhanced Generation of Holes Caused by Electron Impact Ionization,” IEEE-EDL vol. 23, Aug 2002, pp 491-493.•A. Chimenton and P. Olivo, “Flash Memory Reliability: an improvement against the Erratic Erasephenomena using the Constant Charge Erasing Scheme,” SSDM 2002, pp 156-157.•A. Chimenton and P. Olivo, “Erratic erase in flash memories—Part II: Dependence on operating conditions,” IEEE Trans. Electron Devices, vol. 91, Apr. 2003, pp. 1015-1021.

Experimental characterization and modelling of the anomalous leakage after cycling:•S. Yamada et al. “Non-uniform Current Flow through Thin Oxide after Fowler-Nordheim CurrentStress,” IRPS 1996, pp.108-112.•F. Arai et al. “Extended data retention process technology for highly reliable flash EEPROMs of 106 to107 W/E cycles,” IRPS 1998, pp. 378-382.•Y. Manabe et al. ”Detailed observation of small leak currents in flash memories with thin tunnel oxide,”ICMTS 1998, pp. 95-99.•H. Kameyama et al., “A new data retention mechanism after endurance stress on Flash memory,” IRPS2000, pp. 194-199.•F. Schuler et al. “Long time estimate of failures rates due to low temperature charge loss,” NVSMW2000, pp. 102-105.


References (3)•G. Tempel et al. “Abnormal charge loss of Flash cells at medium temperatures,” NVSMW 2000, p. 105.•G. Tao et al. “Data retention prediction for modern floating gate non-volatile memories,”Microelectronics Reliability, vol. 40, 2000, pp. 1561-1566.•A. Modelli, et al. “A new conduction mechanism for the anomalous cells in thin oxides Flash EEPROMs”, IRPS 2001, pp. 61-66.•P.J. Kuhn et al. “A reliability methodology for low temperature data retention in floating gate non-volatile memories,” IRPS 2001, pp. 266-270.•G. Tempel et al. “Observation of a general Log2 dependency of the faiulure rate of anomalous low temperature leaky bits,” in NVSMW 2001, pp. 117-119.•H. Belgal, N. Righos, I. Kalastirsky, J. Peterson, R.Shiner, N. Mielke, “A New Reliability Model for Post-Cycling Charge Retention of Flash Memories,” IRPS 2002, pp. 7-20.•F. Schuler, R. Degraeve, P. Hendrickikx, D. Wellekins, "Physical description of anomalous charge loss in floating gate based NVM's and identification of its dominant parameter," IRPS 2002, pp 26-33.•M. Suhail, T. Harp, J. Bridwell, P.J. Kuhn, "Effects of Fowler Nordheim Tunneling Stress vs. Channel Hot Electron Stress on Data Retention Characteristics of Floating Gate Non-Volatile Memories," IRPS2002, pp. 439-440.•A. Hoefler, J.M. Higman, T. Harp, and P.J. Kuhn, "Statistical Modeling of the Program/Erase Cycling Acceleration of Low Temperature Data Retention in Floating Gate Nonvolatile Memories," IRPS 2002,pp 21-25.


•G. Tao, A. Scarpa, H. Valk, L. van Marwijk, K. van Dijk, F. Kuper, "Fast wafer level monitoring of stress induced leakage current in deep sub-micron embedded nonvolatile memory processes," Proc.Integrated Reliability Workshop, pPRR-3.1.•T. Wang, Nian-Kai Zous, Chih-Chieh Yeh, "Role of Positive Trapped Charge in Stress-InducedLeakage Current for Flash EEPROM Devices," IEEE Trans. El. Dev., Vol. 49, No. 11, Nov 2002, pp. 1910-1916.•D. Ielmini, A.S. Spinelli, A.L. Lacaita and A. Modelli, "A Statistical Model for SILC in Flash Memories," IEEE Trans. El. Dev., Vol 49, No 11, Nov 2002, pp 1955-1961.•A. Chimenton, A.S. Spinelli, D. Ielmini, A.L. Lacaita, A. Visconti, P. Olivo, "Drain accelerated degradation of tunnel oxides in Flash memories," IEDM 2002, pp. 167-170.

Radiation Damage•C. Claeys, H. Ohyama, E. Simoen, M. Nakabayashi, K. Kobayashi, "Radiation damage in flash memory cells," Nuclear Instr. And Methods in Physics Research B 186 (2002), pp. 392-400.•G. Cellere, A. Paccagnella, L. Larcher, A. Chimenton, J. Wyss, A. Candelori, A. Modelli, "Anomalous Charge Loss From Floating-Gate Memory Cells Due to Heavy Ions Irradiation", IEEE Trans. on Nuclear Science, December 2002, pp. 3051-3058.•G. Cellere, A. Paccagnella, A. Visconti, M. Bonanomi, P. Caprara, S. Lora, “A model for TID effects on Floating Gate memory cells” IEEE Trans. on Nuclear Science, December 2004, pp. 3753-3758

References (4)


Documents

FLASH MEMORY RELIABILITY - Intranet DEIBhome.deib.polimi.it/spinelli/corsi/nano/flash.pdf · † Introduction to Flash Memory † Intrinsic cell reliability: – Cycling Endurance