Final VLSI LAB Digital Analog Record 2

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Text of Final VLSI LAB Digital Analog Record 2

Dr Ambedkar Institute of Technology

prepared by Yajnesh Padiyar

Electronics & Communication

VLSI Lab06ECL77

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Dr. Ambedkar Institute of Technology

LABORATORY CERTIFICATEThis is to certify that Smt/Sri has satisfactorily completed the course of Experiments in Practical VLSI LAB prescribed by the Visvesvaraya Technological University Bachelor of Engineering course in the Laboratory of this college in the year.

Date

..Signature of the Teacher In charge of the batch

Head of the Department

Name of the Candidate .. Reg. No. . Examination Centre .. Date of Practical Examination ...

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INDEXI.

Getting started with cadence ASIC Flow

II. ASIC Digital Design Flow

Inverter Basic Gates Buffer JK Flip Flop SR Flip Flop D Flip Flop T Flip Flop MS Flip Flop Synchronous 4-bit up/down counter Asynchronous 4-bit up/down counter Serial Adder Parallel Adder

III. Analog Design

Inverter Design Common Drain Amplifier Common Source Amplifier

IV. VLSI Viva Questions

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I.

Getting started with cadence digital lab

1. Right click on the desktop and select open terminal 2. Now check the connection with server ping 192.168.3.81 if server connection is successful then u see a series of lines showing data transfer informations 3. A. Now type cd /mnt/cadence press enter B. then type ls press enter (ls is used to see the contents of present directory as DIR in DOS) C. now you must be able to see a series of files if not type mount -t nfs 192.168.3.81:/root/cadence /mnt/cadence repeat the instruction twice D. check set A and B again 4. After the 3 step its necessary to go back to root directory type cd / now type #cd / # source ~/cshrc (if u get error then type next step else skip it) #csh (now type the above step again and then continue) #ls (ls can be skipped if you know which is the next directory to go) #cd root #ls #cd Cadence_digital_labs #ls #cd Workarea #ls here u will be placing all your code files the 4th step can be done in single step #cd root/ Cadence_digital_labs/ Workarea 5. Now to compile and simulate the code type #ncvlog inverter_test.v mess (test bench compilation) #ncvlog inverter.v mess (RTL code compilation) #ncelab inv_test mess (elaboration) #ncsim inv_test (simulation) for GUI the first two commands remain the same but from third #ncelab inv_test access +rwc #ncsim inv_test -gui 6. The 5th step can also be done using the single step with GUI #irun inverter.v inverter_test.v access +rwc -gui

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Synthesize procedure

1. Go to rclabs directory in workarea#cd rclabs 2. Go to work directory in rclabs #cd work 3. Type #rc gui (this would start a GUI window) After the 3rd step again come back to the terminal type the following rc:/>set_attr lib_search_path ../library rc:/>set_attribute hdl_search_path ../rtl rc:/>set_attr library slow_highvt.lib (if this step gives an error then close the rc window and then type the following #cd / #cd root/Cadence_digital_labs #tar -xzvf Cadence_digital_labs.tar.gz this should work and then continue with RC labs again) rc:/>read_hdl {file_name.v} (in the above step it is necessary to copy the RTL code(file_name.v) to the folder rtl in the rclabs folder) rc:/>read_sdc ../constraints_filename.g (if any constraints file they must be read here) rc:/>elaborate rc:/>synthesize -to_mapped -effort medium (now you must be able to see the schematic . else go to file and click on update) rc:/>write > any_name.v rc:>report timing rc:/>report power rc:/>report area

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II.RTL Code module inverter(a, b); input a; output b; assign b = ~a; endmodule

ASIC Digital Design Flow 1. INVERTER

Test Bench Code module test_inv; // Inputs reg a; // Outputs wire b; inverter my_inv (a,b); initial begin // Initialize Inputs a = 0; #100; // Wait 100 ns for global reset to finish $display(a=%d |,a,b=%d,b); a = 1; #100; $display(a=%d |,a,b=%d,b); end endmodule

Block Diagram

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Output Waveform

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2. BASIC GATESRTL Code

AND Gatemodule and_gate(a,b,c); input a,b; output c; assign c = a & b; endmodule Test Bench Code module test_and; // Inputs reg a,b; // Outputs wire c; and_gate my_gate (a,b,c); initial begin a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 0; #100; $display(a=%d |,a,b=%d a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 1; #100; $display(a=%d |,a,b=%d end endmoduleBlock Diagram

|,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c);

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Output Waveform

RTL Code

OR Gatemodule or_gate(a,b,c); input a,b; output c; assign c = a | b; endmodule Test Bench Code module test_or; // Inputs reg a,b; // Outputs wire c; or_gate my_gate (a,b,c); initial begin a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 0; #100; $display(a=%d |,a,b=%d a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 1; #100; $display(a=%d |,a,b=%d end endmodule

|,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c);

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Block Diagram

Output Waveform

RTL Code

XOR Gatemodule xor_gate(a,b,c); input a,b; output c; assign c = a ^ b; endmodule Test Bench Code module test_xor; // Inputs reg a,b; // Outputs wire c; xor_gate my_gate (a,b,c); initial begin a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 0; #100; $display(a=%d |,a,b=%d

|,b,c=%d,c); |,b,c=%d,c);

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a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 1; #100; $display(a=%d |,a,b=%d end endmoduleBlock Diagram

|,b,c=%d,c); |,b,c=%d,c);

Output Waveform

RTL Code

XNOR Gatemodule xnor_gate(a,b,c); input a,b; output c; assign c = ~ (a ^ b;) endmodule Test Bench Code module test_xnor; // Inputs reg a,b; // Outputs wire c;

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xnor_gate my_gate (a,b,c); initial begin a = 0; b = 0; #100; $display(a=%d |,a,b=%d |,b,c=%d,c); a = 1; b = 0; #100; $display(a=%d |,a,b=%d |,b,c=%d,c); a = 0; b = 0; #100; $display(a=%d |,a,b=%d |,b,c=%d,c); a = 1; b = 1; #100; $display(a=%d |,a,b=%d |,b,c=%d,c); end endmodule Block Diagram

Output Waveform

RTL Code

NOR Gatemodule nor_gate(a,b,c); input a,b; output c; assign c = ~ (a | b;)

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endmodule Test Bench Code module test_nor; // Inputs reg a,b; // Outputs wire c; nor_gate my_gate (a,b,c); initial begin a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 0; #100; $display(a=%d |,a,b=%d a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 1; #100; $display(a=%d |,a,b=%d end endmodule Block Diagram

|,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c);

Output Waveform

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RTL Code

NAND Gatemodule nand_gate(a,b,c); input a,b; output c; assign c = ~ (a & b;) endmodule Test Bench Code module test_ nand; // Inputs reg a,b; // Outputs wire c; nand _gate my_gate (a,b,c); initial begin a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 0; #100; $display(a=%d |,a,b=%d a = 0; b = 0; #100; $display(a=%d |,a,b=%d a = 1; b = 1; #100; $display(a=%d |,a,b=%d end endmodule

|,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c); |,b,c=%d,c);

Block Diagram

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Output Waveform

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3. BUFFERRTL Code module buffer_1(a, b); input a; output b; not(ta,a); not(b,ta); endmodule Test Bench Code module buff_test; reg a; wire b; buffer_1 my_buff(a,b); initial begin a = 0; #100; a = 1; #100; end endmodule Block Diagram

Output Waveform

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4. JK Flip FlopRTL Code module jk_ff(j, k, clk, q, qb); input j,k,clk; output reg q,qb; reg kk = 1b0; reg [1:0] t; always@(posedge(clk)) begin t={j,k}; case(t) 2'b00 : kk = kk; 2'b01 :kk = 1b0; 2'b10 : kk = 1b1; 2'b11 :kk = ~kk; default: ; endcase q = kk; qb = ~q; end endmodule Test Bench Code module jk_test; reg j,k,clk; wire q,qb; jk_ff my_ff (j,k,clk,q,qb); initial clk = 1'b0; always #5 clk = ~clk; initial begin j = 0; k = 0; #10; j = 1; k = 1; #20; j = 0; k = 1; #10; j = 1; k = 1; #20; j = 1; k = 0; #10; end endmodule

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Block Diagram

Output Waveform

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5. SR Flip flopRTL Code module sr_ff(s,r, q,qb); input s,r; output reg q,qb; reg st = 1'b0; reg [1:0] k; always@(s,r) begin k = {s,r}; case(k) 2'b00 : st = st; 2'b01 :