Fab Benchmarking - Introduction - Smithsonian Institutionsmithsonianchips.si.edu/ice/cd/CEICM/SECTION4.pdf · Fab benchmarking is a practice used by ... fabs within a company is a

44Fab Benchmarking

Fab benchmarking is a practice used bysemiconductor manufacturers worldwide toassess the competitiveness of their manufac-turing operations. Benchmarking betweenfabs within a company is a common practice,as manufacturers today can have 20 or morefab lines worldwide. Comparisons amongdifferent semiconductor companies is lesscommonly performed and is typicallyaccomplished using outside consultingfirms. In any event, benchmarking is aformal practice designed to assess a fabÕs orcompanyÕs performance relative to the per-formance of world-class manufacturers.World-class semiconductor operations aredistinguished in terms of line and probeyields, manufacturing cost per wafer, laborproductivity, cycle times, tool productivity,and on-time delivery performance. World-class fabs also consistently improve perfor-mance in each of these areas throughsuperior practices in manufacturing technol-ogy, factory operation, organization, andmanagement. Importantly, a world-class fabdoes not have to be a manufacturer of state-of-the-art devices: It achieves excellent assetmanagement given the assets that it has.

This Chapter first defines world-class manu-facturing and presents associated perfor-mance objectives. It then explains howbenchmarking measures consist of several dif-ferent, yet interrelated categories including:

¥ Yields and yield learning¥ Process control and Computer integrated

manufacturing¥ Cycle time management¥ Tool productivity¥ Labor productivity¥ Human resources management¥ Customer satisfaction

In each of the categories, metrics of perfor-mance are defined and explained. Forinstance, within the category of tool produc-tivity are such metrics as cost of ownershipand overall equipment effectiveness. Fab-wide, companies often use various manage-ment strategies to target many or all of theabove goals. Chapter 5 which followsexplores the use of such management strate-gies and the practical implementation ofthese techniques by different semiconductormanufacturers.

Within this chapter, select results are alsopresented from a worldwide survey of 28fabs designed to identify operational prac-tices that underlie leading-edge manufactur-ing performance. The CompetitiveSemiconductor Manufacturing Survey[1],performed by the University of California atBerkeley over a five-year period, was thefirst study of its kind in the semiconductorindustry and it revealed the large variationin performance among semiconductor fabs.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-1

4 Fab Benchmarking

Fab Benchmarking

INTEGRATED CIRCUIT ENGINEERING CORPORATION4-2

Importantly, the study tied the achievementof high marks in a developed set of perfor-mance metrics with a list of key practices.

World-class Manufacturing Objectives

What makes an IC manufacturer or its sup-pliers world class? To maximize the produc-tivity of fab operations, IC manufacturerscontinually strive to:

¥ Increase yields,¥ Increase throughput,¥ Decrease inventories,¥ Decrease operating expenses, ¥ Decrease lead times, and ¥ Improve customer service.

These goals are accomplished by reducingmanufacturing cycle times, improvingthroughput (by increasing equipment pro-ductivity), and reducing the time spent per-forming non-value added procedures (i.e.,misprocessing, set-up of equipment, runningtest wafers). Therefore, world-class manufac-turing objectives become:

¥ Improved process capability,¥ Greater equipment availability/utilization,¥ Reduced misprocessing,¥ Higher yields,¥ Reduced step-up time of equipment,¥ Selective use of off-line metrology and

inspection equipment,¥ Faster learning and diagnosis (e.g., yield

ramp or yield learning),¥ Improved scheduling and maintenance

procedures,¥ Smoother transitions from R&D and pilot-

line operations to production,¥ Better understanding of processes and

manufacturing, and¥ Improved employee productivity and

morale.

Because so many of these objectives rely onequipment performance, the requirementsfor each piece of equipment become critical.

Equipment Selection Criteria

A short list of the most important criteria inequipment selection follows.

¥ Process capability, and flexibility to meetfuture requirements,

¥ High reliability (mean time between failureof at least 200 hours),

¥ High availability,¥ High throughput to maximize the number

of wafer processed,¥ Low, consistent, and predictable defect

density,¥ Serviceability, and¥ Low cost of consumables.

High yields are achieved when the processcapability of each piece of equipment is wellcharacterized and repeatable. As devicerequirements change more quickly and asproduct introductions shorten, equipmentmust increasingly be able to meet today'sperformance objectives and readily extend tomeet tomorrow's requirements.

Equipment selection criteria have changedover the last 20 or so years. While perfor-mance remains one of the key criteria, fabmanagers are increasingly stressing theimportance of equipment cost-of-ownership,serviceability, and reliability.

Benchmarking Yields and Yield Learning

Results from BerkeleyÕs CSM study indi-cated there are eight underlying themes forworld-class manufacturing. With respect toyield and yield management, key practicesof leading fabs in the study included:

Fab Benchmarking


¥ Rigorous management of SPC programs,retiring unneeded control charts andadding new ones as needed, adjusting con-trol limits as appropriate and adjusting fre-quencies of measurements to focus oncritical areas of improvement

¥ Automatic display of corrective actionguidelines when an out-of-control situa-tion occurs, often accompanied by auto-matic notification of the engineer andautomatic disabling of the equipment

¥ Automated uploading of metrology data,SPC measurements, tracking data, etc.

¥ Integration of engineering databases andin-line defect inspection results with data-bases of die yields, parametric measure-ments, allowing statistical correlationbetween die failures and causes

¥ Extensive analysis of wafer map and bit-fail patterns to trace faults to the root causeof the defects. The cause may be related toprocessing equipment, environment,people, etc.

¥ Automated recipe downloading at thetools with ÒsmartÓ lot-machine interfaces

Bringing New Equipment and Processesinto the Fab

Semiconductor manufacturers typicallyspend a lot of time and money bringing newequipment into the fab. Any reduction in thiscritical "yield learning" time can significantlyimprove the company's competitive posi-tion. In some cases, rapid yield learningallows the company to bring new devices tomarket faster, for which it can commandhigher prices, leading to higher profits. Bybringing equipment to a production-worthystate faster, the cost burden of the newly-pur-chased piece of equipment is also lessened.

Semiconductor firms use a variety of strate-gies to reduce the time-to-silicon or time-to-money. Today, equipment is often installed atthe vendorsÕ sites several months prior tobeing placed in the fab so that the newprocesses and equipment will be optimizedprior to fab installation. Marathon testing istypically performed to ensure adequate meantime between failure (MTBF) and mean timebetween repair (MTBR) rates on the equip-ment. Such processes have become more nec-essary as the complexity of equipment hasaccelerated over the years (both in terms ofhardware and software), and new equipmentdevelopment and introduction cycles haveaccelerated with advancing technology.

There are essentially three distinct, yet over-lapping stages a new piece of equipmentundergoes (Figure 4-1). First, the equipmentvendor typically develops a unit process orprocesses, which are usually tested first atthe vendor's site, known as alpha-site test-ing. The next phase is beta-site testing.During beta-site testing, the unit process orprocesses are customized for each of the ICmanufacturers processes, and the processmay be further optimized to allow for inte-gration. Beta-site testing can include process-ing of up to a thousand wafers. Many of thelarger IC houses will perform "Ironman" or"marathon" testing of new equipment at onesite, for the benefit of the entire organization.During such tests, equipment is run continu-ously and modifications to the equipmentare made to continually reduce mean timebetween failure and mean time to repairrates. In the third stage, the IC manufacturerpurchases additional equipment (ramp-up)to tool its facility. At this stage, minorimprovements that might only be realizedduring production are performed. Here we

Fab Benchmarking


review strategies used by Intel and Motorolato accelerate cycles of learning and ensurethe use of production-ready equipment inthe production line.

Intel's Partners With Vendor to EnableFaster Ramp-up

Intel recently used a partnership-basedmanagement strategy to develop and trans-fer a new process tool into production.[2]

The strategy was designed to ensure mini-mum impact to fab output, and fasterreturn-on-investment based on the mini-mization of process and equipmentchanges once the tool is installed in a man-ufacturing line. The equipment improve-ment program included proliferationmethodologies to rapidly improve equip-ment performance and improve site-to-siteprocess replication among Intel fabs. Thecomplete program reduced the cost of own-ership of the unit process by 60 percent dueto an increased throughput of 18 percent, a2X defect reduction, and a 4X increase inthe number of wafers processed betweenpreventive maintenance procedures. This

project was performed while both develop-ment and manufacturing fabs were in themiddle of an aggressive ramp.[2]

The upgrade consisted of nine modificationsto the chamber hardware and a processchange. It took nine months to complete, andinvolved interaction between five groupswithin Intel and four groups at the supplier.The article stresses the importance of closevendor-customer relations throughout thedevelopment phases. The project attemptedto eliminate past problems, including poorparts' quality, delays in delivery, insufficientdocumentation, insufficient operator train-ing, and poor process replication. Such prob-lems are at least partially due to the intensepressure on vendors to improve product per-formance and meet product introductiondates, often resulting in equipment introduc-tions that do not meet advertised benefits. Tomeet demand, vendors are compelled to sub-contract parts manufacturing to more thanone subcontractor, which can result in signif-icant lot-to-lot variation. In addition, withoutadequate training on specific hardware,parts may be installed incorrectly. The set ofprocess improvements on a 200mm CVDsystem are summarized in Figure 4-2.

Develop Unit Processes

Integrate Unit Processes

Proliferate Into Manufacturing

Time19874Source: Intel/SEMI/IEEE

Figure 4-1. The Entire Process Development Cycle Takes Two or More Years to Complete

Fab Benchmarking


Initially, the CVD tool had been fairly non-manufacturable, with very low uptimes andhigh defect densities. To improve uniformity,first, a new showerhead and wafer susceptorwere designed. While this change signifi-cantly improved uniformity, uniformity driftproblems after 150 wafers persisted. Next, anadditional clean recipe was developed.

To reduce variation in spare parts, thevendor was informed in advance about thescope of the project and was required tofreeze parts manufacturing processes so thatall spare parts manufactured would be iden-tical to those that were being beta-site tested.Then, an inspection procedure at the equip-ment vendor was developed to ensure 100

percent inspection of each part for qualitycontrol. A documentation procedure wasalso instituted to ensure parts quality.

Next, the equipment engineers that installedthe parts during alpha site testing trained theequipment engineers, and this team thentrained the Intel technicians at each site inproper part installation.

In spite of this high level of control, out-of-specification parts were still shipped,emphasizing the need to improve vendor-customer relations. Site-to-site process repli-cation, due to small differences in systemsset-up (such as different pumps), continuedto be an issue. One procedure that aided

Figure 4-2. Steps Taken to Improve the Manufacturability of a 200mm CVD Tool and Benefits Gained

STEPS• Developed new shower-head and susceptor to improve uniformity.• Added cleaning step to reduce defect levels.• All parts were inspected 100% by the design group at the vendor's

site to provide quality control.• The vendor's field Custom Engineers (CEs) were trained to ensure

proper part installation during beta-site testing.• Documentation of part quality, manufacturer, and all other part

characteristics.• Had CEs train maintenance engineers at each semiconductor facility

to assure proliferation of proper installation and maintenance procedures.• Executed procedures to assure on-going feedback to vendor regarding

parts supply and parts quality.• Used "Copy Exactly" concept to document processes, systems, and

procedures affecting wafer processing on the system. Process recipes,specifications, metrology tool type, and operational methodologies werecopied across all fab lines, speeding qualification of hardware and processesat all other fab sites.

• Proliferation to manufacturing sites focused on resources and alignment tovendor/customer expectations rather than development.

BENEFITS• 18% increase in CVD system throughput• 2x reduction in defects• 3mm die edge recovery to gain more die per wafer• 4x increase in number of wafers processed between PM procedures

19986Source: ICE

Fab Benchmarking


site-by-site replication was the use of a"copy exactly" procedure, where processrecipes, specifications, etc., for a particularmodule were copied across all fabs manu-facturing a particular product. Proliferationwas thereby simplified, as the qualificationat the manufacturing sites was viewed moreas an extension of a "post-PM qualification,"rather than a new hardware qualification.This resulted in substantial savings in testruns and manpower.[2]

Motorola Targets Faster Cycles of Learning

Motorola recently outlined a proactiveapproach to equipment development,aimed at shortening the cycles of learningon new processing equipment.[3] The pro-gram uses "Ironman" testing and a compre-hensive debug process at the vendor's siteto allow the manufacturing robustness ofboth software and hardware components ofprocess tools to be increased. The programcontinually tracks how quickly designproblems are fixed, so that engineers candrive key parameters to lower values ofmean-time-to-failure, mean-time-betweeninterrupt (or repair), and cost of ownership.As a result, the quality and cost effective-ness of the delivered equipment isimproved, and the cycle time for bringingthe equipment to a production-worthystate is shortened significantly.

Motorola first created Strategic EquipmentTeams, empowered to identify the technolo-gies and equipment needed to processfuture devices. The teams could eitherchoose commercially available equipmentor, if not satisfied with these systems,engage in joint development programs withthe vendors to assure development and

"burn-in" of systems and the availability ofproduction-worthy equipment within ausable timeframe. The teams:

¥ Established sector-wide equipmentroadmaps,

¥ Integrated equipment evaluations anddevelopment methodologies sector-wide,

¥ Benchmarked equipment performance inexisting factories,

¥ Recommended manufacturable equipmentsets for future factories, and

¥ Sent a single message to suppliers, reflect-ing needs of the entire sector.

One of the techniques the company used toimprove supplier performance includedinstalling a Motorola-owned processingtool at the vendor's site for parallel use byits engineering group and Motorola engi-neers. Typically, latest products are notreadily available for the vendor to performhardware and software testing. In thisprocess, the engineering team at thevendor's site identified faults in the system,and executed Engineering Change Notices(or the equivalent) to drive continuousimprovement of the equipment hardwareand software in a timely manner. A keyissue was ensuring that the engineeringproject manager could implement suchchanges and proliferate them in the field,into the vendor's manufacturing, and intothe new product design.

The focus of "Ironman" tests is to improvethe performance of the integrated hardware,wafer transfer, and process control of theequipment. Motorola has found in previousIronman studies, that approximately 90 per-cent of all manufacturing performance issuesidentified with available tools in the early

Fab Benchmarking


stages are either hardware or softwarerelated. This is key as vendor's equipmentimprovement efforts typically focus onprocess performance, not equipment manu-facturability or robustness. During theseIronman test, the equipment:

¥ Runs a process recipe 24 hours a day unlessrequired for process development ordesign evaluation related activities,

¥ Undergoes routine PM , start-up, and shut-down procedures, testing all hardware andsoftware capability of the tool, and

¥ Undergoes system hardware and softwareupgrades and process enhancements.

The equipment debug phase generallyundergoes three stages of learning. First,major improvements are made, resulting inup to 5-20 hour MTBI (mean-time-between-interrupt), with the second stage extendingthat level to 20-60 hours MTBI. The third andmost challenging cycle is when MTBIapproaches 120 or more hours. During theentire debug process, the teams continuallytrack the time it takes to identify an issue,

design a fix, evaluate the new design, andmake the fix available. A metric tracking thecycles of learning is identified and improvedupon in a systematic manner.[5] The equip-ment improvement at the supplier site is crit-ical, as it represents full departure fromprevious procedures in which the equipmentwas essentially debugged by the customersin the fabs in a non-competitive fashion.[5]

The article points out how process tool test-ing has evolved with the increasing softwarecomponent in semiconductor equipment(Figure 4-3). In the 1970s and 1980s, testsfocused on mechanical and electrical perfor-mance. Today, while understanding ofmechanical failures has evolved to a sophis-ticated level, expertise in software program-ming has not developed as quickly. Inaddition, certain problems can be both soft-ware- and hardware-related. In Motorola'sstudy, this was evidenced by the number ofsoftware fixes for different iterations of asystem's software, which did not continu-ously improve (Figure 4-4).

ReliabilityLevel

Time Period

Hardware SoftwareStatistical Test

Percent or Parts Per Thousand

Parts Per Million

Parts Per Billion

1970s

1980s

1990s

1990s

2000s

2010s

Test all

Sampling

Varied Statistical– Accelerated testing– Burn-in testing– ESS– Life testing– (etc.)

19875Source: Motorola/IEEE/SEMI

Figure 4-3. Software development Has Become a Key Aspect of Process Tool Development

Fab Benchmarking


The article suggests that Ironman studies berun only after the equipment has demon-strated MTBI levels of 120 hours or more.When this level is attained, any introduc-tions of hardware or software to the tool willslow development and may actually degradesystem performance. It also recommendsthat the supplier run marathon tests continu-ously, while tracking and improving on thetime needed to implement design fixes.

By installing the Motorola-owned equip-ment at both the vendor's site and the user'ssite, parallel, more cost-effective programsfor process improvement were possible.

From year-to-year, the 800 plus existing fabsare being made more cost effective out ofnecessity. In 1994 and early 1995, many exist-ing fab expansions and upgrades were beingperformed in conjunction with improvementprograms to increase the effectiveness ofexisting equipment and facilities.

For many of these companies, the focus is onproducing non-leading-edge devices (2.0-0.8µm), on 100, 125, or 150mm wafers.Because the profits on devices shrink withmaturity, the company must continuallyreduce manufacturing costs, while produc-ing the greatest number of good devices perwafer start (e.g., high productivity and highyields). As shown in Figure 4-5, the largestpercentage of wafers used in 1994 were150mm (38 percent), and approximately thesame number of 100 and 125mm waferswere used (28 and 27 percent). Only 7 per-cent of the wafers used were 200mm.However, ICE expects this situation tochange rapidly. Interestingly, a glance atregional wafer usage (Figure 4-6) revealshow the North American, European andROW countries consume many more100mm wafer than the Japanese. The distri-bution of fab capacities listed in ICE's 1995Profiles report indicates how fab capacitiesranges anywhere from 500 wafers per weekto over 30,000 wafers per week. The goal forall these companies is to meet world-classmanufacturing objectives.

The Importance of Cycle Time Management

Cycle time is the time needed to fabricatedevices. More specifically, it is the timerequired to process a product from start tofinish -- either from wafer start to the timethe final passivation layer is put on the wafer(wafer processing time), or from wafer startto the time the packaged device is ready forshipping. Average wafer processing time forfabs worldwide is between 30 and 90 days.

RevisionsRequired

Fixes

2.1

2.2

2.3

2.4

2.5

2.7

2.8

3.0

Average

105

73

24

7

23

45

29

27

42

19876Source: Motorola/IEEE/SEMI

Figure 4-4. Number of Fixes for DifferentRevisions of Software Programs Do Not

Necessarily Improve

Fab Benchmarking


The principle advantage of fast cycle timemanufacturing is rapid yield learning. "Yieldlearning" time, also called defect learningtime, refers to the time required to bring anew product's yield to acceptable levels.Yield learning time is typically between 6months and 2 years, depending on produc-tion capability, engineering capability, anddevice complexity. The obvious advantage to

low yield learning time is in reducing time-to-market, often enabling the company tosell the chips at higher prices and morerapidly recoup investments. Not surpris-ingly, the first company bringing newdevices to market is typically in a muchbetter position to dominate the market forthat particular product.

≤100mm28%

125mm27%

150mm38%

200mm7%

19743ASource: ICE

7.8 MillionWafers/Month

*As of the end of 1994

Figure 4-5. 1994 Worldwide Distribution of Wafer Size Capacity


1994

≤100mm17%

125mm39%

150mm39%

200mm5%


1994

≤100mm38%

125mm25%

150mm28%

200mm9%


1994

≤100mm34%

125mm33%

150mm24%

200mm9%


1994

≤100mm32%

125mm17%

150mm43%

200mm8%

*As of the end of 1994

19745ASource: ICE

JAPAN NORTH AMERICA

EUROPE ROW

Figure 4-6. Regional Monthly Wafer Capacity by Wafer Size*

Fab Benchmarking


Rapid cycle time manufacturing is alsobecoming more critical as product lifecyclescontinue to shorten. As discussed in Chapter1, products command the highest pricesearly in their lifetime. Therefore, the fabÕsability to rapidly ramp to high volume pro-duction of devices with the highest ASPsbecomes even more important. Obviouslythe reduced cost per wafer realized whenproduction levels are reached are a strongincentive as well.

Fast cycle time manufacturing also meansmore wafers are processed in a given time-frame, so that processing problems can bedetected more quickly and the yield of agiven device can be improved more quickly.Industry experts have discovered time andagain that a company's profitability largelydepends on its ability to rapidly identify andfix processing problems.

The actual cycle time of products in a fab islimited at the low end by the raw processtime for a wafer undergoing a certainprocess. Often referred to as the theoreticalcycle time, this time is typically between 5and 10 working days or 120 and 240 hours. Inpractice, a fab tries to attain an actual cycletime that is between 2X and 3X the theoreticalcycle time. A cycle time of 2.5-3.0 days permask layer is considered average, a 2-daycycle time per layer is very good and a world-class fab is capable of processing a layer in 1.2days. Some examples of cycle time per layerfor Memory fabs is shown in Figure 4-7.[1]

Figure 4-8 and 4-9 show similar data forCMOS Logic and MSI cycle times per layer.

However, it is important to note that shortcycle time manufacturing does have its down-sides. To achieve faster cycle time, a largerequipment set is usually required so thatproduct is not waiting for tool availability. In

addition, although low cycle time enhancesthe likelihood of on-time delivery of devicesand allows faster yield learning, it will notnecessarily reduce manufacturing cost perwafer. Inventories are lower, but smallerbatches of devices may need to be processedso that processing time at any one piece ofequipment is not too long.

The Most Important Trends in EquipmentDesign

Many of the trends discussed throughoutthis book are critical to new fab equipmentoperation. To enable faster yield-learning:

¥ Equipment efficiency must be increasedmore rapidly in the pre-production stagesof development (Figure 4-10),

¥ The manufacturability of equipment Ñthroughput, cost of consumables, and costof maintenance must be targeted duringequipment design phases,

¥ Unless the equipment vendor has exten-sive software programming capabilities,third- party suppliers should be used tofacilitate faster time-to-market,

¥ Users and vendors should work togetherto take advantage of the latest hardwareand software capabilities,

¥ Equipment must be capable of extendingbeyond one generation of product,

¥ Partnerships should be formed early indesign phases to speed time-to-market ofequipment and ensure customer satisfaction.

In addition to these trends, emerging featureson production tools such as minienviron-ments, in-situ particle monitors, equipmentcontrol interfaces, etc., must be consideredearly in the design phases. Progressive equip-ment companies are also using modeling pro-grams during equipment design stages toimprove the quality of delivered product.

Fab Benchmarking


L1L2L3L4L5L6L7L8L9L10L11L12L13L14L15L16

1988 1989 1990 1991 1992 1993 1994 1995 1996

6

5

4

3

2

1

7

Cyc

le T

ime

Per

Lay

er (

Day

s)

Time

Source: University of California Berkeley 22919

Figure 4-8. CMOS Logic Fab Cycle Time Per Layer

M1M2M3M4M5M6M7M8M9M10

1988 1989 1990 1991 1992 1993 1994 1995 1996

6

5

4

3

2

1

Cyc

le T

ime

Per

Lay

er (

Day

s)

Time


Figure 4-7. Memory Fab Cycle Time Per Layer

Fab Benchmarking


19803Source: Samsung Electronics

Overall Equipment Efficiency Number of Breakdowns

Rel

ativ

e P

erce

nta

ge

Rel

ativ

e P

erce

nta

ge

65

60

50

40

30

20

10

010 02 3 4 5Years of Operation

1 2 3 4 5Years of Operation

100

80

60

40

20

0

Figure 4-10. Equipment Efficiency as a Function of Product Maturity

1988 1989 1990 1991 1992 1993 1994 1995 1996

6

5

4

3

2

1

Cyc

le T

ime

Per

Lay

er (

Day

s)

Time


B1B2B3B4B5B6B7B8

Figure 4-9. MIS Fab Cycle Time Per Layer

Fab Benchmarking


Future tools also need real-time feedbackand control of critical process parameters,optimization of batch size to reduce cycletime, and advanced product tracking toincrease the productivity of the fabs."Minibatch" tools may provide the best solu-tion for single-wafer quality with batchthroughputs. Such tools include theNovellus Concept One and Dual-Altusdielectric CVD and tungsten CVD systems,which process several wafers sequentially,Concept Systems' Gemini III epi tool orMattson's Aspen stripper and CVD tools,which process small batches, or W-J's 1000APCVD tool, which processes several wafersin an "assembly-line" mode.

Useful Tool Lifetime

To effectively reduce manufacturing costs,many manufacturers will attempt to useequipment for as long as possible. Tool life-time varies depending on the type of process-ing equipment and the processingrequirements of the devices being manufac-tured. In cases where device dimensionsremain relatively stable for a long period oftime, the fabs have very mature equipment,including 15-year-old projection aligners, 20-year-old ion implanters, and 20-year-old ICtesters. However, in this industry, such exam-ples are really exceptions to the rule. Lifetimesof some tools are often limited to only one ortwo generations of devices (3-6 years).

Fabs purchase new equipment if the existingequipment can no longer attain the desiredprocess result, if it is converting from onewafer size to another, or if it is expandingcapacity (in which case, used equipment

might also be considered). In making transi-tions in device generation, the equipmentcan often be upgraded or undergo an equip-ment improvement program (EIP) to allowits use in processing the new product.Typically, 60-90 percent of the existing equip-ment set can be used to produce next-gener-ation devices. Companies can effectivelyminimize the investment for next-generationtechnology by limiting the amount of newequipment purchased to less than 20 percent(reusing 80 percent), spending no more thana 1.5X premium for next-generation tools,and controlling the increase in the number ofprocess steps to 1.1X (via device design andequipment capability). This strategy, used byIBM in the manufacture of DRAMs, slowsthe overall increase in wafer processingcosts, and allows more timely return oninvestment (Figures 4-11 and 4-12).

Productivity to Customers

Technology Change

Bits/Chip

Chip Area

Density

Equipment Cost

Complexity (No. steps)

Unit Price Increase

Total

2.8x

4.0x

1.4x

2.8x

1.2x

1.5x

1.8x

40%

58%

12%

40%

6%

15%

22%

Per Generation Per Year*

*3 years is 1 generationSource: IBM Microelectronics 19771

Figure 4-11. DRAM Industry Trends

Fab Benchmarking


All existing fabs continually undergo fre-quent changes and adjustments, and sharethe same constraint including[1]:

¥ The need to continue production opera-tions during expansion,

¥ Restrictions in cleanroom space and layout,¥ Constraints in available capital and operat-

ing costs,¥ Fixed time to implement changes,¥ Given process capabilities,¥ Given cleanroom design (Class 100, Class

10, etc.),¥ Given labor force,¥ Existing customer commitments and

inventories, and¥ Existing process flows.

Equipment Productivity

Equipment productivity is a key issue inmanufacturing as the performance of eachwafer processing tool ultimately affects fabproductivity, cycle time, and the company'sability to meet customer demands fordevices. A semiconductor processing tool isavailable for production when it is not downdue to system failure, or the performance ofpreventive maintenance (PM) or qualificationprocedures. The amount of time the system isutilized relative to the time it is available forproduction, is the effective utilization. One ofthe results of Texas InstrumentsÕ landmarkMMST (Microelectronics ManufacturingScience & Technology) program was the find-ing that the effective utilization of semicon-ductor equipment averages only 35percent[2]. As detailed in Figure 4-13, the restof the time is spent:

��

19800Source: IBM Microelectronics

Percent Fab Equipment Cost For New Generation Tools

10 20 30 40 50

1.0

1.2

1.4

1.6

1.8

2.0

1.9

1.7

1.5

1.3

1.1

New

Gen

erat

ion

Eq

uip

men

t P

rem

ium

Lose

Win

Figure 4-12. Profitability Strategy

Fab Benchmarking


¥ Setting-up the equipment to process thewafer (s) (including test wafer runs),

¥ Waiting for product to traverse through theproduction line,

¥ Misprocessing wafers due to drift in pro-cessing parameters or using the wrongprocess recipe,

¥ Adjusting process parameters,¥ Processing bad material, or¥ Performing scheduled or unscheduled

maintenance procedures.

Such procedures lead to poor utilization ofcapital. In addition, as companies make tran-sitions in wafer size, especially from 150mmto 200mm, the throughputs of tools accom-plished in production have dropped. Batchto single wafer transitions in the fab alsoincrease the amount of WIP and limit fabproductivity.

Therefore, cost-reduction strategies that min-imize misprocessing, set-up time, test waferuse, and unscheduled maintenance, willimprove equipment utilization, and conse-quently, the productivity of the fab.

The COO model typically relates cost perwafer for a given device to labor rates, cost ofconsumables, spare parts, scrap, mainte-nance, off-line metrology, facilities, etc. Fromconstructed Pareto charts that show the mag-nitude of each cost element, the manufac-turer can target the most costly segments(Figure 4-14). In general, COO modeling hasshown the industry that machine through-put, tool reliability, and defect limiting yieldoften have a more significant impact on COOthan equipment purchase price.

Production70%

Special Work8%

OperatingLoss 2%

Non-EquipmentLoss 8%

EquipmentLoss 12%

Production35%

Special Work13%

OperatingLoss 11%

Non-EquipmentLoss 13%

EquipmentLoss 28%

GOALCURRENT

19756Source: TI

��

��

��

��

��

��

��

��

��

��

��

��

• Downtime• Calibrations• Set-Up• Maintenance• Pilot Runs

• Operator Skills• No Operator• Training• Meetings

• Misprocessed• Bad Material• No Material• Not Processed

• Process Adjustments

• Beneficial Production

• Preventive Maintenance• Calibrations• Repair

• Training• Meetings

• Waiting for Material

• Process Adjustments

• Beneficial Production

Figure 4-13. Improving Capital Productivity

Fab Benchmarking


However, despite its attributes, COO model-ing cannot indicate how effectively a systemis used in production.[3] For these reasons, anew metric, overall equipment effectiveness(OEE) is now gaining industry attention.

Overall Equipment Effectiveness (OEE)

OEE is the time a given system spends pro-ducing product wafers. As shown in Figure4-15, the goal, determined using SematechÕsfab model, is to improve equipment effec-tiveness to over 60 percent for the 0.25µm

generation of equipment. An OEE of 60 per-cent means that the majority of losses are dueto the fact that no product is available forprocessing (no WIP), with much smaller con-tributions from throughput loss, scheduledand unscheduled downtime, and setup pro-cedures. The hope is that by focusing onOEE, manufacturers will be able to improvemaintenance procedures, setup proceduresand make modifications to increase machinethroughput, reduce rework, etc.[5] OEE isalso related to another important industrymetric, labor productivity.

Figure 4-14. Sematech Cost-of-Ownership Model

Cost per wafer =

where,

• $F = fixed cost

• $V = variable cost

• $Y = cost of yield loss

• L = equipment life

• TPT = throughout rate

• Y(TPT) = throughout yield

• U = production utilization capability

Cost of yield loss =

where,

• W(TPT) = wafers lost to throughput yield

• $P = value of wafer at process step

• W(D) = wafers lost to defect-limited yield

• $T = value of wafer at test

Wafers lost to defect-limited yield = R x L (1– )where,

• R = wafer per week

• L = equipment life

• A = die area

• P = defect fault probability

• D = physical defect density

Production utilization capability =

where,

• SM = scheduled maintenance

• USM = unscheduled maintenance

• TEST = production test

• TA = assist time

• STBY = standby

$F + $V + $YL x TPT x Y(TPT) x U

[W(TPT) x $P] + [W(D) x $T]

1 1 + (A x P x D)

(SM + USM + TEST + TA + STBY)168

1–

19750Source: Semiconductor International

Fab Benchmarking


Cost of Ownership

Many companies use activity-based costing(ABC) to determine the relationship betweenthe cost of devices produced by a fab andeach of the components that contribute to thiscost. Typically, ABC is implemented by form-ing the ABC team, developing the ABCmodel, costing the product line, planning costreduction efforts, implementing cost reduc-tion, and evaluating results. Cross-functionalteams typically contain employees from allfactory departments including finance, pur-chasing, technology development, processengineering, equipment engineering, produc-tion control, and facility groups. The ABCmodel demonstrates cost per wafer sensitiv-ity to composite yield, production volume,utilization rate of existing equipment, and thecost of purchasing new equipment.

One type of activity-based costing tech-nique is cost of ownership (COO) modeling.The Sematech COO model (Figure 4-14) andits many modified versions, are gainingpopularity among North American compa-nies. It is commonly used by equipmentmanufacturers and IC manufacturers to

compare the cost of new, competing piecesof processing equipment. Some companies,particularly U.S. semiconductor manufac-turers, also use modified versions of themodel to estimate the cost components oftool sets in a well-established productionline, an existing product line that is under-going expansion, or a new product line. Anexample of a COO calculation is shown inFigure 4-16.

The cost of ownership model typicallyrelates cost per wafer for a given device tolabor rates, cost of consumables, spare parts,scrap, maintenance, off-line metrology, facil-ities, etc. From constructed Pareto charts thatshow the magnitude of each cost element,the manufacturer can target the most costlysegments (Figure 4-17). In general, COOmodeling has shown the industry thatmachine throughput, tool reliability anddefect limiting yield often have a more sig-nificant impact on COO than equipmentpurchase price. For existing product lines, afocus on the top five cost elements, as well asspecific areas where dollars are expendedeach year to keep the tools operating (i.e.spare parts, setup requirements, chemical

OEE30%

OEE61%

UnscheduledDowntime

15%

Speed15%

Setup10%

Idle Operator10%

Test Wafers8%

Not Schd.5%

Idle NoProduct

5%

Quality2%

No WIP24%

ThroughputLoss 8%

PlannedDowntime

4%

UnplannedDowntime

1%

Setup2%

CURRENT OEE IS 30% OEE GOAL IS OVER 60%Source: Sematech/Semiconductor International 21074

Figure 4-15. Overall Equipment Effectiveness

Fab Benchmarking


consumption, power, etc.) can lead to a sim-plified, more useful model.[4] A team foreach operation is set up to:

¥ List all the major components required toperform the task,

¥ Collect data to estimate cost of the itemsover a particular time frame (weeks,months, years),

¥ Perform Pareto chart analysis by dividingtotal costs by total number of wafers pro-duced,

¥ Target key areas for cost reduction, estab-lish action plan,

¥ For parts/services provided by vendors,work with vendors to lower cost, extendthe life, decrease the quantity required, andconsider purchasing the part from theOEM rather than a distributor, and

¥ Obtain quotes from other vendors, giveoriginal vendor opportunity to lower prices.

For fabs undergoing a facility expansion, themodel is a little more complex as it mustfactor in floor-space, equipment cost anddepreciation, and facilities requirements.[5]

Production

Throughput yield

Defect density (defects/cm2)

Probe yield

Composite yield (throughput yield x probe yield)

Production utilization capability*

Equipment

Original capital cost per system

Raw throughput (throughput at capacity)

Maximum wafer starts per week per system

Equipment utilization capability**

Headcount Per Shift

Direct

Maintenance

Indirect

Total

Top Three Cost Drivers

Scrap

Consumables

Equipment (depreciation, moves, space, training)

All others

Cost Per Good Wafer Out

99.95%

0.01

98.22%

98.17%

63.20%

$3,400,000

57

5,992

87.13%

0.9

0.3

0.5

1.7

39.49%

27.98%

14.34%

18.19%

$/wafer

$0.13

$9.05

$9.18

$3.08

$0.47

$0.13

$0.42

$1.02

$9.18

$6.50

$3.33

$4.23

$23.25

Production utilization capability: The maximum production utilization forthe given qualification requirements.

PUC = Equipment Utilization Capability (EUC) - (scheduled process qual time)/168 hours as a percentage.

Equipment Utilization Capability: The maximum utilization possible forthe given equipment downtime characteristics.

EUC = 1 – (scheduled maintenance + unscheduled maintenance)/168hours as a percentage

*

**

Source: Sematech/Solid State Technology 19765

Management Summary

Figure 4-16. Sample COO Summary

Fab Benchmarking


Labor Productivity

Labor productivity in actual fabs is shown inFigure 4-18. As indicated, the most competi-tive fabs in the study completed 63 layers peroperator per day. The least competitive wasat 8 layers and the average was 29.6 layersprocessed per operator per day. Expandingbeyond direct labor, the labor productivity inlayers completed per total staff per dayranged between 3.3 and 37.7 with the averagecoming in at 17.6 layers per individual perday.[6] Other information in this table indi-cates the dramatic differences in performanceamong semiconductor fabs worldwide.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Flo

or

Sp

ace

Mo

nit

ors

Fac

iliti

es

Mai

nte

nan

ce

Mea

sure

men

ts

Scr

ap

Sp

are

Par

ts

Co

nsu

mab

les

Ch

emic

als

Dep

reci

atio

n

Op

erat

or

50

60

70

80

90

100C

ost

Per

Cat

ego

ry (

$)

To

tal c

ost

(%

)

Category19850Source: IBM Microelectronics/IEEE/SEMI

Figure 4-17. A Pareto Chart Indicates Areas to Focus on to Reduce Total Cost

Fab Benchmarking


References

1. R. Leachman, ÒThird Report on theResults of the Main Phase, CompetitiveSemiconductor Manufacturing SurveyÓ,University of California at Berkeley,August 15, 1996.

2. S. Tripathi and F. Moghadam,ÒMethodologies of Supplier Partnershipand Manufacturing Implementation ofContinuous Improvement Projects,ÓIEEE/SEMI Advanced SemiconductorManufacturing Conference Proceedings,1994, p. 56.

3. E. Keller and J. Bukhman, ÒA Method forAccelerating Cycles of Learning in theSemiconductor Equipment Industry,ÓIEEE/SEMI International SemiconductorManufacturing Science SymposiumProceedings, 1993, p. 70.

4. K. Steeples, et.al., “Cost of OwnershipBenefits Using Multiply Charged IonImplants on Conventional Medium and HighCurrent Implanters,” IEEE/SEMI AdvancedSemiconductor Manufacturing ConferenceProceedings, 1993, p. 223.

5. P. Rahaim, “The Cost of Ownership,”IEEE/SEMI Advanced SemiconductorManufacturing Conference Proceedings,1994, p. 186.

6. D. Art, M. OÕHalloran, and B. Butler,ÒWafer Fab Construction Cost Analysis& Cost Reduction Strategies:Applications of SematechÕs FutureFactory Analysis Methodology,ÓIEEE/SEMI Advanced SemiconductorManufacturing Conference Proceedings,1994, p. 16.

Cycle Time per Layer (Days)

Line Yield per Ten Layers (%)

Murphy Defect Density (Defects/cm2)

0.7 - 0.9µm CMOS Memory

0.7 - 0.9µm CMOS Logic



5x Stepper Throughput (5x LayersCompleted per Machine-Day)

Direct Labor Productivity (WaferLayers Completed/Operator-Day)

Total Labor Productivity (WaferLayers Completed/Total Staff-Day)

On-Time Delivery (% of Line ItemsWith 95% of Die Output on Time)

1.2

98.9

0.28

0.28

0.23

0.21

724(30 w/hr)

63.0

37.7

100%

3.3

88.2

1.52

1.94

0.96

1.15

140(6 w/hr)

8.0

3.3

76%

MetricBest

Score

2.6

92.8

0.74

0.79

0.47

0.61

382(16 w/hr)

29.6

17.6

89%

AverageScore

WorstScore

Note: Average and worst scores are calculated after discarding the worst data sample for each metric.Source: UC Berkeley/ICE, "Mid-Term 1996" 21069

Figure 4-18. Results of Competitive Semiconductor Manufacturing Survey

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