Experimental Optimization of Decoupling …...Cosmin Iorga - NoiseCoupling.com - [email protected] 1 DesignCon 2012 Experimental Optimization of Decoupling Capacitors

Cosmin Iorga - NoiseCoupling.com - [email protected] 1

DesignCon 2012

Experimental Optimization ofDecoupling Capacitors in FPGADesigns by On-Die Measurementof Power Distribution ImpedanceFrequency ProfileCosmin [email protected] (805) 231-9786


Outline

Overview of PDN Design and Optimization

Typical PDN Design Methodology

Differences Between PDN Impedance On-Die and On-PCB

Proposed PDN Design Methodology

FPGA Configuration for On-Die PDN ImpedanceMeasurement

Case Study Implemented in a Spartan 3A FPGA

Conclusions


Overview of PDN Design andOptimization

Define power and ground planes in PCB stackup

Design mounting layout structures for decoupling capacitors

Assign physical location of decoupling capacitors on the PCB

Determine values and types of decoupling capacitors


Typical PDN Design Methodology

Modeling and simulation toolsincrease cost

Iterative process may consumesignificant schedule time

No visibility of PDNimpedance seen by on-diecircuits

Expensive measurementinstruments (VNA …)


Differences Between PDN ImpedanceOn-Die and On-PCB

FPGA

As seen by on-PCB measurements (example VNAone-port or two-port)

As seen by the FPGA on-die circuits - which generate transientcurrents and are affected by supply noise


Differences Between PDN ImpedanceOn-Die and On-PCB

As seen by on-PCB measurements (example VNAone-port or two-port)

As seen by the FPGA on-die circuits - which generate transientcurrents and are affected by supply noise


Proposed PDN Design MethodologyTypical Methodology Proposed Methodology


Proposed PDN Design Methodology

PCB Stackup:

PCB Layout:

Place “open” capacitor pads asmany as could be fit

Use multiple pad sizes

Place pads close to FPGA asfloorplan allows

Larger pads for electrolytic ortantalum may be further apart

Reduce spacing betweenpower/ground planes


On-Die PDN Impedance Measurement


AC Steady-State AnalysisImplemented in FPGAs

A group of FPGA configurable logic blocks is configured tofunction as a sinusoidal current source

Another group of FPGA configurable logic blocks is configuredto form a ring oscillator

(patent pending technology)


Sinusoidal Current SourceImplemented with FPGA Logic Blocks

The sinusoidal current is obtained by summing the dynamic loadcharging and discharging currents of multiple CMOS gates, built as partof CLB blocks

∑ = SINCLB Ii

(patent pending technology)


AC Steady-State AnalysisImplemented in FPGAs

The sinusoidal current flows through the power distribution networkand generates sinusoidal variation of the on-die power supply voltageThe sinusoidal variation of the voltage supply modulates thefrequency of the ring oscillatorA counter circuit measures the frequency of the ring oscillator

PDN impedance is calculated from the average frequency deviation(patent pending technology)


Proposed PDN Design MethodologyTypical Methodology Proposed Methodology


Case Study

The proposed PDN impedance measurement techniqueimplemented in a Spartan 3A FPGA on a test board

PDN impedance frequency profile measured atfrequencies up to 500MHz

Decoupling capacitors chosen by experimentaloptimization

Additional design tradeoffs studied through this technique

FPGA clock frequency chosen based on on-die PDNimpedance profile


Case Study

Implementation of PDN Measurement Method

FPGA Clock Distribution Block

PDN Measurement Block

The PDN measurementblock needs a clock signal,which is provided by theFPGA clock distribution

The PDN measurementblock uses a serial interfaceconnected to FPGA I/Oblocks


Case Study

Device Utilization Summary in a Spartan 3A FPGA


Case Study

Experimental Optimization of DecouplingCapacitors

Start with “open pads” or“best guess” values fordecoupling capacitors:

C39, C43, C44, C45, C50


Case Study

Measured on-die PDN impedance frequency profile

Measurement up to 500MHz

Not accurate below 20kHz

Accuracy can be extendedbelow 20kHz with theexpense of increasedmeasurement time


Case Study

ExperimentalOptimization ofC45

1nF 22nF

47nF

100nF

220nF

Starts with 1nF andgradually increases up to220nF

Values larger than 220nFdo not further reduce theimpedance


Case Study

Remaining resonance peak at220MHz

Capacitive deep at 320MHz

This resonant peak is causedby inductance and decouplingcapacitors in the package

After optimization a resonantpeak at 220MHz still remains

The intended FPGA clockfrequency of 200MHz ischanged to 320MHz wherethe PDN impedance has aminimum

Package and Die Contribution


Case Study

Capacitors removed

Capacitors with addedmounting inductance

Example of Further PDN Optimization Study

Feasibility study ofmoving C39, C43, C44,C50 outside the FPGAregion and using full viasinstead of blind vias

Additional inductanceadded by liftingcapacitors and addingwire jumpers


Test Case Summary

This test case has evaluated how the proposed FPGA on-die PDNimpedance measurement technique can help with:

Selection of decoupling capacitors’ values and types

Trade-off between placement of decoupling capacitors and PCBmanufacturing cost reduction (blind vias versus full vias)

Identifying that the intended FPGA core clock frequency of200MHz was too close to a PDN resonance peak at 220MHz

Locating a minimum PDN impedance at 320MHz where theFPGA clock has been set to operate

Some of these PDN improvements have not been possible with only on-board PDN impedance measurements since the significant contributors werethe interconnects and decoupling capacitors on the FPGA package and die


Conclusions

Low cost alternative to existing PDN design methods

Uses only logic blocks commonly available in any FPGA

Can be implemented in any existing FPGA without theneed of built-in dedicated measurement circuits

Eliminates expensive test bench instruments andsimulation software tools

A case study has exemplified experimental optimizationof decoupling capacitors and has studied various PDNdesign tradeoffs

Documents

Experimental Optimization of Decoupling …...Cosmin Iorga - NoiseCoupling.com - [email protected] 1 DesignCon 2012 Experimental Optimization of Decoupling Capacitors