eGaN® FET PRELIMINARY DATASHEET EPC7014

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EPC7014 – Rad Hard Power TransistorVDS , 60 VRDS(on) , 340 mΩID , 4 A pulse95% Pb / 5% Sn solder

EPC7014 eGaN® FETs are supplied only inpassivated die form with solder bumps. Die size: 0.9 mm x 0.9 mm

Applications • Commercial satellite EPS & avionics• Deep space probes• High frequency Rad Hard DC-DC conversion• Rad Hard motor drives

Features• Ultra high efficiency• Ultra low QG

• Ultra small footprint• Light weight• Total dose – Rated > 1 Mrad• Single event – SEE immunity for LET of 85 MeV/(mg/cm2) with VDS up to 100% of rated breakdow• Neutron

– Maintains Pre-Rad specification for up to 3 x 1015 Neutrons/cm2

EFFICIENT POWER CONVERSIONG

D

S

Maximum Ratings

PARAMETER VALUE UNIT

VDS

Drain-to-Source Voltage (Continuous) 60V

Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 72

ID

Continuous (TA = 25°C) 2.4A

Pulsed (25°C, TPULSE = 300 µs) 4

VGS

Gate-to-Source Voltage 7V

Gate-to-Source Voltage -4

TJ Operating Temperature -55 to 150°C

TSTG Storage Temperature -55 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 7.1

°C/W RθJB Thermal Resistance, Junction-to-Board 25

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 104

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.1 mA 60 V

IDSS Drain-Source Leakage VGS = 0 V, VDS = 60 V 0.0001 0.1 mA

IGSS

Gate-to-Source Forward Leakage VGS = 5 V 0.001 0.5

mAGate-to-Source Forward Leakage# VGS = 5 V, TJ = 125˚C 0.05 1

Gate-to-Source Reverse Leakage# VGS = -3 V 0.05 1.1

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.14 mA 0.8 1.6 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.50 A 240 340 mΩ

VSD Source-Drain Forward Voltage IS = 0.1 A, VGS = 0 V 1.9 V

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

All measurements were done with substrate connected to source.# Defined by design. Not subject to production test.

Rad Hard eGaN® transistors have been specifically designed for critical applications in the high reliability or commercial satellite space environments. GaN transistors offer superior reliability performance in a space environment because there are no minority carriers for single event, and as a wide band semiconductor there is less displacement for protons and neutrons, and additionally there is no oxide to breakdown.

These devices have exceptionally high electron mobility and a low temperature coefficient resulting in very low RDS(on) values. The lateral structure of the die provides for very low gate charge (QG) and extremely fast switching times. These features enable faster power supply switching frequencies resulting in higher power densities, higher efficiencies and more compact designs.

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EPC7014eGaN® FET PRELIMINARY DATASHEET

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

00 0.5 1.0 1.5 2.0 2.5 3.0

I D –

Drai

n Cu

rrent

(A)

Figure 1: Typical Output Characteristics at 25°C

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

R DS(o

n) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 2.5 3.0 3.5 4.0 4.5 5.0

Figure 3: RDS(on) vs. VGS for Various Drain Currents

ID = 0.2 AID = 0.5 AID = 0.8 AID = 1.0 A

800

600

400

200

0

VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

25˚C125˚C

VDS = 3 V

I D –

Drai

n Cu

rrent

(A)

1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

25°C125°C

VDS = 3 V

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.5 3.0 3.5 4.0 4.5 5.0

Figure 4: RDS(on) vs. VGS for Various Temperatures

25°C125°C

ID = 0.5 A

R DS(o

n) –

Drai

n-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V)

800

600

400

200

0

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance#

VDS = 30 V, VGS = 0 V

16 22

pF

CRSS Reverse Transfer Capacitance 0.1

COSS Output Capacitance# 17 26

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 30 V, VGS = 0 V

21

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 26

RG Gate Resistance 12.6 Ω

QG Total Gate Charge VDS = 30 V, VGS = 5 V, ID = 0.5 A 142 184

pC

QGS Gate-to-Source Charge

VDS = 30 V, ID = 0.5 A

43

QGD Gate-to-Drain Charge 25

QG(TH) Gate Charge at Threshold 35

QOSS Output Charge# VDS = 30 V, VGS = 0 V 764 1146

QRR Source-Drain Recovery Charge 0# Defined by design. Not subject to production test.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

#

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EPC7014eGaN® FET PRELIMINARY DATASHEET

All measurements were done with substrate shortened to source.

Capa

citan

ce (p

F)

102

101

100

10-1

10-2

Figure 5b: Capacitance (Log Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

0 20 40 60 10 30 50

5

4

3

2

1

00 20 40 60 80 100 120 140

Figure 7: Gate Charge

V GS –

Gat

e-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (pC)

ID = 0.5 A

VDS = 30 V

Figure 9: Normalized On-State Resistance vs. Temperature

ID = 0.5 A

VGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.0

1.8

1.6

1.4

1.2

1.0

0.80 25 50 75 100 125 150

TJ – Junction Temperature (°C)

Capa

citan

ce (p

F)

0 20 40 60 10 30 50

Figure 5a: Capacitance (Linear Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

40

35

30

25

20

15

10

5

0

Figure 6: Output Charge and COSS Stored Energy

Q OSS

– O

utpu

t Cha

rge (

nC)

E OSS

– C O

SS St

ored

Ener

gy (µ

J)1400

1120

840

560

280

00 20 40 6010 30 50

VDS – Drain-to-Source Voltage (V)

35

28

21

14

7

0

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 8: Reverse Drain-Source Characteristics4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

25°C125°C

VGS = 0 V

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EPC7014eGaN® FET PRELIMINARY DATASHEET

Figure 12: Transient Thermal Response Curves

tp, Rectangular Pulse Duration, seconds

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.2

0.05

0.02

Single Pulse0.01

0.1

Duty Cycle:

Junction-to-Case

PDM

t1

t2

10-510-6 10-4 10-3 10-2 10-1 1

1

0.1

0.01

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

tp, Rectangular Pulse Duration, seconds

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.1

0.2

0.020.05

Single Pulse0.01

Duty Cycle:

Junction-to-Board

PDM

t1

t2

10-5 10-4 10-3 10-2 10-1 1 10

1

0.1

0.01

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

Figure 10: Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.60 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 0.1 mA

0.01

0.001

0.1

1

10

0.1 1 10 100

I D –

Drai

n Cu

rrent

(A)

Limited by RDS(on)

Pulse Width 1 ms 100 μs 10 μs

Figure 11: Safe Operating Area

VDS – Drain Voltage (V)

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EPC7014eGaN® FET PRELIMINARY DATASHEET

DIE MARKINGS

TAPE AND REEL CONFIGURATION4 mm pitch, 8 mm wide tape on 7” reel

7” inch reel Dieorientationdot

Die is placed into pocketsolder bump side down(face side down)

Loaded Tape Feed Direction

a

d

e f

g

h

c

b YYY

Pin 1 is underthis corner

HE

DIM Dimension (mm)EPC7014 (Note 1) Target MIN MAX

a 8.00 7.90 8.30b 1.75 1.65 1.85c (Note 2) 3.50 3.45 3.55d 4.00 3.90 4.10e 4.00 3.90 4.10f (Note 2) 2.00 1.95 2.05g 1.50 1.50 1.60

Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.

Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking Line 2

EPC7014 HE YYY

Die orientation dot

Gate Pad bump is under this corner

HEYYY

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EPC7014eGaN® FET PRELIMINARY DATASHEET

RECOMMENDEDLAND PATTERN (measurements in µm)

DIE OUTLINESolder Bump View(measurements in µm)

Side View

RECOMMENDEDSTENCIL DRAWING (measurements in µm)

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

Pads 1 is Gate;

Pad 3 is Drain;

Pads 2, 4 are Source

The land pattern is solder mask definedSolder mask is 10 μm smaller per side than bump

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Intended for use with SAC305 Type 4 solder, reference 88.5% metals content.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

DIM MIN Nominal MAX

A 870 900 930B 870 900 930c 450 450 450d 450 450 450e 210 225 240f 210 225 240g 187 208 229

Information subject to change without notice.

Revised July, 2021

Seating Plane

87+

/- 17

350+

/- 25

B

A

ce

31

2 4

g

df

Pads 1 is Gate;Pad 3 is Drain;Pads 2, 4 are Source

900

900

450 225

42

1 3

200 +20 / - 10 (*)

X4

242

450

225

* minimum 190

450 225

250

900

900

450

225

R60