ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem

Spring 2014, Feb 21 . . .Spring 2014, Feb 21 . . . ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2014Spring 2014Clock Skew ProblemClock Skew Problem

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html


Single ClockSingle Clock

FF A FF BComb.

CK

Data_in Data_out

CKA

CKA CKB

CKB

Single-cycle path delay


Multiple ClocksMultiple Clocks

FF A FF BComb.Data_in Data_out

CKA

CKA CKB

CKB

Multi-cycle path delay


Clock SkewClock Skew

Skew is the time delay of clock signal at a flip-Skew is the time delay of clock signal at a flip-flop with respect to some time reference.flop with respect to some time reference.

For a given layout each flip-flop has a skew, For a given layout each flip-flop has a skew, measured with respect to a common reference.measured with respect to a common reference.

Skews of flip-flops separated by combinational Skews of flip-flops separated by combinational paths affect the short-path and long-path paths affect the short-path and long-path constraints.constraints.


Skews for Single-Cycle PathsSkews for Single-Cycle Paths

CombinationalBlockDelay:

FFi

CKi

FFj

CKj

si sj

si and sj are arrival times of clock edges w.r.t. a reference time

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)

Delay Latch or D-LatchDelay Latch or D-Latch


D

CK

Q

Q

SR-latch

Setup and Hold Times of LatchSetup and Hold Times of Latch Signals are synchronized with respect to clock (CK).Signals are synchronized with respect to clock (CK). Operation is Operation is level-sensitivelevel-sensitive::

CK = 1 allows data (D) to pass throughCK = 1 allows data (D) to pass through CK = 0 holds the value of Q, ignores data (D)CK = 0 holds the value of Q, ignores data (D)

Setup time Setup time is the interval before the clock transition is the interval before the clock transition during which data (D) should be stable (not change). during which data (D) should be stable (not change). This will avoid any possible race condition.This will avoid any possible race condition.

Hold tiHold time is the interval after the clock transition during me is the interval after the clock transition during which data should not change. This will avoid data from which data should not change. This will avoid data from latching incorrectly.latching incorrectly.


Why Do We Need Setup?Why Do We Need Setup?


D

CK=1Latchopen

Q

Q

SR-latch

Legal inputs are10 or 01 whenLatch closes

Latch InputsLatch Inputs


1

0 time

D

1

0 time

CK

Tr

Ts Th

tp

Tc.Q

Tc.Q : Clock to Q delay

Master-Slave D-Flip-FlopMaster-Slave D-Flip-Flop


D

CK

Q

Q

Master latch Slave latch

Master-Slave D-Flip-FlopMaster-Slave D-Flip-Flop

Uses two level-sensitive clocked D-latches.Uses two level-sensitive clocked D-latches. Transfers data (D) with one clock period delay.Transfers data (D) with one clock period delay. Operation is Operation is edge-triggerededge-triggered::

Negative edge-triggered, CK = 1→0, Q = D (previous Negative edge-triggered, CK = 1→0, Q = D (previous slide)slide)

Positive edge-triggered, CK = 0→1, Q = DPositive edge-triggered, CK = 0→1, Q = D


Negative-Edge Triggered D-Flip-FlopNegative-Edge Triggered D-Flip-Flop


Clock period, Tck

Master openSlave closed

Slave openMaster closedCK

DData can change Data can change

Datastable

Time

Setup time, Ts Hold time, ThTriggering clock edge

Clock-to-Q delay, Tc.Q


Skews for Single-Cycle PathsSkews for Single-Cycle Paths

CombinationalBlockDelay:

FFi

CKi

FFj

CKj

si sj

skews, si and sj are delays from a common clock generator

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)


Short-Path Constraint (Double-Clocking)Short-Path Constraint (Double-Clocking)

CKi

CKj

si

sj

intendedNot intended

Thj

Condition to avoid double clocking: si + Tc.Q + δ(i,j) ≥ sj + Thj

δ(i,j)

Tck


Long-Path Constraint (Zero-Clocking)Long-Path Constraint (Zero-Clocking)

CKj

CKi

si

sj

intended Not intended

Tsj

Condition to avoid zero clocking: si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj

Tc.Q+Δ(i,j)

Tck


Maximum Clock FrequencyMaximum Clock Frequency

Linear program:

Objective function, Minimize Tck

Subject to constraints, for all flip-flop pairs (i,j),

(1) si + Tc.Q + δ(i,j) ≥ sj + Thj short path

(2) si + Tc.Q + Δ(i,j) ≤ sj + Tck – Tsj long path

Effects of ConstraintsEffects of Constraints Short path:Short path:

Independent of clockIndependent of clock Minimum path delay: Minimum path delay: δδ(i,j) ≥ sj – si – Tc.Q + Thj(i,j) ≥ sj – si – Tc.Q + Thj

Long path:Long path: Minimum clock priod: Tck ≥ si – sj + Tc.Q + Minimum clock priod: Tck ≥ si – sj + Tc.Q + ΔΔ(i,j) + Tsj(i,j) + Tsj

Example: Shift register, assume Example: Shift register, assume δδ(i,j) ≈ (i,j) ≈ ΔΔ(i,j) ≈ 0(i,j) ≈ 0 si – sj ≥ Thj – Tc.Q > 0, si > sj for correct operationsi – sj ≥ Thj – Tc.Q > 0, si > sj for correct operation Tck ≥ si – sj + Tc.Q + Tsj, sj > si for maximum speedTck ≥ si – sj + Tc.Q + Tsj, sj > si for maximum speed Clock routed opposite to dataClock routed opposite to data



Shift Register ExampleShift Register Example

FFi

Ci Ri

FFj

Cj Rj

FFk

CkRk

CK

Delay = si sj sk

Delay ≈ 0 Delay ≈ 0

si + Tc.Q – sj ≥ Thj for correct operationTck ≥ si – sj + Tc.Q + Tsj for correct operationTck + si + Tc.Q – sj ≥ si – sj + Tc.Q + Tsj + Thj adding two inequalitiesMaximum clock speed: Tck = Tsj + Thj


Finding Clock SkewsFinding Clock Skews

FFi

CiRi

FFj

CjRj

FFk

CkRk

CK

si

sj

sk

Use Elmore delay formula to calculate si, sj, sk.


Interconnect Delay: Elmore Delay ModelInterconnect Delay: Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with W. Elmore, “The Transient Response of Damped Linear Networks with

Particular Regard to Wideband Amplifiers,” Particular Regard to Wideband Amplifiers,” J. Appl. PhysJ. Appl. Phys., vol. 19, no.1, ., vol. 19, no.1, pp. 55-63, Jan. 1948.pp. 55-63, Jan. 1948.

CKi j

kRi Rj Rk

Ci Cj CkShared resistance:Rii = RiRij = Rji = RiRik = Rki = RiRjj = Ri + RjRjk = Rkj = Ri + RjRkk = Ri + Rj + Rk


Elmore Delay CalculationElmore Delay Calculation

Delay at nodes, sk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )

= 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]

sj = 0.69 [Ri Ci + (Ri + Rj) (Cj + Ck)]

si = 0.69 [Ri (Ci + Cj + Ck)]

ExampleExample


CKi j

k1Ω 1Ω 1Ω

1pF 1pF 1pF

si = 0.69 × 3 ps

sj = 0.69 × 5 ps

sk = 0.69 × 6 ps


Finding Finding δδ(I,j) and (I,j) and ΔΔ(I,j)(I,j)

A1

B3

C1

D2

E1

F1

J1

G2

H3

, -, -

, - 0, 0

, -, -

, -, -

i

j

k

3, 3

, -

, -

4, 4

5, 5

6, 7

6, 8

, -9, 10

Minimum delayMaximum delay


Maximum Clock Frequency for Maximum Clock Frequency for Tolerance Tolerance ±q/2 in Skew±q/2 in Skew

Linear program: Minimize Tck

Subject to: For all flip-flop pairs (i,j),

si + δ(i,j) ≥ sj + Thj + q

si + Δ(i,j) ≤ sj + Tck – Tsj – q

Where q is a constant

si are variables, simin ≤ si

Tck is a variable


Maximum Tolerance for Given Clock Maximum Tolerance for Given Clock FrequencyFrequency

Linear program: Maximize q

Subject to: For all flip-flop pairs (i,j),

si + Tc.Qi + δ(i,j) ≥ sj + Thj + q

si + Tc.Qi+ Δ(i,j) ≤ sj + Tck – Tsj – q

Where Tck, Tc.Qi, Thj and Tsj are constants

si are variables, simin ≤ si

q is a variable


TradeoffsTradeoffs

Increasing clock period Tck

Incr

ea

sing

ske

w to

lera

nce

q

No

so

lutio

n b

eca

use

of

zero

sla

ck.


Clock Skew ProblemClock Skew Problem

N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.

J. P. Fishburn, “Clock Skew Optimization,” J. P. Fishburn, “Clock Skew Optimization,” IEEE IEEE Trans. ComputersTrans. Computers, vol. 39, no. 7, pp. 945-951, , vol. 39, no. 7, pp. 945-951, July 1990.July 1990.

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ELEC 7770 Advanced VLSI Design Spring 2014 Clock Skew Problem