Spring 08, Apr 22 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Mixed-Signal and RF Test Vishwani D. Agrawal James

Spring 08, Apr 22Spring 08, Apr 22 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2008Spring 2008Mixed-Signal and RF TestMixed-Signal and RF Test

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html


Mixed-Signal CircuitsMixed-Signal Circuits Operational amplifier (analog) Programmable gain amplifier (mixed-signal) Filters, active and passive (analog) Comparator (mixed-signal) Voltage regulator (analog or mixed-signal) Analog mixer (analog) Analog switches (analog) Analog to digital converter (mixed-signal) Digital to analog converter (mixed-signal) Phase locked loop (PLL) (mixed-signal)


Wireless Digital RadioWireless Digital Radio

LNA

PA

VGAPhase Splitter

ADC

ADC

Phase Splitter

DAC

DAC

DSP

VGA

Du

ple

xer

LO

LO

LO

0o

0o

90o

90o


Test ParametersTest Parameters DC

Continuity Leakage current Reference voltage Impedance Gain Power supply – sensitivity, common mode rejection

AC Gain – frequency and phase response Distortion – harmonic, intermodulation, nonlinearity, crosstalk Noise – SNR, noise figure


Filter

Analog Test (Traditional)Analog Test (Traditional)

Analog device under test

(DUT)

~

DC

ETC.

DC

RMS

PEAK

ETC.

Stimulus Response


DSP-Based Mixed-Signal TestDSP-Based Mixed-Signal Test

Mixed-signal device under

test (DUT)

A/D RAMRAM D/A

Send memory

Receive memory

Analog Analog

Digital Digital

Synchronization

Digital signal processor (DSP)VectorsVectors

Synthesizer Digitizer

M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, Los Alamitos,California: IEEE Computer Society Press, 1987, pp. 1-14.


Waveform SynthesizerWaveform Synthesizer© 1987 IEEE© 1987 IEEE


Waveform DigitizerWaveform Digitizer© 1987 IEEE© 1987 IEEE


Example: Circuit SpecificationExample: Circuit Specification

Key Performance Specifications: TLC7524CKey Performance Specifications: TLC7524C

8-bit Multiplying Digital-to-Analog Converter8-bit Multiplying Digital-to-Analog Converter

ResolutionResolution 8 Bits8 Bits

Linearity errorLinearity error ½ LSB Max½ LSB Max

Power dissipation at VPower dissipation at VDDDD = 5 V = 5 V 5 mW Max5 mW Max

Settling timeSettling time 100 ns Max100 ns Max

Propagation delay timePropagation delay time 80 ns Max80 ns Max

M. Burns and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement,New York: Oxford University Press, 2001, pp. 23-44.


Voltage Mode OperationVoltage Mode Operation

Data Latches

VO

CS

WR

R R R

R

2R 2R 2R 2R 2R

DB7(MSB)

DB6 DB5 DB0(LSB)

GND

RFB

OUT1

OUT2

Digital data Input

VI

VO = VI (D/256)VDD = 5 VOUT1 = 2.5 VOUT2 = GND

0 1 0 0 011 1

AnalogOutputVoltage

FixedInput

Voltage


Operational/Timing Spec.Operational/Timing Spec.ParameterParameter Test conditionsTest conditions For VDD = 5 VFor VDD = 5 V

Linearity errorLinearity error ±0.5 LSB±0.5 LSB

Gain errorGain errorMeasured using the internal Measured using the internal feedback resistor. Normal full feedback resistor. Normal full scale range (FSR) = Vref – 1 scale range (FSR) = Vref – 1 LSBLSB

±2.5 LSB±2.5 LSB

Settling time to ½ LSBSettling time to ½ LSBOUT1 load = 100 OUT1 load = 100 ΩΩ, , Cext = 13 pF, etc.Cext = 13 pF, etc.

100 ns100 ns

Prop. Delay, digital input to Prop. Delay, digital input to 90% final output current90% final output current 80 ns80 ns

CS

WR

DB0-DB7

tsu(CS) ≥ 40 ns th(CS) ≥ 0 ns

tw(WR) ≥ 40 ns

tsu(D) ≥ 25 ns th(D) ≥ 10 ns


Operating Range Spec.Operating Range Spec.

Supply voltage, VSupply voltage, VDDDD -0.3 V to 16.5 V-0.3 V to 16.5 V

Digital input voltage rangeDigital input voltage range -0.3 V to V-0.3 V to VDDDD+0.3 V+0.3 V

Reference voltage, VReference voltage, Vrefref ±25 V±25 V

Peak digital input currentPeak digital input current 1010μμAA

Operating temperatureOperating temperature -25-25ºC to 85ºCºC to 85ºC

Storage temperatureStorage temperature -65-65ºC to 150ºCºC to 150ºC

Case temperature for 10 sCase temperature for 10 s 260260ºCºC


Test Plan: Hardware SetupTest Plan: Hardware Setup

DACOUT

2.5 V

+Full-scale code

RLOAD

1 kΩ

+Vout

-

VI

D7-D0

VM

+

-

Vo


Test Program PseudocodeTest Program Pseudocode

dac_full_scale_voltage() {

set VI1 = 2.5 V; /* Set the DAC voltage reference to 2.5 V */ start digital pattern = “dac_full_scale”; /* Set DAC output to

+full scale (2.5 V) */ connect meter: DAC_OUT /* Connect voltmeter to DAC output */ fsout = read_meter(), /* Read voltage level at DAC_OUT pin */ test fsout; /* Compare the DAC full scale output to data sheet limit */

}


Analog Fault ModelsAnalog Fault Models

A1 First stage gain R2 / R1

A2 High-pass filter gain R3 and C1

fC1High-pass filter cutoff frequency C1

A3 Low-pass AC voltage gain R4, R5 and C2

A4 Low-pass DC voltage gain R4 and R5

fC2Low-pass filter cutoff frequency C2

Op Amp

High-pass filter

Low-pass filter

amplifier


Bipartite Graph of CircuitBipartite Graph of Circuit

Minimum set of parameters to be observed


Method of ATPG Using SensitivitiesMethod of ATPG Using Sensitivities Compute analog circuit sensitivities Construct analog circuit bipartite graph From graph, find which output parameters

(performances) to measure to guarantee maximal coverage of parametric faults Determine which output parameters are most sensitive

to faults

Evaluate test quality, add test points to complete the analog fault coverage

N. B. Hamida and B. Kaminska, “Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling,” Proc. ITC, 1993.


SensitivitySensitivity Differential (small element variation):

S = × =

Incremental (large element variation):

ρ = ×

Tj – performance parameter

xi – network element

Tj

xi

xi ∂Tj

Tj ∂xi

ΔTj / Tj

Δxi / xi Δ xi → 0

Tj

xi

xi

Tj

ΔTj

Δxi


Incremental Sensitivity Matrix of Incremental Sensitivity Matrix of CircuitCircuit

-0.91

0

0

0

0

0

R1

1

0

0

0

0

0

R2

0

0.58

-0.91

0

0

0

C1

0

0.38

-0.89

0

0

0

R3

0

0

0

-0.96

-0.97

0

R4

0

0

0

0.48

-0.97

-0.88

R5

0

0

0

-0.48

0

-0.91

C2

A1

A2

fc1

A3

A4

fc2


Tolerance Box: Single-Parameter Tolerance Box: Single-Parameter VariationVariation

A1

A2

A4

5% ≤ ≤ 15.98%

5% ≤ ≤ 14.10%

5% ≤ ≤ 20.27%

5% ≤ ≤ 11.60%

5% ≤ ≤ 15.00%

5% ≤ ≤ 15.00%

ΔR1

R1

ΔR2

R2

ΔR3

R3

ΔC1

C1

ΔR4

R4

ΔR5

R5

fC1

fC2

A3

5% ≤ ≤ 14.81%

5% ≤ ≤ 15.20%

5% ≤ ≤ 14.65%

5% ≤ ≤ 13.96%

5% ≤ ≤ 15.00%

5% ≤ ≤ 35.00%

5% ≤ ≤ 35.00%

ΔR3

R3

ΔC1

C1

ΔR5

R5

ΔC2

C2

ΔR4

R4

ΔR5

R5

ΔC2

C2


Weighted Bipartite GraphWeighted Bipartite Graph

Five tests provide most sensitive measurement of all components


IEEE 1149.4 StandardIEEE 1149.4 StandardAnalog Test Bus (ATB)Analog Test Bus (ATB)


Digital/Analog InterfacesDigital/Analog Interfaces

At any time, only 1 analog pin can be stimulated and only 1 analog pin can be read


SummarySummary DSP-based tester has:DSP-based tester has:

Waveform synthesizerWaveform synthesizer Waveform digitizerWaveform digitizer High frequency clock with dividers for synchronizationHigh frequency clock with dividers for synchronization

Analog test methodsAnalog test methods Specification-based functional testingSpecification-based functional testing Model-based analog testingModel-based analog testing

Analog test bus allows static analog tests of Analog test bus allows static analog tests of mixed-signal devicesmixed-signal devices Boundary scan is a prerequisiteBoundary scan is a prerequisite


References: Analog & RF TestReferences: Analog & RF Test A. Afshar, A. Afshar, Principles of Semiconductor Network TestingPrinciples of Semiconductor Network Testing, Boston: Butterworth-, Boston: Butterworth-

Heinemann, 1995.Heinemann, 1995. M. Burns and G. Roberts, M. Burns and G. Roberts, Introduction to Mixed-Signal IC Test and MeasurementIntroduction to Mixed-Signal IC Test and Measurement, , New New

York: Oxford University Press, 2000.York: Oxford University Press, 2000. M. L. Bushnell and V. D. Agrawal, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory Essentials of Electronic Testing for Digital, Memory

and Mixed-Signal VLSI Circuitsand Mixed-Signal VLSI Circuits, Boston: Springer, 2000. Chapters 10, 11 and 17., Boston: Springer, 2000. Chapters 10, 11 and 17. D. Gizopoulos, editor, D. Gizopoulos, editor, Advances in Electronic Testing Challenges and MethodologiesAdvances in Electronic Testing Challenges and Methodologies, ,

Springer, 2006. Chapters 9 and 10.Springer, 2006. Chapters 9 and 10. J. L. Huertas, editor, J. L. Huertas, editor, Test and Design-for-Testability in Mixed-Signal Integrated Test and Design-for-Testability in Mixed-Signal Integrated

CircuitsCircuits, Boston: Springer, 2004., Boston: Springer, 2004. P. Kabisatpathy, A Barua, and S. Sinha, P. Kabisatpathy, A Barua, and S. Sinha, Fault Diagnosis of Analog Integrated CircuitsFault Diagnosis of Analog Integrated Circuits, ,

Springer, 2005.Springer, 2005. R. W. Liu, editor, R. W. Liu, editor, Testing and Diagnosis of Analog Circuits and SystemsTesting and Diagnosis of Analog Circuits and Systems, , New York: New York:

Van Nostrand Reinhold, 1991.Van Nostrand Reinhold, 1991. M. Mahoney, M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal CircuitsDSP-Based Testing of Analog and Mixed-Signal Circuits, , Los Alamitos, Los Alamitos,

California: IEEE Computer Society Press, 1987.California: IEEE Computer Society Press, 1987. A. Osseiran, A. Osseiran, Analog and Mixed-Signal Boundary ScanAnalog and Mixed-Signal Boundary Scan, , Boston: Springer, 1999.Boston: Springer, 1999. T. Ozawa, editor, T. Ozawa, editor, Analog Methods for Computer-Aided Circuit Analysis and Analog Methods for Computer-Aided Circuit Analysis and

DiagnosisDiagnosis, , New York: Marcel Dekker, 1988.New York: Marcel Dekker, 1988. K. B. Schaub and J. Kelly, K. B. Schaub and J. Kelly, Production Testing of RF and System-on-a-Chip Devices for Production Testing of RF and System-on-a-Chip Devices for

Wireless CommunicationsWireless Communications, Boston: Artech House, 2004., Boston: Artech House, 2004. B. Vinnakota, editor, B. Vinnakota, editor, Analog and Mixed-Signal TestAnalog and Mixed-Signal Test, , Upper Saddle River, New Jersey: Upper Saddle River, New Jersey:

Prentice-Hall PTR, 1998.Prentice-Hall PTR, 1998.

Documents

Spring 08, Apr 22 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Mixed-Signal and RF Test Vishwani D. Agrawal James