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Spring 08, Apr 15 Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Ag ELEC 7770: Advanced VLSI Design (Ag rawal) rawal) 1 ELEC 7770 ELEC 7770 Advanced VLSI Design Advanced VLSI Design Spring 2008 Spring 2008 Design for Testability Design for Testability (DFT): Scan (DFT): Scan Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor ECE Department, Auburn University ECE Department, Auburn University Auburn, AL 36849 Auburn, AL 36849 [email protected] [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/ http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/ course.html course.html

Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Design for Testability (DFT): Scan Vishwani D

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Page 1: Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Design for Testability (DFT): Scan Vishwani D

Spring 08, Apr 15Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11

ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI Design

Spring 2008Spring 2008Design for Testability (DFT): ScanDesign for Testability (DFT): Scan

Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor

ECE Department, Auburn UniversityECE Department, Auburn University

Auburn, AL 36849Auburn, AL 36849

[email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html

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Spring 08, Apr 15Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 22

Scan DesignScan Design Circuit is designed using pre-specified design rules.Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design:Test structure (hardware) is added to the verified design:

Add a Add a test controltest control (TC) primary input. (TC) primary input. Replace flip-flops by Replace flip-flops by scan flip-flopsscan flip-flops (SFF) and connect (SFF) and connect

to form one or more shift registers in the test mode.to form one or more shift registers in the test mode. Make input/output of each scan shift register Make input/output of each scan shift register

controllable/observable from PI/PO.controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable Use combinational ATPG to obtain tests for all testable

faults in the combinational logic.faults in the combinational logic. Add shift register tests and convert ATPG tests into scan Add shift register tests and convert ATPG tests into scan

sequences for use in manufacturing test. sequences for use in manufacturing test.

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Scan StructureScan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANIN

TC or TCK Not shown: CK orMCK/SCK feed allSFFs.

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Scan Design RulesScan Design Rules

Use only clocked D-type of flip-flops for all state Use only clocked D-type of flip-flops for all state variables.variables.

At least one PI pin must be available for test; At least one PI pin must be available for test; more pins, if available, can be used.more pins, if available, can be used.

All clocks must be controlled from PIs.All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops.Clocks must not feed data inputs of flip-flops.

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Correcting a Rule ViolationCorrecting a Rule Violation

All clocks must be controlled from PIs.All clocks must be controlled from PIs.

Comb.logic

Comb.logic

D1

D2

CK

Q

FF

Comb.logic

D1

D2CK

Q

FF

Comb.logic

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Scan Flip-Flop (SFF)Scan Flip-Flop (SFF)D

TC

SD

CK

Q

QMUX

D flip-flop

Master latch Slave latch

CK

TC Normal mode, D selected Scan mode, SD selected

Master open Slave opent

t

Logicoverhead

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Level-Sensitive Scan-Design Flip-Flop Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)(LSSD-SFF)

D

SD

MCK

Q

Q

D flip-flop

Master latch Slave latch

t

SCK

TCK

SCK

MCK

TCK No

rmal

mo

de

MCK

TCK Sca

nm

od

e

Logic

overhead

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Adding Scan StructureAdding Scan Structure

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANIN

TC or TCK Not shown: CK orMCK/SCK feed allSFFs.

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Comb. Test VectorsComb. Test Vectors

I2 I1 O1 O2

S2S1 N2N1

Combinational

logic

PI

Presentstate

PO

Nextstate

SCANINTC

SCANOUT

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Combinational Test VectorsCombinational Test Vectors

I2 I1

O1 O2

PI

PO

SCANIN

SCANOUT

S1 S2

N1 N2

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TC

Don’t careor random

bits

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectorsnsff = number of scan flip-flops

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Testing Scan RegisterTesting Scan Register Scan register must be tested prior to application of scan Scan register must be tested prior to application of scan

test sequences.test sequences.

A shift sequence 00110011 . . . of length A shift sequence 00110011 . . . of length nnsffsff+4+4 in scan in scan

mode (TC = 0) produces 00, 01, 11 and 10 transitions in mode (TC = 0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.all flip-flops and observes the result at SCANOUT output.

Total scan test length: Total scan test length: ((nncombcomb + 2) + 2) nnsffsff + + nncombcomb + 4 + 4 clock clock

periodsperiods.. Example: 2,000 scan flip-flops, 500 comb. vectors, total Example: 2,000 scan flip-flops, 500 comb. vectors, total

scan test length ~ 10scan test length ~ 1066 clocks. clocks. Multiple scan registers reduce test length.Multiple scan registers reduce test length.

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Multiple Scan RegistersMultiple Scan Registers Scan flip-flops can be distributed among any Scan flip-flops can be distributed among any

number of shift registers, each having a separate number of shift registers, each having a separate scaninscanin and and scanoutscanout pin. pin.

Test sequence length is determined by the longest Test sequence length is determined by the longest scan shift register.scan shift register.

Just one Just one test controltest control (TC) pin is essential. (TC) pin is essential.

SFFSFF

SFF

Combinationallogic

PI/SCANIN PO/SCANOUTM

UX

CK

TC

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Scan OverheadsScan Overheads IO pins: One pin necessary.IO pins: One pin necessary. Area overhead:Area overhead:

Gate overheadGate overhead = [4 = [4 nnsffsff/(/(nngg+10+10nnffff)] x 100%)] x 100%, where , where nngg = =

comb. gatescomb. gates; ; nnffff = = flip-flopsflip-flops; Example – ; Example – nngg = 100k gates= 100k gates, , nnffff

= 2k = 2k flip-flopsflip-flops, overhead = 6.7%., overhead = 6.7%. More accurate estimate must consider scan wiring and More accurate estimate must consider scan wiring and

layout area.layout area.

Performance overhead:Performance overhead: Multiplexer delay added in combinational path; approx. two Multiplexer delay added in combinational path; approx. two

gate-delays.gate-delays. Flip-flop output loading due to one additional fanout; Flip-flop output loading due to one additional fanout;

approx. 5-6%. approx. 5-6%.

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Hierarchical ScanHierarchical Scan Scan flip-flops are chained within subnetworks Scan flip-flops are chained within subnetworks

before chaining subnetworks.before chaining subnetworks. Advantages:Advantages:

Automatic scan insertion in netlistAutomatic scan insertion in netlist Circuit hierarchy preserved – helps in debugging and Circuit hierarchy preserved – helps in debugging and

design changesdesign changes

Disadvantage: Non-optimum chip layout.Disadvantage: Non-optimum chip layout.

SFF1

SFF2 SFF3

SFF4SFF3SFF1

SFF2SFF4

Scanin Scanout

ScaninScanout

Hierarchical netlist Flat layout

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Optimum Scan LayoutOptimum Scan Layout

IOpad

Flip-flopcell

Interconnects

Routingchannels

SFFcell

TC

SCANIN

SCANOUT

Y

XX’

Y’

Active areas: XY and X’Y’

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Scan Area Scan Area OverheadOverhead

Linear dimensions of active area: X = (C + S) / r X’ = (C + S + aS) / r Y’ = Y + ry = Y + Y(1 – b) / T

Area overhead X’Y’ – XY = ────── x 100% XY 1 – b = [(1+as)(1+ ────) – 1] x 100% T

1 – b = (as + ─── ) x 100% T

y = track dimension, wire width+separationC = total comb. cell widthS = total non-scan FF cell width s = fractional FF cell area = S/(C+S) a = SFF cell width fractional increase r = number of cell rows or routing channels b = routing fraction in active area T = cell height in track dimension y

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Example: Scan LayoutExample: Scan Layout 2,000-gate CMOS chip2,000-gate CMOS chip Fractional area under flip-flop cells, Fractional area under flip-flop cells, s = 0.478s = 0.478 Scan flip-flop (SFF) cell width increase, Scan flip-flop (SFF) cell width increase, = 0.25= 0.25 Routing area fraction, Routing area fraction, = 0.471= 0.471 Cell height in routing tracks, Cell height in routing tracks, T = 10T = 10 Calculated overhead = 17.24%Calculated overhead = 17.24% Actual measured data:Actual measured data:

Scan implementation Area overhead Normalized clock rate______________________________________________________________________

None 0.0 1.00

Hierarchical 16.93% 0.87

Optimum layout 11.90% 0.91

Page 18: Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Design for Testability (DFT): Scan Vishwani D

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ATPG Example: S5378ATPG Example: S5378

Original

2,781 179 0 0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 414

Full-scan

2,781 0 179 15.66% 4,603214/228 99.1% 100.0% 5 s 585105,662

Number of combinational gatesNumber of non-scan flip-flops (10 gates each)Number of scan flip-flops (14 gates each)Gate overheadNumber of faultsPI/PO for ATPGFault coverageFault efficiencyCPU time on SUN Ultra II, 200MHz processorNumber of ATPG vectorsScan sequence length

Page 19: Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Design for Testability (DFT): Scan Vishwani D

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Timing and PowerTiming and Power Small delays in scan path and clock skew can Small delays in scan path and clock skew can

cause race condition.cause race condition. Large delays in scan path require slower scan Large delays in scan path require slower scan

clock.clock. Dynamic multiplexers: Skew between TC and Dynamic multiplexers: Skew between TC and

TC signals can cause momentary shorting of D TC signals can cause momentary shorting of D and SD inputs.and SD inputs.

Random signal activity in combinational circuit Random signal activity in combinational circuit during scan can cause excessive power during scan can cause excessive power dissipation.dissipation.

Page 20: Spring 08, Apr 15 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Design for Testability (DFT): Scan Vishwani D

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Boundary Scan Test LogicBoundary Scan Test Logic

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Instruction Register LoadingInstruction Register Loading

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System View of InterconnectSystem View of Interconnect

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Elementary Boundary Scan CellElementary Boundary Scan Cell

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Serial Boundary ScanSerial Boundary Scan

Other implementations: 1. Parallel scan, 2. Multiple scans.

Ed

ge

con

nec

tor

PCB orMCM

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SummarySummary Scan is the most popular DFT technique:Scan is the most popular DFT technique:

Rule-based designRule-based design Automated DFT hardware insertionAutomated DFT hardware insertion Combinational ATPGCombinational ATPG

Advantages:Advantages: Design automationDesign automation High fault coverage; helpful in diagnosisHigh fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily combined into Hierarchical – scan-testable modules are easily combined into

large scan-testable systemslarge scan-testable systems Moderate area (~10%) and speed (~5%) overheadsModerate area (~10%) and speed (~5%) overheads

Disadvantages:Disadvantages: Large test data volume and long test timeLarge test data volume and long test time Basically a slow speed (DC) testBasically a slow speed (DC) test

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ExercisesExercises What is the main advantage of scan method?What is the main advantage of scan method?

Given that the critical path delay of a circuit is Given that the critical path delay of a circuit is 800ps and the scan multiplexer adds a delay of 800ps and the scan multiplexer adds a delay of 200ps, determine the performance penalty of scan 200ps, determine the performance penalty of scan as percentage reduction in the clock frequency. as percentage reduction in the clock frequency. Assume 20% margin for the clock period and no Assume 20% margin for the clock period and no delay due to the extra fanout of flip-flop outputs.delay due to the extra fanout of flip-flop outputs.

How will you reduce the test time of a scan circuit How will you reduce the test time of a scan circuit by a factor of 10?by a factor of 10?

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AnswersAnswers

What is the main advantage of scan method?What is the main advantage of scan method?Only combinational ATPG (with lower complexity) is used.Only combinational ATPG (with lower complexity) is used.

Given that the critical path delay of a circuit is 800ps and the scan Given that the critical path delay of a circuit is 800ps and the scan multiplexer adds a delay of 200ps, determine the performance penalty multiplexer adds a delay of 200ps, determine the performance penalty of scan as percentage reduction in the clock frequency. Assume 20% of scan as percentage reduction in the clock frequency. Assume 20% margin for the clock period and no delay due to the extra fanout of flip-margin for the clock period and no delay due to the extra fanout of flip-flop outputs.flop outputs.Clock period of pre-scan circuitClock period of pre-scan circuit = 800+160= 800+160 = 960ps= 960psClock period for scan circuitClock period for scan circuit = 800+200+200= 800+200+200 = 1200ps= 1200psClock frequency reductionClock frequency reduction = 100= 100××(1200-960)/1200(1200-960)/1200 = 20%= 20%

How will you reduce the test time of a scan circuit by a factor of 10?How will you reduce the test time of a scan circuit by a factor of 10?Form 10 scan registers, each having 1/10Form 10 scan registers, each having 1/10 thth the length of a single scan the length of a single scan register.register.