EEE ZG512-L2.pptx

7/24/2019 EEE ZG512-L2.pptx

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BITS PilaniK K Birla Goa Campus

Embedded System Design( EEE ZG512)- Lecture 2

9-Aug-215

!eet"# $%$ S"en&yDe't$ & EEE E*I

7/24/2019 EEE ZG512-L2.pptx


BITS PilaniK K Birla Goa Campus

Embedded System -!em&ry

7/24/2019 EEE ZG512-L2.pptx


BITS Pilani, K K Birla Goa Campus

High speed memory design is costly –Complex , support circuitry is also costly

+#c"e

CPU CacheController

Cache

MainMemory

Address

7/24/2019 EEE ZG512-L2.pptx



Average memory access cost with cache <Average

emory access cost without cache

7/24/2019 EEE ZG512-L2.pptx



h hit rate ! pro"a"ility that a given memory location is in cache

#$hmiss rate

tav %htcache &'#$h( tmain

)# $ cache closest to CP*

tav %h#t)#cache & h+t)+cache&'#$h#$h+( tmain

h+$ rate at which access hit the second cache , "ut not the irst cache

A,er#ge #ccess time

7/24/2019 EEE ZG512-L2.pptx



Assume that the system has a two-level cache:

The level-1 cache has a hit rate of 90% and the level- cache has ahit rate of 9!%"

The level 1 cache access time is # ns$ the level cache access time is1ns and access time of main memory is &0 ns"

'hat is the avera(e memory access time)

E#m'.e

7/24/2019 EEE ZG512-L2.pptx

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h# – -./

h+ $ -.# x -./0

tav % h#t)# & h+t)+ & '#$h# $h+(tmain

tav % -./ x 1ns & -.-/0 x #2ns & '#$-./$-.-/0( 3-ns

2.+/2 ns

S&.uti&n

7/24/2019 EEE ZG512-L2.pptx


Memory Address*e(ister +MA*,

Cache

Memory ata*e(ister +M*,

Cache Architecture

3456 7 eetha 8 5henoy

7/24/2019 EEE ZG512-L2.pptx


A (iven desi(n with cache im.lemented has a main memory accesscost of 0 cycles on a miss and cycles on a hit "

The desi(n without the cache has a main memory access cost of 1/cycles "

'hat is the minimum hit rate of the cache to mae the cacheim.lementation worthwhile )

E/ Inc.uding c#c"e &,er"e#d

20+1-, 3 1/Minimum it rate 4 %

Avera(e memory access cost with cache 3Avera(e Memory

access cost without cache

7/24/2019 EEE ZG512-L2.pptx


5et o active locations which CP* is accessing$ 9or:ing

set

Cache Hit

Cache iss – Compulsory miss; Cold iss

– Capacity iss –too large wor:ing set – Conlict iss –ore than one memory location may "e mapped to the same

cache location

7/24/2019 EEE ZG512-L2.pptx


Direct !#''ed +#c"e5loc 0

5loc 1

5loc

5loc 6

5loc 0

5loc 1

5loc

5loc 6

5loc 0

5loc 1

5loc

5loc 6

5loc 0

5loc 1

5loc

5loc 6

5loc 0

5loc 1

5loc

5loc 6

Pa(e0

Pa(e1

Pa(e

Pa(e6

Cache

MainMemory

##456 7 eetha 8 5henoy

7/24/2019 EEE ZG512-L2.pptx


Direct m#''ed c#c"e

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he ollowing data is present in memory as shown "elow.

E#m'.e / Direct !#''ed +#c"e

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


7f the data is read 8y the .rocessor in the followin( order from theaddresses

0000

0001

01001000

how the contents of the cache for direct-ma..ed four line cachewith each read o.eration" The data is read as 8ytes

7/24/2019 EEE ZG512-L2.pptx


Main Memory Address ; # 8its

Cache ; # line

Ta( - 8its

5loc <o" ; 8its

00 01

S&.uti&n

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S&.uti&n

Block Tag Data

00

01

10

11

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


Ater 1st re#d()

Block Tag Data

00 00 =&01

10

11

Cold Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


Ater 2nd re#d (1)

Block Tag Data

00 00 =&

01 00 /

10

11

Cold Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


Attem't 0rd re#d(1)

Block Tag Data00 00 =&

01 00 /

10

11

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


Ater 0rd re#d

Block Tag Data00 01 /!

01 00 /

10

11

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


Ater t" re#d

Block Tag Data

00 10 9101 00 /

10

11

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx


7f the data is read 8y the .rocessor in the followin( order from theaddresses

1001

0001

0101

1101how the contents of the cache for way set associative$ two line

cache after every read o.eration"

r&b.em

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Main Memory Address ; # 8its5loc <o" ; 1 8it

Ta( 6- 8its

000 1

S&.uti&n

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S&.uti&n

Block Tag Data T#g D#t#

0

1

et 0 et 1

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



Ater 1st re#d


0

1 100 A

et 0 et 1

Cold Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



Ater 2nd re#d


0

1 100 A 000 /

et 0 et 1

Cold Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



Ater 0rd re#d

Block Tag Data T#g D#t#0

1 100 A 000 /

et 0 et 1

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



Ater 0rd re#d


0

1 010 & 000 /

et 0 et 1

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D

0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



Ater t" re#d


0

1 100 & 000 /

et 0 et 1

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



Ater t" re#d


0

1 010 & 110 !0

et 0 et 1

Con>ict Miss

0000 F8

0001 56

0010 3A

0011 79

0100 67

0101 8D0110 9B

0111 78

1000 91

1001 AD1010 BC

1011 78

1100 96

1101 70

1110 00

1111 FF

7/24/2019 EEE ZG512-L2.pptx



?east recently used +?*U,Most recently used +M*U,

*andom re.lacement

3e'.#cement &.icy

7ncreases varia8ility of memoryaccess time ;<ot suita8le for safetycritical A..lications

7/24/2019 EEE ZG512-L2.pptx



*niied Cache

=nstruction Cache ; 6ata cache

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>ou are assigned to analy?e a segment o code or an4m"edded 5ystem so as to provide a solution to

improve the perormance. he em"edded system uses

an hierarchical memory organi?ation with single level o

cache. he memory initiali?ations are shown ollowed "ythe code.

r&b.em 5

7/24/2019 EEE ZG512-L2.pptx



int i4 int u6157 u is #n int #rr#y & 15 members u67 t& u617

int ,6157 , is #n int #rr#y & 15 members u67 t& u617

int 8607

int 67

int y657

int 4

&r (i4 i:15 i;;)

<

4; u6i7=,6i7 !u.ti'.y #nd Accumu.#te >

@int reers to + "it data. he varia"les i, ? are stored in registers where

as the int arrays u, v, w, x, y is mapped to A'ain memory(.

7/24/2019 EEE ZG512-L2.pptx



!#in !em&ry/ he main memory is "yte organi?ed ie ,each int ta:es our

locations in main memory. he page in main memory starts with u array and gets

illed according to the array initiali?ation . Assume that there is no compiler

optimi?ation.

+#c"e !em&ry/ A direct$mapped cache with a si?e o D1 Bytes and a "loc: si?e o

#D Bytes is used. he varia"le uE-F is mapped to the rst word o cache line -. 9hen

a memory access is perormed and on a cache miss, data rom main memory is

copied to the cache as "loc:s, ie the entire "loc: in main memory o the particular

page is copied to "loc: in cache.4g uE-F is accessed the entire "loc: within the same

page in main memory is copied to cache. eplacement rom cache also happens as

"loc:s. Assume uEiF is accessed "eore vEiF or the execution o ?%?&uEiFIvEiF!

7/24/2019 EEE ZG512-L2.pptx



a( Jind the Hit rate o cache

"( 5uggest a modiication to improve the perormance o

cache. Hardware or the same is inali?ed hence only

modiication in sotware is possi"le .

7/24/2019 EEE ZG512-L2.pptx


U[0)

U(1)

U(2)

U(3)

U(4)

U(5)

U(6)U(7)

U(8)

U(9)

U(10)

U(11)

U(12)

U(13)

U(14)

V(0)

V(1)

V(2)

V(3)

V(4)

V(5)

V(6)

V(7)V(8)

V(9)

V(10)

V(11)

V(12)

V(13)

V(14)

W(0)

W(1)

Page 0 Page 1 Cache

U[12)

U(13)

U(14)

V(0)

U[0)

U(1)

U(2)

U(3)

V[1)

V(2)

V(3)

V(4)

U[0)

U(1)

U(2)

U(3)

V[1)

V(2)

V(3)

V(4)

U[0)

U(1)

U(2)

U(3)

U[4)

U(5)

U(6)U(7)

V[1)

V(2)

V(3)

V(4)

V[1)

V(2)

V(3)

V(4)

U[0)

U(1)

U(2)

U(3)

V[1)

V(2)

V(3)

V(4)

V[5)

V(6)

V(7)V(8)

U(8)

U(9)

U(10)

U(11)

U[4)

U(5)

U(6)U(7)

U[4)

U(5)

U(6)U(7)

V[5)

V(6)

V(7)V(8)

U[4)

U(5)

U(6)U(7)

V[5)

V(6)

V(7)V(8)

V(9)

V(10)

V(11)

V(12)

V(9)

V(10)

V(11)

V(12)

U(8)

U(9)

U(10)

U(11)

V(9)

V(10)

V(11)

V(12)

U(8)

U(9)

U(10)

U(11)

U(8)

U(9)

U(10)

U(11)

V(9)

V(10)

V(11)

V(12)

U(8)

U(9)

U(10)

U(11)

V(9)

V(10)

V(11)

V(12)

u@0-missu@1-hit

u@-missu@6-missu@#-missu@-hitu@/-missu@!-missu@&-missu@9-hitu@10-missu@11-

missu@1-hit

v@0-missv@1-missv@-miss

@6-missv@#-hitv@-missv@/-missv@!-missv@&-hitv@9-missv@10-missv@11-missv@1-hitv@16-missv@1#-miss

7/24/2019 EEE ZG512-L2.pptx



'rite throu(h'rite 8ac

irty 8it

7/24/2019 EEE ZG512-L2.pptx


Advantage o =ntroducing Cache emory

=mproving Cache hit via cache mapping schemes

=mproving Cache hit via optimal programming

Discussi&n &cus

456 7 th 8 5h /

Documents

EEE ZG512-L2.pptx