Embed Size (px)
Citation preview
Lecture 1 (Introduction) Lecture 1 (Introduction)
Why is designing digital ICs different today than it was before?
Will it change in future?
The First ComputerThe First Computer
The BabbageDifference Engine(1832)
25,000 partscost: £17,470
ENIAC - The first electronic computer (1946)ENIAC - The first electronic computer (1946)
The Transistor RevolutionThe Transistor Revolution
First transistorBell Labs, 1948
The First Integrated Circuits The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
Intel 4004 Micro-ProcessorIntel 4004 Micro-Processor
19711000 transistors1 MHz operation
Intel Pentium (IV) microprocessorIntel Pentium (IV) microprocessor
Moore’s LawMoore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months
Moore’s LawMoore’s Law
161514131211109876543210
195
9
196
0
196
1
196
2
196
3
196
4
196
5
196
6
196
7
196
8
196
9
197
0
197
1
197
2
197
3
197
4
197
5
LO
G 2 O
F T
HE
NU
MB
ER
OF
CO
MP
ON
EN
TS
PE
R I
NT
EG
RA
TE
D F
UN
CT
ION
Electronics, April 19, 1965.
Evolution in ComplexityEvolution in Complexity
Transistor CountsTransistor Counts
1,000,000
100,000
10,000
1,000
10
100
11975 1980 1985 1990 1995 2000 2005 2010
8086
80286i386
i486Pentium®
Pentium® Pro
K1 Billion 1 Billion
TransistorsTransistors
Source: IntelSource: Intel
ProjectedProjected
Pentium® IIPentium® III
Courtesy, Intel
Moore’s law in MicroprocessorsMoore’s law in Microprocessors
40048008
80808085 8086
286386
486Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tra
nsi
sto
rs (
MT
)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years
Courtesy, Intel
Die Size GrowthDie Size Growth
40048008
80808085
8086286
386486 Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
FrequencyFrequency
P6Pentium ® proc
486386
28680868085
8080
80084004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Fre
qu
ency
(M
hz)
Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
Power DissipationPower Dissipation
P6Pentium ® proc
486
3862868086
80858080
80084004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Po
wer
(W
atts
)
Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase
Courtesy, Intel
Power will be a major problemPower will be a major problem
5KW 18KW
1.5KW 500W
40048008
80808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Po
wer
(W
atts
)
Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive
Courtesy, Intel
Power densityPower density
400480088080
8085
8086
286386
486Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Po
wer
Den
sity
(W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp
Courtesy, Intel
Not Only MicroprocessorsNot Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband
(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
CellPhone
MOS Transistor ScalingMOS Transistor Scaling(1974 to present)(1974 to present)
Scaling factor s=0.7 per node (0.5x per 2 nodes)
Metal pitch Technology Nodeset by 1/2 pitch(interconnect)
Gate length(transistor)
Poly width
Ideal Technology Scaling (constant fieldIdeal Technology Scaling (constant field))
Quantity Before Scaling After Scaling
Channel Length L L’ = L * s
Channel Width W W’ = W * s
Gate Oxide thickness tox t’ox = tox * s
Junction depth xj x’j = xj * s
Power Supply Vdd Vdd’ = Vdd * s
Threshold Voltage Vth V’th = Vth * s
Doping Density, p n+
NA ND
NA’ = NA / s ND’ = ND / s
Challenges in Digital DesignChallenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
DSM 1/DSM
?
Productivity TrendsProductivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
200
3
198
1
198
3
198
5
198
7
198
9
199
1
199
3
199
5
199
7
199
9
200
1
200
5
200
7
200
9
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Logic Tr./ChipTr./Staff Month.
xxx
xxx
x
21%/Yr. compoundProductivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Lo
gic
Tra
nsi
sto
r p
er C
hip
(M)
0.01
0.1
1
10
100
1,000
10,000
100,000
Pro
du
ctiv
ity
(K)
Tra
ns.
/Sta
ff -
Mo
.
Source: Sematech
Complexity outpaces design productivity
Co
mp
lexi
ty
Courtesy, ITRS Roadmap
Why Scaling?Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
Cost of a function decreases by 2x But …
How to design chips with more and more functions? Design engineering population does not double every
two years… Hence, a need for more efficient design methods
Exploit different levels of abstraction
Design Abstraction LevelsDesign Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
Design MetricsDesign Metrics
How to evaluate performance of a digital circuit (gate, block, …)? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function
Cost of Integrated CircuitsCost of Integrated Circuits
NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor
Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area
NRE Cost is IncreasingNRE Cost is Increasing
Die CostDie Cost
Single die
Wafer
From http://www.amd.com
Going up to 12” (30cm)
Cost per TransistorCost per Transistor
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢-per-¢-per-transistortransistor
Fabrication capital cost per transistor (Moore’s law)
What about InterconnectWhat about Interconnect
Global wires Non-scalable delay Delay exceeds one clock cycle
Non-scalable interconnects Excessive power dissipation Non reliability in signal transmission
Lower Latency and Energy Dissipation
Three Dimensional Integration
Optical Interconnects Wireless/RF Interconnects
Emerging Interconnect TechnologiesEmerging Interconnect Technologies
SummarySummary Digital integrated circuits have come a long
way and still have quite some potential left for the coming decades
Some interesting challenges ahead Getting a clear perspective on the challenges and
potential solutions is the purpose of this course Understanding the design metrics that govern
digital design is crucial Cost, reliability, speed, power and energy
dissipation
Course StructureCourse Structure MOS Transistors MOS Inverter Circuits Static MOS Gate Circuits High-Speed CMOS Logic Design Transfer Gate and Dynamic Logic Design Semiconductor Memory Design Advanced Devices beyond CMOS
Course StructureCourse Structure
Extensive use of CAD tools Homework assignments One to two midterm exams and one
final exam Course Project
Suite of two courses EE 466/586 and EE587 will cover various aspects starting from circuits to systems
ReferencesReferences Textbook:
CMOS VLSI Design, Weste and Harris, Fourth Edition Additional Reference:
Analysis and Design of Digital Integrated Circuits - In Deep Submicron Technology, Hodges, Jackson and Saleh, McGraw-Hill, Third Edition, 2004.
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective. Second Edition, Prentice Hall, 2003.
Important announcements will be posted in the course website www.eecs.wsu.edu/~ee586
