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Multiplexers
2:1 multiplexer chooses between two inputs
X11
X01
1X0
0X0
YD0D1S
0
1
S
D0
D1Y
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Multiplexers
2:1 multiplexer chooses between two inputs
1X11
0X01
11X0
00X0
YD0D1S
0
1
S
D0
D1Y
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Gate-Level Mux Design
How many transistors are needed?
1 0 (too many transistors)Y SD SD= +
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Gate-Level Mux Design
How many transistors are needed? 20
1 0 (too many transistors)Y SD SD= +
44
D1
D0
S Y
4
2
22 Y
2
D1D0S
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Transmission Gate Mux
Nonrestoring mux uses two transmissiongates
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Transmission Gate Mux
Nonrestoring mux uses two transmissiongates
Only 4 transistorsS
S
D0
D1YS
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Inverting Mux
Inverting multiplexer
Use compound AOI22Or pair of tristate invertersEssentially the same thing
Noninverting multiplexer adds an inverter
SD0 D1
Y
S
D0
D1Y
0
1S
Y
D0D1
S
S
S
S
S
S
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4:1 Multiplexer
4:1 mux chooses one of 4 inputs using twoselects
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4:1 Multiplexer
4:1 mux chooses one of 4 inputs using twoselects
Two levels of 2:1 muxesOr four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
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D Latch
When CLK = 1, latch is transparent Q follows D (a buffer with a Delay)
When CLK = 0, the latch is opaque Q holds its last value independent of D
a.k.a. transparent latch or level-sensitive latch CLK
D Q L a t c h D
CLK
Q
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D Latch Design
Multiplexer chooses D or old Q
10
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
Old Q
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D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
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D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its valuea.k.a. positive edge-triggered flip-flop , master- slave flip-flop
F l o p
CLK
D Q
D
CLK
Q
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D Flip-flop Design
Built from master and slave D latches
QMCLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
L a t c h
L a t c h
D QQM
CLK
CLK
A “negative level-sensitive” latch A “positive level-sensitive” latch
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D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QM Q
D
CLK
Q
Inverted version of D
Q -> NOT(NOT(QM))
Holds the last value of NOT(D)
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Race Condition
Back-to-back flops canmalfunction from clock skew
Second flip-flop fires EarlySees first flip-flop changeand captures its resultCalled hold-time failure or
race condition
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Nonoverlapping Clocks
Nonoverlapping clocks can prevent racesAs long as nonoverlap exceeds clock skew
Good for safe designIndustry manages skew more carefully instead
φ1
φ1φ1
φ1
φ2
φ2φ2
φ2
φ2
φ1
QMQD
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Gate Layout
Layout can be very time consumingDesign gates to fit together nicelyBuild a library of standard cellsMust follow a technology rule
Standard cell design methodologyVDD and GND should abut (standard height)Adjacent gates should satisfy design rulesnMOS at bottom and pMOS at topAll gates include well and substrate contacts
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Example: Inverter
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Inverter, contd..
Layout using Electric
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Example: NAND3
Horizontal N-diffusion and p-diffusion stripsVertical polysilicon gates
Metal1 V DD rail at topMetal1 GND rail at bottom32 λ by 40 λ
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NAND3 (using Electric), contd.
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Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scaleDraw with color pencils or dry-erase markers
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Stick Diagrams
Stick diagrams help plan layout quicklyNeed not be to scaleDraw with color pencils or dry-erase markers
Vin Vout
VDD
GND
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Wiring Tracks
A wiring track is the space required for a wire
4 λ width, 4 λ spacing from neighbor = 8 λpitchTransistors also consume one wiring track
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Well spacing
Wells must surround transistors by 6 λImplies 12 λ between opposite transistor flavorsLeaves room for one wire track
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Area Estimation
Estimate area by counting wiring tracksMultiply by 8 to express in λ
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Example: O3AI
Sketch a stick diagram for O3AI and estimate area
DC B AY •++= )(
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Example: O3AI
Sketch a stick diagram for O3AI and estimate areaDC B AY •++= )(
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Example: O3AI
Sketch a stick diagram for O3AI and estimate area DC B AY •++= )(
