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 7.1 EXPERIMENT 7: HAZARDS AND GLITCHES PURPOSE The purpose of this experiment is to consider the effect of glitches, caused by hazards, in asynch ronous sequent ial ci rcuits. In synch ronous sequential circuits, most of the glitches that may occur do not cause problems because they occur in the part of the clock cycle where they do not affect the fl ip-fl ops. (In order for t his to be the case, the length of clock peri od must be of proper length.) However, in asyn chronous sequential circuits (such as the in ternal operation of clocked flip-flops) glitches can affect signals on the feedback loops and cause the circuit to enter an in correct state. HAZARDS IN ASYNCHRONOUS SEQUENTIAL CIRCUITS Assume that a Boolean function, F, can be expressed as a sum of two product terms, F1 and F2. Both these terms might be functions of the same logical variable, A, the value of which is changing. Let the value of A bef ore the change be denoted by A and, after the change, by A*. Consider the expressions: F(A) = F1(A) + F2(A) F(A*) = F1(A*) + F2(A*) A static-1 hazard exits if F1(A)=0 and F2(A)=1, but F1(A*)=1 and F2(A*)=0. In other words, if the value of the Boolean expression F before and after the change is 1, but the 1 is caused by two diff erent pro duct t erms that change due to t he change in A . In the circui t impl ementin g F, the gat e and wire delays may be such that F1 and F2 are simultaneously 0. This wil l cause F to become 0 for a short time, in which case, the static-1 hazard in the function results in a glitch in the circuit. In general, a hazard is the possib ili ty of an unwan ted tr ansient (spike or gli tch). In a particular circuit implementing the function, a glitch may or may not occur depending the actual delays in the circuit . An exam ple of a h azar d in an asynchronous sequent ial ci rcuit is given i n Example 1. Example 1: The circuit shown in Figure 7.1 illustrates a hazard in an asynchronous sequential circuit. Also, it i llustrates the use of a Karnaugh map for iden tify ing a static-1 h azard. (In this notation y is the present state and Y is the next state.) The timing diagram in Figure 7.1(c) is supported by the following discussion: Assume at t=0-, X1X2y = 111; Since Y=X1X2' + X2y = 1.0 + 1.1 = 1, the circuit is stable. Then at t=0, X2 changes from 1 -> 0;

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