EE 4271 VLSI Design, Fall 2011 Static Timing Analysis and Gate Sizing Optimization

EE 4271 VLSI Design, Fall 2011

Static Timing Analysis and Gate Sizing Optimization

Delay Evaluation

• 1. Gate delay• 2. Interconnect delay

2023.04.18 Circuit Delay PJF- 2

Circuit Model

• For an inverter


Csink

Csink

…

…

Gate Resistance

• Pull-up and pull-down resistors are not a constant. Which value should we choose?

• Gate delay also depends on its input signal


K-Factor Gate Delay• More accurate than RC• Consider input transition time tr (transition rising time) or tf

(transition falling time)• Transition time is signal rising/falling time from 10% to 90%• K-factor equation

– Delay td=k(tr/f, Ctotal)– Output transition time t’r/f=k’(tr/f, Ctotal)

• Synopsis K-factor form: – Delay= a*tr+b*Ctotal+c*tr*Ctotal+d– Obtained from SPICE simulation

• Widely used


rising time

Circuit Delay Evaluation - Two Components

• Cell delay + interconnect delay– Cell delay is computed using RC– Interconnect delay is computed using Elmore

delay


Cell CellInterconnect

Wire and Gate Models

7

l

hB

r l

h0

rB

c h l( )

2c h l( )

2

CB

Step by Step


Model combinational circuit using the previous slideModel combinational circuit using the previous slide Starting from primary input gates, compute the Starting from primary input gates, compute the

arrival time (AT) at each gate, i.e., compute gate arrival time (AT) at each gate, i.e., compute gate delay and interconnect delaydelay and interconnect delay

In order to compute the AT at a gate, the ATs of all In order to compute the AT at a gate, the ATs of all its input gates need to be computedits input gates need to be computed

Repeat the above process until the ATs at all primary Repeat the above process until the ATs at all primary output gates are computedoutput gates are computed

Example of Static Timing Analysis

• Arrival time (AT): input -> output, take max 2023.04.18 Circuit Delay PJF- 9

C=1,R=1

C=5,R=2

C=5,R=2

C=4,R=2 C=10,R=5

unit wire resistance=1unit wire capacitance=1

10

2

2

12

2AT=0

AT=267AT=75

AT=145

AT=22

AT=31

AT=0

AT=121

AT=21

AT=167

AT=267

AT=12Take the

MaxAT=31

1

3

2

4

5

Timing Optimization

• Arrival time (AT): input -> output, take max 2023.04.18 Circuit Delay PJF- 10

Should we size up this gate to improve timing?

C=1,R=1

C=5,R=2

C=5,R=2

C=4,R=2 C=10,R=5


10

2

2

12

2AT=0

AT=267AT=75

AT=145

AT=22

AT=31

AT=0

AT=121

AT=21

AT=167

AT=267

AT=12Take the

MaxAT=31

Timing Optimization- II• Suppose that we have a gate (with same gate

type) doubling its width. We roughly have C=10, R=1.

• If we change the gate with this new one, what is the new delay? Does not change


C=1,R=1

C=10,R=1

C=5,R=2

C=4,R=2 C=10,R=5


10

2

2

12

2AT=0

AT=267AT=75

AT=145

AT=16

AT=31

AT=0

AT=121

AT=21

AT=167

AT=267

AT=6Take the

MaxAT=31

Timing Optimization- III• Suppose that we have a gate (with same gate

type) doubling its width. We roughly have C=8, R=1.

• If we change the gate with this new one, what is the new delay?


C=1,R=1

C=5,R=2

C=5,R=2

C=8,R=1 C=10,R=5


10

2

2

12

2AT=0

AT=257AT=65

AT=149

AT=38

AT=43

AT=0

AT=125

AT=25

AT=171

AT=257

AT=20Take the

MaxAT=43

Gate Sizing• This optimization is called gate sizing. Change the

gate size (width) in optimization.• 1. Given multiple choices (implementations) per

gate type, find a gate implementation at each gate such that the circuit timing is minimized.

• 2. Given multiple choices per gate type, find a gate implementation at each gate such that the circuit timing satisfies the target and the total gate area/power is minimized– This formulation is widely used.


Delay due to Gate Sizing

• Suppose that unit width gate capacitance is c and unit width gate resistance is r. Given gate size wi,

– Gate size wi: R r/wi, C cwi

• Delay is a function of RC– Delay RiCj wi/wj

14

Combinatorial Circuit Model

• Gate size variables x1, x2, x3

• Delay on each gate depends on x

15

Drivers Loads

x2x3

x1 a3

a4a5

a1

a2

D1

D3

D2D5

D4

D7

D6

D9D8D10

a6

a7

Path Delay

• Express path delay in terms of component delay

• A component can be a gate or a wire

• Delay D for each component

• Arrival time a for some components

16

7105

5984

5973

663

4532

3422

3411

aDa

aDDa

aDDa

aDa

aDDa

aDDa

aDDa

Gate Sizing

• Power/area minimization under delay constraints:

• This can be solved efficiently using gpsolve

17

gateeach on sizelargest andsmallest

)( and

target timing theis output,primary Subject to

Minimize1

iUxL

iinputjiaDa

AjAa

x

iii

iij

maxmaxj

n

i ii

Gate Sizing using GPSOLVE

• Follow the steps in gatesizing.m for the example in the slides of timing analysis and optimization

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Documents

EE 4271 VLSI Design, Fall 2011 Static Timing Analysis and Gate Sizing Optimization