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EDA Tool CookbookJun Chen
Version 0.0.2 from 07/17/2017
Abstract
This document includes EDA tool experiences. The content is branched out from Report Collection, so thatthe original file compiling time is reduced.
Revision History
Revision Date Author(s) Description0.0.1 06/22/2017 Junc Branch out from Report Collection v0.0.630.0.2 07/17/2017 Junc Added Verilog-A
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Contents1 HSPICE 5
1.1 HSPICE Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2 Hspice Basic Topic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 Useful Spice Code Piece . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4 Advanced Topic 1: Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.5 Advanced Topic 2: Measure Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.6 Advanced Topic 3: Option Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.7 Advanced Topic 4: Optimization Process (DC Analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . 121.8 Advanced Topic 5: Optimization Process (Transient Analysis) . . . . . . . . . . . . . . . . . . . . . . . 141.9 Advanced Topic 6: AC analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9.1 Analyze Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.10 Advanced Topic 7: S-parameter files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.10.1 Hspice Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161.10.2 Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Matlab Simulink 182.1 Matlab Tricks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2 Simulink Tricks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Virtuoso Simulation Usage 213.1 Virtuoso Simulation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.2 Virtuoso Mix signal simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1 Import Spice Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263.3 Make use of finfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.4 Write out different signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.5 Write out phase and amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Verilog-A / Verilog-AMS Introduction 304.1 Basic Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.2 Time operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324.3 Example in verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334.4 Syntax Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.5 Synthesis Simulation Verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344.6 Useful Verilog-A resource: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5 ModelSim for Gate Level 37
6 Gate Level with VCS 40
7 Verilog Basic Introduction 417.0.1 Delay and advanced modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.1 Verilog Note II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447.1.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447.1.2 Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447.1.3 Auto generate verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.1.4 System call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.1.5 Synthesis-able Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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8 VHDL 478.1 Basic Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478.2 Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478.3 Logic value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488.4 process, function, procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488.5 Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.6 Build in function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.7 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498.8 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9 nWave Usage 51
10 NanoSim Simulation 54
11 V2LVS Conversion Verilog and Spice 55
12 VCS Mix Signal Simulation 5512.1 VCS Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.1.1 Basic Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5612.1.2 VCS NanoSim Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.2 CustomSim XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5712.3 VCS with verilog-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
13 Python development 6113.1 Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.1.1 Automatic run programs in windows, API COM level . . . . . . . . . . . . . . . . . . . . . . . 6113.1.2 Automatic run programs in windows, GUI level . . . . . . . . . . . . . . . . . . . . . . . . . . . 6113.1.3 Automatic run programs in windows, Key-mouse level . . . . . . . . . . . . . . . . . . . . . . . 6113.1.4 Prerequriements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6113.1.5 Automatic run browser in windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6113.1.6 Other automation tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.2 File access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14 Web development 6214.1 Setup process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6214.2 Django operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6214.3 PHP-Python development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6314.4 CONCLUSION: Server script is blocked! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6314.5 chrome debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6314.6 Markdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
15 Unix 6515.1 Shell experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6615.2 Update Unix Utility Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6715.3 TexStudio Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7015.4 Putty Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7015.5 Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16 Git Development 7116.1 Background of git . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.1.1 Difference between git and perforce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7116.1.2 git configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7216.1.3 Basic usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7416.1.4 Branch maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
16.2 git hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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16.2.1 Core git setup flow: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7616.2.2 Github useful commands: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7616.2.3 Sync fork from original branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
16.3 Git lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7816.4 Basic usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
17 Environment Experiences 7917.1 Python in windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7917.2 gvim in windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7917.3 mail and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7917.4 Excel Statistical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8017.5 Webex usage experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
18 Latex format 8318.1 IEEE conference experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19 JUNC Utility 8519.1 Latex checker core engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8519.2 Mail based latex checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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1 HSPICE1.1 HSPICE SimulationEnvironment setup. Before run hspice or cscope, user need to:
source /eda/ synopsys . shsource /eda/ cscope . shsource /eda/eda . sh
1.2 Hspice Basic TopicTo kick-off hspice, run
hsp i c e f i le_name . sp
Below files are useful for investigation:
• .ps main simulation file used by hspice.
• .tr0 waveform file which can be used by CosmosScope.
• .mt0 measure result file, to dump power/current result.
The *.tr0 file is generated waveform file. User can check the output waveform by executing
cscope f i l e . t r0
Figure 1: CosmosScope waveviewer
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Unit of HSpice is shown in below table
unit name sizea atto 10−18
f femto 10−15
p pico 10−12
n nano 10−9
u micro 10−6
m mili 10−3
k kilo 103 (not l !!!)x mega 106
g giga 109
AC Sweeping Before running s-parameter, we need to understand AC related codes:
.AC DEC 10 1K 100MEG
.AC LIN 100 1 100HZ
This example performs a frequency sweep by 10 points per decade from 1kHz to 100MHz, and This example runs a100-point frequency sweep from 1- to 100-Hz.
A basic ac noise demo displayed in below, the output file is .ac0, which will show the db and phase BoadDiagram
*A SIMPLE AC RUN.OPTION LIST NODE POST.OP.AC DEC 10 1K 1MEG.PRINT AC V(1) V(2) I (R2) I (C1)* smal l vo l t age s i g n a lV1 1 0 10 AC 1* or use t h i s AC/DC source :* V1 1 Vin dc 10* Vin Vin 0 av 1
R1 1 2 1KR2 2 0 1KC1 2 0 .001U.END
The related model. With 10V DC and 1V AC
Figure 2: RC model demo ac analysis
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MOS Definition in Hspice The Hspice use below syntax to model a CMOS/PMOS:
Mxxx nd ng ns <nb> mname <<L=>length> <<W=>width>+ <AD=val> AS=val> <PD=val> <PS=val>+ <NRD=val> <NRS=val> <RDC=val> <RSC=val> <OFF>+ <IC=vds , vgs , vbs> <M=val> <DTEMP=val>+ <GEO=val> <DELVTO=val>
According to the syntax, the PMOS and NMOS should be connected with caution. Typical schematic view of PMOSand NMOS is shown in below figure. The drain and source node is different.
Figure 3: Schematic of NMOS
Example usage located in: "/vlsilab/j-chen/hspice_case/junc_converter/murata_mos/parameter_testing".The option definition is shown in below table. Note, if user wants to modify threshold voltage, the model source fileshould be changed (find keyword ’vth’):
Parameter DescriptionMxxx MOSFET element name.nd Drain terminal node name.ng Gate terminal node name.ns Source terminal node name.nb Bulk terminal node name, optional.mname MOSFET model nameL MOSFET channel length, in meters.W MOSFET channel width, in meters.AD Drain diffusion area.AS Source diffusion area.PD Perimeter of drain junction, including channel edge.PS Perimeter of source junction, including channel edge.NRD Number of squares of drain diffusion for resistance calculations.NRS Number of squares of source diffusion for resistance calculations.RDC Additional drain resistance due to contact resistance, in ohms.RSC Additional source resistance due to contact resistance, in ohms.OFF Sets initial condition for this element to OFF, in DC analysis.IC=vds, vgs,vbs Initial voltage across external drain and source (vds).M Multiplier, to simulate multiple MOSFETs in parallel. Default=1.DTEMP The difference between element and circuit temperature in Celsius. Default=0.0.GEO Source/drain sharing selector for a MOSFET model parameter.DELVTO Zero-bias threshold voltage shift. Default=0.0.
Table 2: HSpice Mos Transistor Options
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Commonly Used Syntax and Elements shown in below table.
Syntax DescriptionMxxx MOSFET. Mxxx nd ng ns <nb> mname (e.g. Mopamp1 d1 g3 s2 b model1 L=2u W=10u)Rxxx Resistance. Rxxx n1 n2 Rval. (e.g. Rterm input gnd R='sqrt(HERTZ)')Cxxx Capacitor. Cxxx n1 n2 Cval.(e.g. C1 1 2 C='1e-6 - HERTZ/1e16' )Lxxx Inductor. Lxxx n1 n2 Lval. (e.g. Lcoil input gnd L='1u*i(input)')Kxxx Inductor. Lxxx n1 n2 Lval. (e.g. Kcoil input gnd L='1u*i(input)') multure parasitic inductor.Dxxx Diode. Dxxx PinPlus PinMinus mname. (e.g. D1 1 2 diode1)Qxxx Bipolar Junction Transistor (BJT) Qxxx nc nb ne mnameVxxx Independent voltage source (e.g. VIN 13 2 0.001 AC 1 SIN (0 1 1MEG))(1-volt AC use sin description)Ixxx Independent current source (e.g. I1 n1 n2 PL(1MA 0S 5MA 25MS) )Pxxx Port (e.g. P1 in gnd port=1 z0=50 )Exxx Voltage-controlled voltage source (VCVS) (e.g. an inverter Einv out 0 PWL(1) in 0 .7v,5v 1v,0v)Fxxx Current-controlled current source (CCCS)Gxxx Voltage-controlled current source/r/cap (VCCS) Gxxx n+ n- <VCCS VCR VCCAP> in+ in-Gxxx Voltage-controlled MOS (VCCS) Gxxx n+ n- <NPWL PPWL> in+ in-Hxxx Current-controlled voltage source (CCVS)
Table 3: Hspice Element Syntax
Commonly Used Functions shown in below table.
Syntax Descriptionpulse pulse( v1 v2 td tr tf pulse-width period )sin VIN 13 GND DC=0.5 AC=SIN (0 1.2 50MEG 1ns 10000000) damping sinPL / PWL PWL(t1 v1 t2 v2 t3 v3⋯) while PL (v1 t1 v2 t2 v3)POLY(i) Polynomial Functions
Table 4: Hspice Element Syntax
1.3 Useful Spice Code PiecePulse in HSPICE is defined by:
Pulse v1 v2 td t r t f pw per iodexample : VIN nc lk VSS pu l s e 0 0 .8 1n 1p 1p 500p 1n
Where pw is pulse width, td is pulse start(rising time), tr and tf is rising and fulling transition time respectively.
Data driven input used in PWL and optimization.
. opt ions l i s t node postV1 1 0 PWL(TIME, pv1 )R1 1 0 1V2 2 0 PWL(TIME, pv2 )R2 2 0 1
.DATA dsrcTIME pv1 pv20n 5v 0v5n 0v 5v10n 0v 5v
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.ENDDATA
.TRAN DATA=dsrc
. p r i n t v (1 ) v (2 )
.END
Switch, variable resistor is defined by:
G_Switch n1 n2 VCR PWL(1) c1 c2+ 0v ,100 g+ 1v , 1 p
R1 n1 n2 ’ 100g *(TIME>=T1) ’
Switch Level MOSFET is defined by:
Gnmos d s VCR NPWL(1) g s LEVEL=1 0 .4 v ,150 g+ 1v ,10meg 2v ,50 k 3v , 4 k 5v , 2 k
Voltage Controlled Capacitor is defined by:
Gcap out 0 VCCAP PWL(1) c t r l 0 2v , 1 p 2 .5 v , 5 p
Zero-Delay Gate Use VCCS is defined below. The table means, if output voltage is 0V, then output current is0A.
Gand out 0 AND(2) a 0 b 0 SCALE=’1/ r load’+ 0v , 0 a+ 1v , . 5 a+ 4v , 4 . 5 a+ 5v , 5 a
Zero-Delay Gate Use VCVS is defined below. The table means, if output voltage is 0V, then output current is0A.
e nandout 0 nand (2) in1 0 in2 0+ 0 .0 5 .0 v+ 0 .5 4 .8 v+ 1 .0 4 .5 v+ 4 .0 0 .5 v+ 4 .5 0 .2 v+ 5 .0 0 .0 v
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1.4 Advanced Topic 1: Transient AnalysisBy pass the initial analysis . May help to converge the circuit.
.TRAN 1ns 100ns UIC
.OP 20ns
Data driven sweep can be used for multi-parameter non-uniform value.
. t ran 1n 100n sweep data=mydata
. data mydata param1 param2 . . .va l1 va la . . .va l2 valb . . .. . . .. enddata
Parameter driven sweep only allow one parameter sweep.Param will be varied 10 times for each decade from 1u to 10u (lg increase)
. tran 1n 100n sweep param DEC 10 1u 10u
Param will be varied 5 equal times from 1u to 10u (Equal divide)
. param paramm=1k
. tran . 5 n 20n sweep paramm LIN 5 1k 10krand andout 0 paramm
Parameter altering to be done...
https : // s o l v n e t . synopsys . com/ r e t r i e v e /021478. html
Measuring Signal during transient..
1.5 Advanced Topic 2: Measure MethodTo measure waveform characters of rise, fall and delay:
.MEAS TRAN vmax MAX V( out ) FROM=TDval TO=Tstop
.MEAS TRAN vmin MIN V( out ) FROM=TDval TO=Tstop
.MEAS TRAN Tr i s e TRIG V( out ) va l=’vmin+0.1*vmax’ TD=TDval+ RISE=1 TARG V( out ) va l =’0.9*vmax’ RISE=1.MEAS TRAN Tf a l l TRIG V( out ) va l =’0.9*vmax’ TD=TDval+ FALL=2 TARG V( out ) va l=’vmin+0.1*vmax’ FALL=2.MEAS TRAN Tdelay TRIG V( in ) va l =2.5 TD=TDval FALL=1+ TARG V( out ) va l =2.5 FALL=2
To measure ripple, high voltage time:
.MEAS TRAN Th1 WHEN V( out)= ’ 0 .5* vcc ’ CROSS=1
.MEAS TRAN Th2 WHEN V( out)= ’ 0 .5* vcc ’ CROSS=2
.MEAS TRAN Tmid PARAM=’ (Th1+Th2)/2 ’
.MEAS TRAN Vmid FIND V( out ) AT=’Tmid ’
.MEAS TRAN Tfrom WHEN V( out)= ’Vmid ’ RISE=1
.MEAS TRAN Ripple PP V( out ) FROM=’Tfrom’ TO=’Tmid ’
To Measure power and on fly data:
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. meas tran inpu t i avg i ( r s ) from ’ 80/ f r eq_sca l ’ to ’ 95/ f r eq_sca l ’
. meas tran inputv avg v ( in ) from ’ 80/ f r eq_sca l ’ to ’ 95/ f r eq_sca l ’
. meas tran outputv avg v ( out ) from ’ 80/ f r eq_sca l ’ to ’ 95/ f r eq_sca l ’
. meas tran output i avg i ( r l oad ) from ’ 80/ f r eq_sca l ’ to ’ 95/ f r eq_sca l ’
. meas tran JUNC_efficiency param = ’ ( output i *outputv )/ ( i npu t i * inputv ) ’
. meas tran JUNC_frequency param = ’ f r eq_sca l ’
To measure waveform feature:
* measure two undershoots.MEAS TRAN imin1 MIN i (VDD) FROM=0.2n TO=0.7n.MEAS TRAN imin2 MIN i (VDD) FROM=0.8n TO=1.2n
* measure pu l s e width.MEAS TRAN Th1 WHEN i (VDD)=−0.015 CROSS=1.MEAS TRAN Th2 WHEN i (VDD)=−0.015 CROSS=2.MEAS TRAN Th3 WHEN i (VDD)=−0.015 CROSS=3.MEAS TRAN Th4 WHEN i (VDD)=−0.015 CROSS=4.MEAS TRAN Twidth1 PARAM=’ (Th2−Th1) ’.MEAS TRAN Twidth2 PARAM=’ (Th4−Th3) ’
1.6 Advanced Topic 3: Option SettingThe Hspice option is categorized into below table.
Method Resolution OutputBypass, Maxord, Method, Puretp, Trcon Accurate, Runlvl,... Post, Interp
Table 5: option table
Option Runlvl is used to balance speed and accuracy. Default accuracy is 3. 0 will turn off the option. 6 ishighest resolution.
. opt ions post=2 run l v l=0
Guidelines for runlvl setting:
Circuit type settingdigital 1-3Analog 3-5
Characterization 5-6
Table 6: Hspice run level
Option Method is used to control numerical integration algorithm. Four method is valid in HSpice, Backward-Euler, Gear, Trapezoidal, BDF.
Option Post is used to display plots using an interactive waveform viewer.
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1.7 Advanced Topic 4: Optimization Process (DC Analysis)Warning! This method is NOT recommend! Mainly two types of optimization flow, they are:
• Curve fit optimization requires curve data, param and measure statements.
• Goal Function Optimization optimization over a target function, use goal statements.
Required statements for optimization:
• .MODEL modname OPT ...
• .PARAM parameter=OPTxxx (init, min, max)
• A .DC, .AC, or .TRAN analysis statement with MODEL=modname, OPTIMIZE=OPTxxx, and RESULTS=measurename
• .MEASURE measurename ... <GOAL = .. or val> –note that a space is required
Step 1. Know your target.. The purpose is to optimize based on time or voltage/current?
• Time based. i.e. rise/fall timing fitting, then use TRAN analysis method.
• Value based. i.e. voltage/current match, then use DC/AC analysis method.
Step 2. Prepare Reference data.. For curve fit, prepare datafile
Step 3. Write Optimization Script in below script.
a. determine the parameter to optimize.
.PARAM pow = 0.8V+ r t e s t=optrange ( 0 . 5 , 0 . 1 , 100)
b. prepare cost function
. measure dc i d e r r e r r par ( dcurr ) i ( routM) minval=1n ignore=1n
. measure dc vderr e r r par ( dcurr ) i ( routM) minval=1n ignore=1n
c. setup optimization engine model
. model optmodel opt r e l i n=1e−3 i t r o p t=35 grad=1e−6 c l o s e=2 cut=4+cend i f=1e−9 r e l o u t=1e−3
Where: relin (relative input variation). itropt (maximum number iteration). grad (possible convergence if less thangrad). close (initial estimate of how close is). cut(close modifier). cendif(accurate derivative) . relout(relative outputvariance for convergence)
Warning 1 Hspice optimization is very sensitive to input data and error function selection. It is NOT recom-mended to use Hspice build-in opt engine to model RC circuit.Warning 2 Hspice optimization is very difficult to debug, there is no effective way to write complex measurefunction. It is NOT recommend to use Hspice build-in opt engine to debug model.
Example is made to estimate a load resistor. The case is located at:
/work/ j−chen/vcs_case / rc_modeling/hspice_opt_modeling
Step 1: use optimize_test.sp to generate testing U-I data junc1.datStep 2: write optimization script optimize_test2.spAfter running the simulation, the result will be printed as:
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opt imiza t i on completedmeasured r e s u l t s < r e l o u t= 1.0000E−03 on l a s t i t e r a t i o n s
**** opt imized parameters op t l* %norm−sen %change. param rp = 10.0000 $ 100.0000 24.3787m
****
******f i l e : junc t e s t prototpye for r e s i s t o r t e s t i n g
****** dc t r a n s f e r curves tnom= 25.000 temp= 25.000 ******
*** data name = de s i r ed 1 s t sweep ***i d s e r r= 611.6084m from= 1.0000 to= 401.0000
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1.8 Advanced Topic 5: Optimization Process (Transient Analysis)The Transient based optimization requires detailed waveform description, and normally consists with below steps:Step 1: List parameters to be optimized (Initial-guess Lower-bound Higher-bound)
.PARAM xxx = optrange (2 f , 1 f , 5 f )
Step 2: list measure criteria, we can use multiple measure statements.
.MEASURE er r param = xxx goa l = 0 *Try to make e r r o r to 0
Step 3: setup optimization model
.MODEL optmod OPT i t r o p t = 100 *Set # of i t e r a t i o n s for opt imiza t i on
.TRAN 0.01p 10n SWEEP OPTIMIZE = optrange RESULTS = er r MODEL = optmod
1.9 Advanced Topic 6: AC analysisPDN location:
~/vcs_case / spector_ver i log_mix / vhdl in /Test6
Progress:
• Spectre failed and Hang.
• Hspice hang for Xcore_or1k_core_or1200_cpu_or1200_if_addr_saved_reg_22_ now, trying to fix conver-gence with .ic method, also , reduce netlsit to have a try in ac_analysis_15nm_2
• Kanamoto sensei send modified model (doesn’t help on convergence issue):weff (effective channel width)lrsd (length of source-drain)asej adej (source junction area, drain junction area)psej pdej (source to substrate PN junction. drain to sub)
All parameter definition: https://xyce.sandia.gov/downloads/_assets/documents/Reference_Guide.pdf
Deal with convergence experiences:
Set below opt ions . However , gmindc and gmin should not be s e t l a r g e r than 1e−9.. opt ion gmindc=1e−9 gmin=1e−9. opt ion gshunt =1e−12 gmindc=1e−6 * from kanamoto s e n s e i
If option does not work, tie all the unconnected pins with 1000k resistors. where:
• gshunt add small inductor to each nodes(useful in high frequency situation)
• GMAX Connected with Vin, for initial node current calculation.
• GMINDC insert small resistors between bulk, source, near threshold region (default e-11, should not largerthan e-9)
• GRAMP adjust gmindc
• DCON control convergence flow
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Hspice convergence flow:
I f a c i r c u i t does not converge in the number o f i t e r a t i o n s that ITL1 s p e c i f i e s ,HSPICE i n i t i a t e s an autoconvergence proce s s . This p roc e s s manipulatesDCON, GRAMP, and GMINDC, and even CONVERGE in some ca s e s .
Figure 4:
flow control in below:
Se t t i ng .OPTION DCON=−1 d i s a b l e s Steps 2 and 3 .Se t t i ng .OPTION CONVERGE=−1 d i s a b l e s Steps 4 and 5 .Se t t i ng .OPTION DCON=−1 CONVERGE=−1 d i s a b l e s Steps 2 , 3 , 4 , and 5 .Se t t i ng the DV opt ion to a value other than the default , Step 2 uses the value you s e t for DV, but Step 3 changes DV to 1e6 .
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Se t t i ng .OPTION GRAMP has no e f f e c t on autoconverge . Autoconverges e t s GRAMP independent ly .S e t t i ng .OPTION GMINDC, then GMINDC ramps to the value you set ,i n s t ead o f to 1e−12, in Steps 2 and 3 .Se t t i ng .OPTION CONVERGE=5 invokes GSHUNT ramping which i s t r i e dbe f o r e GMATH ramping due to a more robust a lgor i thm than GMATH. TheGSHUNT algor i thm prov ides enhancements to the autoconvergence f lowcur rent probe , and numerica l s t a b i l i t y .S e t t i ng .OPTION CONVERGE=4 invokes the GMATH ramping method .
1.9.1 Analyze Process
The RC equivalent circuit: Here we use lowest frequency impedance as R1, and highest frequency impedance as R2.
Figure 5: Equivalent Circuit
In the RC network impedance calculation, the modulus is obtained by below equation:
|Z| = |Vac
Iac| =
|R1 · (R2 + 1jωC )|
|R1 +R2 + 1jωC |
(1)
Hence the capacitance C can be calculated as follows:
C =
√√√√(1
ω)2 ·
R12
|Z|2 − 1
(R1 +R2)2 − (R1·R2)2
|Z|2(2)
Here: ω = 2πf . In our simulation: Vac = 0.001, frequency ranges from 10kHZ to 10GHZ.By using equation(1), I found the calculated impedance is different with ”fitting” impedance result.
Reference The related calculation approach reference: https://www.allaboutcircuits.com/textbook/alternating-current/chpt-4/ac-capacitor-circuits/
imaginary reference https://wenku.baidu.com/view/3cc3cfc2aef8941ea66e0505.html
1.10 Advanced Topic 7: S-parameter files1.10.1 Hspice Signal Integrity
The basic hspice s model usage:
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**S−parameter example.OPTION post. probe v ( n2 ). ac l i n 500 1Hz 30MegHz. tran 0 .1 ns 10ns
P1 n1 0 port=1 Z0=50 ac=1v PULSE 0v 5v 5n 0 .5 n 0 .5 n 25n
P2 n2 0 port=2 Z0=50
* S parameterS1 n1 n2 0 mname=s_model. model s_model S TSTONEFILE = ss_ts . s2p
Rt1 n2 0 50. end
1.10.2 Signal Integrity
When using a touch stone file, with reference impedance:
*S−parameter example.OPTION postV1 n1 0 ac=1v PULSE 0v 1v 0n 0 .5 n 0 .5 n 4n 10n. ac l i n 500 1Hz 30MegHz. tran 0 .01 ns 20ns
* r e f e r e n c e node i s s e tS1 n11 n2 0 mname=s_model
* S parameter. model s_model S TSTONEFILE = lunwen1 . s2p
Rt1 n2 0 50r i n n1 n11 10. end
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2 Matlab Simulink2.1 Matlab TricksTo plot 3D figure from a excel file:
function plot3Ddata (x , y , z )test = xl s r ead ( ’ test . x l s ’ , ’A1 : C216825 ’ ) ;x=test ( : , 1 ) ;y=test ( : , 2 ) ;z=test ( : , 3 ) ;t r i = delaunay (x , y ) ;t r i s u r f ( t r i , x , y , z ) ;end
To plot figure from a txt file:
[ aveg_v aveg_i r i p p l e e f f f r e q load ref_v ] =text read ( ’ test . txt ’ , ’% f %f %f %f %f %f %f ’ ) ;
plot3Ddata ( f req , load , aveg_v )holdplot3Ddata ( f req , load , ref_v )
function plot3Ddata (x , y , z )x=test ( : , 1 ) ;y=test ( : , 2 ) ;z=test ( : , 3 ) ;t r i = delaunay (x , y ) ;t r i s u r f ( t r i , x , y , z ) ;end
2.2 Simulink TricksThis section tells simulink result . The overall simulink diagram is shown in below figure (correspond toFigure 5.):
Figure 6: Simulink diagram
First is the interleaved 2-phase clock. In order to prevent short circuit, there is a ’dead overlapping’ between twophases shown in below figure.A phase wave is typically described by:
1. voltage : typical 2V.
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Figure 7: Real phased clock wave
2. period : equals to 1/frequency, typical value 1/1MHZ.
3. delaytime : Td also stands for dead overlap time, typical 200ps.
4. risetime : Tr typical value 200ps.
5. falltime : Tf typical value 200ps.
6. pulsewidth : period/2 - Td − Tr − Tf
The generator proposed by reference book 2 in ?? is however not supported in Simulink because it will introduceinvalid arithmetic loop. Therefore I simplified the clock block into equivalent model shown in right side.
(a) proposed generator (b) simplified generator
Figure 8: Real phased clock wave v.s. simplified model
The second issue is the device model. Since simulink mainly has three main types of signals.
1. Standard Simulink signals: Ports that take in/ouput these signals have open arrowheads;
2. Physical signals: Ports that take in/ouput these signals have closed arrowheads;
3. Domain-specific signals. Ports that take in/ouput these signals have round circles;
The under-the-hood representation for these signals is different. We can not inter-connect any two of these signalsor even physical signals from different domains. A workaround is to use the Sensors and Sources blocks in therespective Domain library to convert the Domain Signals to Physical Signals and vice-versa. Then use the ’Physicalto Simulink’ or ’Simulink to Physical’ blocks in the ’Utilities’ library of Simscape. So that we can then interface thetwo domains ( Simscape and SimPowerSystems in this case ). The solution used in this case is replace the MOSFETwith switch model. we need to map the NMOS/PMOS capacitance and resistance into ’Snubber capacitance’ and’Snubber resistance’. The final output wave shown in below figure:Average output voltage is 0.963V, Related parameter setting:
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Figure 9: simulink output wave(upper current, bottom voltage)
Name V aluesimulation time 20e-5sinput voltage 2Vload resistance 5e4 Ω (50kΩ)
fly cap 1.3292e-9 Fload cap 1.3292e-9 F
switch internal 1 Ωswitch Snubber resistance 1e10 Ω
pulse period 10e-6sdead period 5e-7s
Table 7: Simulink setting
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3 Virtuoso Simulation UsageIn the unix environment, run below command to initiate Virtuoso to build up circuit.
source /eda/ cadence2 . shv i r tuo so −64
All the build in library is located in:
/eda/ cadence /Virtuoso / t o o l s / d f I I / e t c / c d s l i b / a r t i s t / analogLib /nport /
The design is placed under: /vlsilab/j-chen/lib/Test4 . To open a design, select from menu: ”Library”, in librarymanager, select and open Test4. In below dialogue box, select CORE+DRIVE design.
Figure 10: Library selection
The schematic window shows a DC-DC converter, which is 3:2 buck converter. There should be two phases, one iscontrolled by signal Ph1hb and Ph1b, another is controlled by signal Ph2h and Ph2. Two capacitors C1 and C2 arecharged in parallel in phase 1, then they are connected in serial to discharge in phase 2.
(a) CORE+DRIVE (b) CORE+DRIVE +PCB
Figure 11: Schematic View
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3.1 Virtuoso Simulation NotesVirtuoso has many tricks to go through.
Simulation setup process : To open a design, select ”CORE+DRIVER” to open.
Figure 12: Open design
Must click check/save button to perform netlist check. If there is any error, the dangling pin will flash.
Figure 13: check and save
Then select the ipwl file for current source. Initial value for source profile must be zero, otherwise blowup! Thenlaunch the simulation with ”ADE L”.
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In the new simulation window, set up the definition files(for transistor description) and stimulus files.
Figure 14: Simulation setup step 1
Next step is to set simulation time and accuracy defaults:
Figure 15: Simulation setup step 2
Next step is to DISABLE sst2 for output format, otherwise data will be lost! (output-> save all..)
Figure 16: Virtuoso Output Setting to Avoid Data Loss
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Then define the probe pin:
Figure 17: Define probe pin
Then click the netlist and run
Figure 18: netlist and run
Finally, remember to save the simulation result after simulation. The state will save a lot of setup time.
Figure 19: Save State
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Debugging process When change a instance setting, must modify the value and click to next input cell. Otherwise,the setting value will NOT be saved.
Figure 20: debug a setting
Also, remember to set load with 100nF and 5Ω. This will ensure reasonable output.
Unlock design Use below process if you found package is locked by someone
Type clsAdminTool at s h e l l prompt , and you w i l l get a > prompt2) Type are . /
Get stimulation environment Previous running is organized in below
TestNangate_sim/LPB_REF/ spe c t r e / schematic / n e t l i s t
3.2 Virtuoso Mix signal simulationExample case is located at:
/eda /6/ cadence /Virtuoso / t o o l s / d f I I / samples /
The tutorial document is located at:
/eda /6/ cadence /Virtuoso /doc/amsdInVirtuoso /amsdInVirtuoso . pdf
Spice import is controlled by spicein module, the doc:
/eda /6/ cadence /Virtuoso /doc/ transrefOA/ transrefOA . pdf
To change the default editor:
https : // secure . engr . o r e gons ta t e . edu/ wik i /ams/ index . php/Cadence/TipsAndTrickshttp : // eecs . o r e gons ta t e . edu/ research / v l s i / t each ing /ECE471_WIN12/ l a b s / c d s i n i thttp : //www. edaboard . com/ thread60653 . html
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3.2.1 Import Spice Netlist
In order to import a spice below step is necessary. The process is based on this case:
/eda /6/ cadence /Virtuoso / t o o l s / d f I I / samples / sp i c e I n /
Important: add PG pins before spice import!First is to select File->import...
Figure 21: spice in step 1
Note: the spice netlist top module name should NOT be the same as ”top level” name.
Figure 22: spice in step 2
Note: output lib is set to target library, cellview name...
Figure 23: spice in step 3
Note: load in mapping file (dev.map) and apply. The mapping file is listed in below:
−− Device Mapping f i l e generated from Spice In GUI
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devSe l e c t := capac i t o r capdevSe l e c t := r e s i s t o r r e sdevSe l e c t := pnp pmos4devSe l e c t := nmos nmos4devSe l e c t := npn nmos4devSe l e c t := pmos pmos4devSe l e c t := n f e t nmos4devSe l e c t := p f e t pmos4devSe l e c t := diode dio
To generate symbol layout:
(a) manual (b) box
Figure 24: Create Symbol View
3.3 Make use of finfetVirtuoso does not support finfet by default. First user need to add parameter in the schematic window as below:
Figure 25: Step 0: add parameter
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Then the CDF editor shall be opened and nfin parameter should be added.
Figure 26: Add parameter nfin in CDF
Finally, register the nfin parameter for the spectre simulator
Figure 27: Add parameter nfin for simulation
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3.4 Write out different signalThe waveform calculation method: Below expression can be used for ADE bode plotting.
Figure 28: Phase and angle probe setting for ADE
Phase expr e s s i on : phase (VF( ”/z_para_z11” ) )Magtitude exp r e s s i on : dB20(VF( ”/z_para_z11” ) )
3.5 Write out phase and amplitudeSelect output, phase and amplitude. Select net on schematic layout, press ’ESC’
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4 Verilog-A / Verilog-AMS IntroductionVerilog-A is still under developing. It claims to be the ”super-set” of Verilog. Verilog-A is supposed to be able tomodel both digital behavior ans analog behavior. Now the language can be partially supported in spectre.
4.1 Basic CodeVariable resistor:
// Veri logA fo r RCVA_4, Interface_RC , v e r i l o g a
‘ i n c lude ” cons tant s . vams”‘ i n c lude ” d i s c i p l i n e s . vams”
module VarRes (p , n , cp , cn ) ;
inout p , n ;input cp , cn ;e l e c t r i c a l p , n , cp , cn ;analog begin
i f (V( cp , cn )>=0.70)I (p , n) <+ V(p , n) / 10G;
else i f (V( cp , cn )>=0.21)I (p , n) <+ V(p , n) / 10G;
else i f (V( cp , cn ) >0.2)I (p , n) <+ V(p , n) / 470 ;
else i f (V( cp , cn)>0)I (p , n) <+ V(p , n) / 470 ;
elseI (p , n) <+ V(p , n) / 10G;
end
endmodule
Basic Resistor:
‘ include ” cons tant s . vams”‘ include ” d i s c i p l i n e s . vams”module r e s i s t_1k (p , n) ;parameter real r e s i s t a n c e = 1000.0 ;inout p , n ;e l e c t r i c a l p , n ;analogV(p , n) <+ I (p , n) * r e s i s t a n c e ;endmodule
Basic Capacitor:
‘ include ” cons tant s . vams”‘ include ” d i s c i p l i n e s . vams”module capac i t o r (p , n) ;parameter real c = 1 ;inout p , n ;e l e c t r i c a l p , n ;analogI (p , n) <+ ddt (V(p , n ) ) * c ;endmodule
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Basic Inductor:
‘ include ” cons tant s . vams”‘ include ” d i s c i p l i n e s . vams”module inductor (p , n) ;parameter real i = 1 ;inout p , n ;e l e c t r i c a l p , n ;analogV(p , n) <+ ddt ( I (p , n ) ) * i ;endmodule
Basic DC Voltage source:
‘ include ” cons tant s . vams”‘ include ” d i s c i p l i n e s . vams”module Vsource (p , n) ;parameter real dc = 1 ;output p , n ;e l e c t r i c a l p , n ;analogV(p , n) <+ dc ;endmodule
Basic DC Current source:
‘ include ” cons tant s . vams”‘ include ” d i s c i p l i n e s . vams”module Csource (p , n) ;parameter real dc = 1 ;output p , n ;e l e c t r i c a l p , n ;analogI (p , n) <+ dc ;endmodule
Basic flow control:
‘ include ” cons tant s . vams”‘ include ” d i s c i p l i n e s . vams”module r e l a y (p , n , ps , ns ) ;parameter real th r e sho ld = 0 ; th r e sho ld Voutput p , n ;input ps , ns ;e l e c t r i c a l p , n , ps , ns ;
analog begin@( c r o s s (V( ps , ns)− thresh , 0 ) ) ; // u s e l e s s , use wi th caut ioni f (V( ps , ns)− thresho ld , 0 ) )
V(p , n)<+0;else
I (p , n)<+0;endmodule
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4.2 Time operationTime operation
Figure 29: Time operation
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4.3 Example in verilogA verilog RC filter..
Figure 30: rc filter
RC filter 2:
‘ i n c lude ” d i s c i p l i n e . h”
module rc_ladder ( in , out , gnd ) ;inout in , out , gnd ;e l e c t r i c a l in , out , mid , gnd ;
parameter r=1k ;parameter c=1n ;
analog begin// s t a g e 1I ( in , mid ) <+ V( in , mid ) / r ;I (mid , gnd ) <+ ddt ( V(mid , gnd ) * c ) ;
// s t a g e 2I (mid , out ) <+ V(mid , out ) / r ;I ( out , gnd ) <+ ddt ( V( out , gnd ) * c ) ;
endendmodule
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4.4 Syntax VariableVector usage:
Module adc ( out , in , c l k ) ;parameter integer b i t s = 8 from [ 1 : 2 4 ]input in , c l koutput [ 0 : b i t s −1] out ;integer r e s u l t [ 0 : b i t s −1]
r e s u l t [ i ] = vdd
for ( i = 0 ; i<b i t s ; i = i +1) beginV( out [ i ])<+ t r a n s i t i o n ( t e s u l t [ i ] , td , t t ) ;
end
Unit is shown in below table
multiplier unit label1012 T109 G106 M103 k, K10−3 m10−6 u10−9 n10−12 p10−15 f10−18 a
integer can only support 231 signed number, which means 31 bit long.
4.5 Synthesis Simulation Verilog-AVerilog-A can be handled in Virtuoso and run through spectre.
step 1 Before the run, user need to add below file at local directory:
F i l e name : . c d s i n i t
Content :
;####################################; junc c rea ted to customize v i r tuo so;###################################
pr i n t f ( ” z z z z z z z z z z z z z z z z z z z z z z z z z z o e \n” )ed i t o r = ”/ usr /bin /gvim”
Perform below command in CDS window if not work
ed i t o r=”/ usr /bin /gvim”
step 2 Import verilog-a net list.
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(a) Create cell view (b) Read in file
Figure 31: Import verilog-a
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step 3 create a symbol view net list, by press alt-c, alt-c, alt-c, or select below menu:
(a) Create symbol view (b) Create symbol
Figure 32: Import verilog-a
4.6 Useful Verilog-A resource:
References[1] The Designer’s guide to verilog ams, Kenneth S. Kundert, Olaf Zinke. (Cook book)
[2] http://www2.ece.ohio-state.edu/~bibyk/ece822/verilogamsref.pdf reference manual
[3] http://www.designers-guide.org/VerilogAMS/ Example case
[4] https://verilogams.com/refman/modules/analog-procedural/timing.html Example flow model
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5 ModelSim for Gate LevelThe overall document is located at:
/eda /6/mentor/modeltech/docs / pdfdocs /
Demo case. The case is located in directory:
/work/ j−chen/vcs_case /demo_case_vsim/
To start ModelSim, run:
vsim
Then create project and add verilog source code files:
Figure 33: Add existing files.
Note: Do remember to modify verilog files if compile error. modelsim requires explicit relative path. For example,need to modify include file to:
‘ i n c lude ” . . / openr i sc_junc / or1200_def ines . v”‘ i n c lude ” . . / top/ t2k_system_defines . v”
And move parameter into module scope.
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To start simulation, select library->test->simulation :
Figure 34: start simulation
To analyze the signal, select the signal, then set the time and clock simulation.
Figure 35: View simulation wave
model sim script is enabled by ”do” script. User can setup all the simulation process by script and run modelsim:
vsim −do t e s t .dovsim −c −qu i e t −do ”do l i b s . do ; qu i t ”
or in t r a n s c r i p t s h e l l :do t e s t .do
An example case is prepared in directory:
/work/ j−chen/vcs_case /demo_case_vsim/ gate_leve l / t e s t .do
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An example is shown in below:
# c r e a t e a l i b or d e c l a r e a l i b ( u sua l l y for a model )v l i b junc_l ib
# map a l o g i c a l l i b namd (1 s t junc_l ib ) to a r e a l l i b l o c a t i o n (2nd junc_l ib )vmap junc_l ib junc_l ib# compi le source codes , −work i s a mustv log counter_gate . v counter_tb . v NanGate_45nm_OCL_conditional_modudp . v −work junc_l ib
# setup s imu la t i onvsim junc_l ib . t e s t −t 10nsadd wave sim : / t e s t /dut/*run 2000
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6 Gate Level with VCSThe verilog source file is counter.v and test bench file is counter_tb.v :
vcs −f main_counter . forvcs −f main_counter . f − f u l l 6 4
In the current directory, vcs will generate an executable file simv by default. Run the file and generate dump file.
simv
Then open the cscope and read in ”counter.dump”, you will read the wave. Note, need to change the nanosim.outinto nanosim.vf, and use nWave to open the waveform.
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7 Verilog Basic IntroductionThis section covers basic contents which will be used in later VCS simulation flow.[8] For a design, verilog writerneed to provide two parts, the design and test bench. You can go through the main idea of Verilog within 1 or 2hours in below link: http://www.asic-world.com/verilog/index.html
A typical design code is shown in below:
// 2:1 mux with s e l e c t i o n1 always @ (a or b or s e l )2 begin3 y = 0 ;4 i f ( s e l == 0) begin5 y = a ;6 end else begin7 y = b ;8 end9 end
// r e g i s t e r1 always @ (posedge c l k )2 i f ( r e s e t == 0) begin3 y <= 0 ;4 end else i f ( s e l == 0) begin5 y <= a ;6 end else begin7 y <= b ;8 end
// c l o c k genera tor1 always begin2 #5 c lk = ~ c lk ;3 end
In above section, = (blocking assignment) means the value will be assigned sequentially. While <= (non block-ing assignment) means the value will be assigned in parallel. #5 means 5 time units. For other Control flow ref-erence, see below netlink: http://www.asic-world.com/verilog/verilog_one_day2.html#Control_Statements
A typical test bench is shown in below: A detailed guidance of writing a test bench can be found in this linkhttp://www.asic-world.com/verilog/art_testbench_writing2.html
// Testbench Code Goes here29 module arb i te r_tb ;3031 reg c lock , r e s e t , req0 , req1 ;32 wire gnt0 , gnt1 ;3334 i n i t i a l begin35 $monitor ( ” req0=%b , req1=%b , gnt0=%b , gnt1=%b” , req0 , req1 , gnt0 , gnt1 ) ;36 c l o ck = 0 ;37 r e s e t = 0 ;38 req0 = 0 ;39 req1 = 0 ;40 #5 r e s e t = 1 ;41 #15 r e s e t = 0 ;
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42 #10 req0 = 1 ;43 #10 req0 = 0 ;44 #10 req1 = 1 ;45 #10 req1 = 0 ;46 #10 req0 , req1 = 2 ’ b11 ;47 #10 req0 , req1 = 2 ’ b00 ;48 #10 $finish ;49 end5051 always begin52 #5 c lo ck = ! c l o ck ;53 end5455 a r b i t e r U0 (56 . c l o ck ( c l o ck ) ,57 . r e s e t ( r e s e t ) ,58 . req_0 ( req0 ) ,59 . req_1 ( req1 ) ,60 . gnt_0 ( gnt0 ) ,61 . gnt_1 ( gnt1 )62 ) ;6364 endmodule
Other notes :Time Scale tells the system to use 1 ns for all reporting and internally use 1 ps for resolution of time in this partof design.
‘timescale 1ns /1ps
Dump file to dump all the variables during simulation
$dumpfi le ( ” t e s t . vcd” ) ;
Specify model to set delay
specifyspecparam TRise = 10 ,TFall = 15 ;( In => Out) = (TRise , TFall ) ;
$setup (Data_in , posedge Clock , TRise ) ;endspecify
$readmemh is used to read memory. A memory array may be initialized by reading memory pattern file from diskand storing it on the memory array. $readmemb is used for binary representation of memory content and $readmemhfor hex representation.
1 module memory ( ) ;2 reg [ 7 : 0 ] my_memory [ 0 : 2 5 5 ] ;34 i n i t i a l begin5 $readmemh( ”memory . l i s t ” , my_memory ) ;6 end7 endmodule
Example memory pattern file
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1 //Comments are a l l owed2 1100_1100 // This i s f i r s t address i . e 8 ’ h003 1010_1010 // This i s second address i . e 8 ’ h014 @ 55 // Jump to new address 8 ’ h555 0101_1010 // This i s address 8 ’ h556 0110_1001 // This i s address 8 ’ h56
forever will run endlessly. normally used in initial block
5 i n i t i a l begin6 #1 c lk = 0 ;7 forever begin8 #5 c lk = ! c l k ;9 end
10 end
7.0.1 Delay and advanced modeling
See below link for delay behavior model and timing check in verilog:
http : //www. w i l e y . com/ l e gacy / w i l e y c h i /mblin/supp/ s tuden t /LN07AdvancedModeling . pd f
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7.1 Verilog Note II7.1.1 Basic Operation
Wire is used for assign combinational logic. Typical
wire a ;wire [ 3 1 : 0 ] b ;wire [ 3 1 : 0 ] c , d ;
reg is used for register logic. Every assignment in the always logic must be defined as reg. Typical
reg a ;reg [ 3 1 : 0 ] b ;reg [ 3 1 : 0 ] c , d ;
memory is defined by register collection. like:
// a memory wi th 1k 32− b i t r e g i s t e r s .reg [ 3 1 : 0 ] memory_name [ 1 0 2 3 : 0 ] ;// access memorymemory_name [ address ] <= data ;outdata = memory_name [ address ]
Memory access is shown in below
reg [ 7 : 0 ] memory [ 0 : 7 ] ;integer i ;i n i t i a l begin
$readmemb( ” i n i t . dat ” , memory ) ;for ( i =0; i <8; i=i +1)
$display ( ”Memory[%d ] =%b” , i , memory [ i ] ) ;end
block and non-blocking assignment.
• Blocking: = Effective instantently, in combinational logic.
• Non-Blocking : <= Effective after always block. In sequential locig.
7.1.2 Control Flow
If else flow in blow form
i f ( a>b) beginout1<=int1 ;out2<=int2 ;end
else beginsat1 <=1’b1 ;end
Note: must complete if-else. Otherwise a latch will be generated.
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7.1.3 Auto generate verilog
To dynamically generate verilog:
genvar j ;generate
for ( j =0; j<N; j=j+1)begin : xor_loop
xor g l ( out [ j ] , i 0 [ j ] , i 1 [ j ] ) ;end
endgenerate
7.1.4 System call
To display message:
reg [ 1 1 : 0 ] r1 ;r1=10;$display ( ” S imulat ion dec va l $d , =%h ! ” , r1 , r1 ) ;$dumpfi le ( ” my f i l e . dump” ) ;$dumpvars ( top ) ;
7.1.5 Synthesis-able Verilog Code
Better to apply below principles:
• One always one event expression(combine with different events)
• Don’t mix level and edge event in always event
• For multiple event, use or
• Only use one edge (even for reset or set)
• Define reg for any assignment in always
• Level sensitive as combinational logic
• Hard to find in design-compilerdangling wire vector (bus) is NOT synthesisablemissmatch port vector is NOT synthesisablere-assign vector is NOT allowed
Below listed some useful examples
// a 3:1 mux examplemodule mux_2_1 ( out , a , b , s e l ) ;
input a , b , s e l ;output out ;reg out ; // why reg here ? JUNC
always @(a or b or s e l )i f ( ! s e l ) out = a ;else out = b ;
endmodule
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// 3 b i t adder wi th assignmentmodule adder3b i t ( count , sum , a , b , carry_in ) ;
input [ 2 : 0 ] a , b ;input carry_in ;output count ;output [ 2 : 0 ] sum ;assign count , sum = a+b+carry_in ;
endmodule
// a 4−1 muxmodule mux_4_1 ( out , i1 , i2 , i3 , i4 , s e l ) ;
output out ;input i1 , i2 , i3 , i 4 ;input [ 1 : 0 ] s e l ;reg out ; // output as reg , because as s i gned in b l o c k
always @( i 1 or i 2 or i 3 or i 4 or s e l ) begincase ( s e l )1 ’ b00 : out = i1 ;1 ’ b01 : out = i2 ;1 ’ b10 : out = i3 ;1 ’ b11 : out = i4 ;default : out = 1 ’bx ;endcase
end
endmodule
// 4− b i t countermodule counter (Q, c lk , c l e a r ) ;
output [ 3 : 0 ] Q;input c lk , c l e a r ;reg [ 3 : 0 ] Q;
always @(posedge c l k or posedge c l e a r )begin
i f ( c l e a r==1’b1 )Q<=4’d0 ;
elseQ<=Q+1;
end
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8 VHDL8.1 Basic IntroductionA VHDL design consists of entities, architectures, and configurations.
Figure 36: VHDL structure
Entity is design’s external interface. in below example:
ENTITY andgate ISPORT ( a : IN s td_log i c ;
b : IN s td_log i c ;c : OUT s td_log i c ) ;
END andgate ;
Architecture is the internal implementation. An entity may have different architectures.
ARCHITECTURE a_name OF entity_name ISBEGIN
−− some codec <= a AND b ;
END a_name ;
Process is high level like code, executed in serial.
label : PROCESS ( s en s i t i v e_s i gna l 1 , . . . )begin
end process ;
Configuration determines the mapping between architecture and instance of architecture.
8.2 Data typeBelow data types are listed from https://wenku.baidu.com/view/b85d9863783e0912a2162a7e.html
CONSTANT vcc : i n t e g e r :=1; −− de f i n e a cons tant va lueVARIABlE count : i n t e g e r 0 to 255:=20 −− a v a r i a b l e wi th i n i t i a l 20SIGNAL c l k : b i t := ’0 ’ ; −− a wire , i n i t i a l va lue i s 0SIGNAL count : BIT_VECTOR(3 DOWNTO 0 ) ; −− a wire bus
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Update signal is:
x<=9;z<=x after 5ns ;
8.3 Logic valueStandard logic value is..
U: u n i n i t i a l i z e d ;X: f o r c i n g unknow ;0 : f o r c i n g 01 : f o r c i n g 1Z : high impedanceW: weak unknownL : weak 0H: weak 1−: don ’ t care
Where the std_logic only allows ”-,1,z,0”. The logic can be converted by:
To_bit ( su l ) − from std_ulog i c to b i tTo_bitvector ( su lv ) − from std_ulog ic_vector / std_log ic_vectorTo_StdULogic (b) − from b i t to s td_ulog icTo_StdLogicVector (bv ) − from bit_vector or std_ulog ic_vectorTo_StdULogicVector (bv)− from bit_vector or s td_log ic_vectorTo_X01(v ) − from bit , std_ulogic , or s td_log i c to X01To_X01Z(v ) − from bit , std_ulogic , or s td_log i c to X01ZTo_UX01(v ) − from bit , std_ulogic , or s td_log i c to UX01
The value type can be converted by:
CONV_INTEGER() to integerCONV_STD_LOGIC_VECTOR()
8.4 process, function, procedureThe Process can be defined by (similar with always or initial block in verilog):
l a b e l 1 : PROCESS ( s i gna l 1 , s i g n a l 2 . . . )−− v a r i a b l e d e c l a r eBEGIN
−− executed in s e r e i a lEND PROCESS l a b e l 1 ;
While procedure and function must be used only in process. Below is example:
01 . l ibrary i e e e ;02 .use i e e e . std_logic_1164 . a l l ;03 .use i e e e . std_logic_unsigned . a l l ;04 .05 . entity swap i s06 . port07 . (08 . data : in s td_log ic_vector (7 downto 0 ) ;09 . q : out s td_log ic_vector (7 downto 0)10 . ) ;11 .end entity ;12 .
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13 . architecture r t l of swap i s14 .15 .procedure swap1 ( a : inout s td_log ic_vector (7 downto 0) ) i s16 . variable temph , templ : s td_log ic_vector (3 downto 0 ) ;17 .begin18 . templ :=a (3 downto 0 ) ;19 . temph:=a (7 downto 4 ) ;20 . a:=templ&temph ;21 .end swap1 ;22 .begin23 . process ( data )24 . variable b : s td_log ic_vector (7 downto 0 ) ;25 . begin26 . b:=data ;27 . swap1 (b ) ;28 . q<=b ;29 . end process ;30 .end r t l ;
8.5 LibraryThere are two libs which can be used implicitly: std and work, where std is ieee libraries, work is used for userimplementation. To use library:
Library std ;Use std . t e x t i o . a l l ;
To define a library:PACKAGE fun IS
END;
8.6 Build in functionList VHDL build in APIs...
to_x01 ( ) −−
8.7 ExamplesBelow examples from [2]. Full implementation of different logic elements can be found at[3] Below is 4 to 1 MUX
l ibrary i e e e ;use i e e e . std_logic_1164 . a l l ;entity MUX41 i sport −−de f i n e inpu t s and outpu t s
( S1 : i n b i t ; −− input S1S0 : i n b i t ;D3 : in b i t ;D2 : in b i t ;D1 : in b i t ;D0 : in b i t ;Y : out b i t −− output Y, note : NO
) ;end MUX41;
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architecture l o g i c of MUX41 i s −− Note MUX41 i s the same as e n t i t y name abovebegin
Y <= (D0 and (not S1 ) and (not S0 ) ) or(D1 and (not S1 ) and S0 )or (D2 and S1 and (not S0 ) ) or(D3 and S1 and S0 ) ;
end l o g i c ; −− Note matching names ‘ l o g i c’
Another 2 to 1 MUX uses vector and if-else flow
l ibrary i e e e ;use i e e e . std_logic_1164 . a l l ;entity MUX2to1 i s port (
A, B: in s td_log ic_vector (7 downto 0 ) ;Se l : in s td_log i c ;Y: out s td_log ic_vector (7 downto 0 ) ) ;
end MUX2to1 ;
architecture behavior of MUX2to1 i sbegin
process ( Sel , A, B) −− rerun process i f any changes ,begin
i f ( Se l = ’1 ’ ) thenY <= B;
else Y <= A;end i f ; −− note t ha t *end i f * i s two words
end process ;end behavior ;
8.8 Reference
References[1] http://atlas.physics.arizona.edu/~kjohns/downloads/vhdl/599_2008_94_2797.pdf VHDL tu-
torial.
[2] https://mil.ufl.edu/3701/examples/vhdl/VHDL_examples.pdf VHDL example
[3] http://esd.cs.ucr.edu/labs/tutorial/ different logic elements
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9 nWave UsageThis section covers usage of nWave. nWave is used to view the output waveform of nanosim. It can handle bothanalog and digital data. The detailed usage is listed in user manual[11]. In order to read the data, user must renamedefault .out file into .vf file. The .vf file has below format:
; ! output_format 5 .3; header 408337244; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−; | |; | NanoSim Vers ion F−2011.09−SP2 |; | SN:20120217−amd64 |; | Machine Name : bufo . i c s . e s . osaka−u . ac . jp |; | Copyright ( c ) 2011 Synopsys Inc . , A l l Rights Reserved . |; | |; −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−;; Bu i l t by nsmgr on Fr i Feb 17 01 : 36 : 52 PST 2012; Mon Mar 27 16 : 03 : 34 JST 2017;;. vdd 1 .2. t ime_reso lut ion 0 .001. cu r r en t_re so lu t i on 1e−07. vo l t ag e_re so lu t i on 0 .001; t e n t a t i v e s imulat ion_time 9007199254740000;. h igh_threshold 0 .84. low_threshold 0 .36. nnodes 84186. nelems 394219. extra_nodes 0. bus_notation [ − ]. h i e r_separator .. case L. index i ( vdd ) 1 i01 −18246801 −11246911 −110226
Format description
• Here time_resolution 0.001 means minimum unit is 0.001 ns(1ps). The default resolution is 0.01ns[10]. (set byset_sim_tres in nanosim cfg file).
• The current_resolution 1e-07 means minimum current resolution, the set command is set_sim_ires.
• The voltage_resolution defines the voltage unit(default 10mV). set_print_vres will set this for nanosim cfgfile.
• The signal is presented by two lines: time line, and ”index value” line.
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To Read the Waveform See below figure. Each value is shown in three values: actual value, reference value anddifference with reference.
Figure 37: How to read the waveform
To set the grid , use below menu View->Grid Options
Figure 38: Enable Grid of nWave
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To zoom time , drag the mouse on the top blue bar
Figure 39: Zoom Time
To zoom value , drag from left corner
Figure 40: Zoom Value
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10 NanoSim SimulationTBD
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11 V2LVS Conversion Verilog and SpiceIn order to convert a Verilog netlist into Spice netlist, there are several ways.
• v2lvs in calibre
• verilogIn in cadence
• nettran in Herculs of synopsys
The Calibre tool document is located in (Topic can be searched via index.html):
/eda /6/mentor/docs_cal_2013 . 2_18 .13/ docs /
V2LVS tool is described in Calibre VericationUser’s Manual.[12]. Here the LVS refers to Layout Versus Schematiccircuit. The usage section is on page 633. Chapter 17. The V2LVS tool translates a verilog netlist into spice netlist.
• Load Verilog Library
v2 lvs : : l oad_ver i l og $ f i l e _ l i s t in t c l f i l e− l $ f i l e _ l i s t in command l i n e
• Load Spice model as pin only internal contents are ignored.
v2 lv s : : load_spice −range_mode or ”− l s r ”#w i l l load i n t e r f a c e in fo rmat ion for p [ n ]
v2 lv s : : load_spice −pin_mode or ”− l s p ”#w i l l load i n t e r f a c e in fo rmat ion for pin
• Include Spice Library Files
V2lvs : : s e t_ inc lude s in t c l f i l e−s in command l i n e
Useful TCL and options:
Option Tcl Command Description-i v2lvs::generate_ordered_pins -enable generate pins for spice simulators
-incvdir v2lvs::include_dir directory for include files-l v2lvs::load_verilog -lib_mode verilog lib file-lsp v2lvs::load_spice -pin_mode translate spice pin into verilog-lsr v2lvs::load_spice -range_mode translate spice pin into verilog pin vector-n v2lvs::unmber_unconnected_pins unconnected pins receive numbered connections-o v2lvs::write_output specifies the output spice file-s v2lvs::set_includes specify include files for spice-sn v2lvs::override_globals -default_not_connected pg nets are not connected to global nets-w v2lvs::set_warning_level set warning level-v v2lvs::load_verilog specifies verilog netlist
12 VCS Mix Signal SimulationIn order to simulate wire transition in spice model, Calibre xRC is required. The reference manual is located in [13].xRC will read in layout and extract spice model.
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12.1 VCS SimulationVCS is a Verilog emulator. It can simulate chip behavior at large scale and long time. VCS first compiles the verilogsource code into object files, which are nothing but C source files. VCS can compile the source code into the objectfiles without generating assembly language files. VCS then invokes a C compiler to create an executable file. We usethis executable file to simulate the design.[4]
12.1.1 Basic Tutorial
All the case is located in directory:
/work/ j−chen/vcs_case /demo_case_vcs
The verilog source file is counter.v and test bench file is counter_tb.v Firstly, put two files’ name into main_counter.fthen run below command:
vcs −f main_counter . forvcs −f main_counter . f − f u l l 6 4
In the current directory, vcs will generate an executable file simv by default. Run the file and generate dump file.
simv
Then open the cscope and read in ”counter.dump”, you will read the wave. Note, need to change the nanosim.outinto nanosim.vf, and use nWave to open the waveform.
12.1.2 VCS NanoSim Simulation
The Nanosim can be integrated in to VCS simulation[5]. The purpose of VCS and NanoSim integration is to verifythe chip at gate level(Verilog) as well as transistor level(Spice). So that mixed signal behavior can be understood.The output result is VCD(Value Change Dump) file for digital part and .out file for nanosim analog part. Also, a_uod.out file combines the two format, which can be viewed by nWave.
Verilog Top Flow Is to verify the verilog top chip together with spice analog circuit. You need to prepare verilogfile, spice file and a wrapper over spice file, so that spice part looks like a model. The preparation flow is shown in[5] page 23. To run a simulating, run
vcs des ign . v +adorvcs −f my_vf i l e_l i s t . txt +ad=my_setup . i n i t −o my_simv
File Preparation .
• Resistance map file (resis_map) will relate verilog resistance level to real analog resistance. The defaultfile is located in ”/Nanosim_installed_directory/platform/ns/interface/vcsace”.
• simulation setup file, by default VCS will read vcsAD.init . The mixed-signal simulation setup file containsboth the partition command and choose command. All other commands, set rmap, set bus_format, setsub_unit, and set out_res, are optional.
choose Command: choose nanosim -n net.spi bsim_lib.sp -c config;partition Command: partition -cell subckt1 subckt2;set rmap command: set rmap resis_comp.map;set bus_format Command: set bus_format <%d>;set sub_unit and set out_res Commands
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choose nanosim −n system_top . sp i −C c fg ;s e t bus_format [%d ] ;s e t rmap resis_map ;
• Design Spice File
•
12.2 CustomSim XAThe introduction documents can be found at:
/eda /6/ synopsys /xa_vM−2017.03/ doc/webworks/ index . htm
Basic usage:
$> xa [− format ] n e t l i s t _ f i l e [ command_line_options ]For example :&> xa input . sp −o . /OUTPUT_DIR −ou t f i l e fm t hsp i c e −c xa . c f g
Supported file and useful command line options
Netlist Format Command Line OptionsHSPICE -n, -hspiceSpectre -nspectre, -spectre
Table 8: Supported netlist file
Option Description-t time[unit] Overwrites the transient analysis time specified in the netlist.
The unit can be ms, us, ps or ns. default is n-c Specifies the name of the command file
Table 9: Command line options
Writing Configure file In a typical customSim run, user can set below batch command in configure file. However,the resolution setting does not work. Customsim will internally dynamically control time/current resolution duringsimulation. each user can use at most 10 cores.
probe_waveform_voltage t e s t . u0 .N* − l im i t 99set_waveform_option −format out −gr id_i 1n −grid_v 1n −t r e s 0 . 1 pset_multi_core −core 10
Output Format Currently, the output format fsdb is dumped in new version which existing cScope and nWavecan’t read in. Therefore it is recommended to use .out format.
Print command Below listed some typical usage of print waveform command. The first two commands will dumpvoltage under model test/u0 into xa.out file. The third command will dump current for all the pins of instancetest.u0.XU4906. The hierarchy search depth is 99.
probe_waveform_voltage t e s t . u0 . N5993 − l im i t 99probe_waveform_voltage t e s t . u0 . * − l im i t 99probe_waveform_current − i a l l t e s t . u0 . XU4906 . * − l im i t 99
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OS Setup Do remember to add below environment settings
setenv LD_LIBRARY_PATH /work/ j−chen/ junc_bin/mpc/ l i b :/work/ j−chen/ junc_bin/gmp_j/ l i b :/work/ j−chen/ junc_bin/mdfr/ l i b :$LD_LIBRARY_PATH
setenv PATH /work/ j−chen/ junc_bin/bin_j/bin :$PATH
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References[1] http://ee.usc.edu/~redekopp/ee209/virtuoso/setup/USCVLSI-VirtuosoTutorial.pdf Clear tutorial for
beginners.
[2] https://www.eda.ncsu.edu/wiki/FreePDK15:Analog_Artist_with_HSPICE HSPICE tutorial
[3] http://www.csl.cornell.edu/courses/ece5745/handouts/ece5745-tut1-vcs.pdf VCS tutorial
[4] http://userwww.sfsu.edu/necrc/files/synopsys%20tutorials/VCS_tutorial.counterexample
[5] www.61ic.com/code/attachment.php?aid=14374&k...t=1458601850 NanoSim Integration with VCS Manual
[6] /eda/6/synopsys/F-2011.09-SP2/doc/ns/tutorials/nanosim/NS-VCS/NS-VCS.pdf
[7] http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf full VCS slides
[8] http://www.ece.umd.edu/class/enee359a/verilog_tutorial.pdf
[9] http://vol.verilog.com/VOL/main.htm
[10] Nanosim reference manual page 348
[11] /eda/6/synopsys/F-2011.09-SP2/doc/ns/manuals/nwave.pdf nWavge user manual
[12] /eda/6/mentor/docs_cal_2013.2_18.13/calbr_ver_user.pdf Calibre verification users manual
[13] /eda/6/mentor/docs_cal_2013.2_18.13/xrc_user.pdf Calibre xRC users manual
[14] http://venividiwiki.ee.virginia.edu/mediawiki/index.php/FinFET_FreePDK15_Tutorial
[15] https://people.eecs.berkeley.edu/~hu/Chenming-Hu_ch7.pdf Introduction of FinFet by Hu
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12.3 VCS with verilog-AThe flow is enabled by adding below code in the spice file:
$ Sp ice n e t l i s t generated by v2 lv s$ v2013 . 2_18 .13 Thu May 16 11 : 29 : 55 PDT 2013.INCLUDE ” vcs_l ib / al l_15nm_cel l . s p i ”.INCLUDE ” vcs_l ib / al l_15nm_trans istor . i nc ”.INCLUDE ” vcs_l ib /env_cfg_15nm . inc ”.INCLUDE ” vcs_l ib / c i r c u i t_ r c . inc ”. hdl t e s t . vams
.SUBCKT leakage_chain out inXU2 in N1 INV_X1RU1 N1 VSS 150k.ENDS
In the verilog-A file, example:
‘ i n c lude ” cons tant s . vams”‘ i n c lude ” d i s c i p l i n e s . vams”
//module t e s t r (p , n , cp , cn ) ;module t e s t r (p , n) ;
inout p , n ;e l e c t r i c a l p , n ;
analog beginI (p , n) <+ V(p , n) / 10 ;endendmodule
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13 Python development13.1 Automation13.1.1 Automatic run programs in windows, API COM level
This approach interacts with windows programs at API level. First, you need to install python for windows extension:https://github.com/mhammond/pywin32 with below command:
python −m pip i n s t a l l pywin32
Then install the DLL by:
python c : \ u s e r s \ junc \AppData\Local \Programs\Python\Python36\S c r i p t s \ pywin32_post ins ta l l . py − i n s t a l l
A send key example can be found at:http://code.activestate.com/recipes/65107-sendkeys-from-the-windows-script-host-wsh-com/
13.1.2 Automatic run programs in windows, GUI level
This solution is based on windows SDK. The inspect is located at:
C: \ Program F i l e s ( x86 )\Windows Kits \10\ bin \10 . 0 . 16299 . 0\ x64\ i n sp e c t . exe
13.1.3 Automatic run programs in windows, Key-mouse level
This approach is based on pywinauto and sendkey.
13.1.4 Prerequriements
First, to install the uiautomation from :
https : // g i t hub . com/ y inka i sheng /Python−UIAutomation−for−Windows
To inspect the menu for each programs, user need to install:
https : // deve l ope r . mic roso f t . com/en−us/windows/downloads/windows−10−sdk
13.1.5 Automatic run browser in windows
This approach is based on splinterhttp://blog.csdn.net/qq_24338883/article/details/52462699Or seleniumhttps://www.cnblogs.com/cloverclt/p/5694765.html
13.1.6 Other automation tool
http://www.sikuli.org/ this is graphic based recognizing tool.
13.2 File accessTo access file on network drive:
os . system ( ’ net use z : \\ dtbu i ld \ i n s t a l l e r ’ )
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14 Web developmentAll the web utility is located at:
Server d i r e c t o r y :/ v l s i l a b /www−use r s / j−chen/
Access v ia :http : //www−i s e 1 . i s t . osaka−u . ac . jp /~ j−chen/
14.1 Setup processStep 1 : Install python3
cd Python−3.6 .4c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/python3make t e s tmakemake i n s t a l la l i a s python ”/work/ j−chen/ junc_bin/python3/bin /python3”
Step 2 : Install Django.The package is unzipped in below:
# /work/ j−chen/ junc_bin/Django−2.0 .1python −m pip i n s t a l l django
The process can be verified by:
pythonimport django
14.2 Django operationNote: this section is based on below reference:https://code.ziqiangxuetang.com/django/django-basic.html
Start a new project :
django−admin . py s t a r t p r o j e c t junc_page
cd junc_pagedjango−admin . py star tapp app1
Start server :
python manage . py migratepython manage . py runse rve r
Then , in the l o c a l environment OS acc e s s :http : // 127 .0 .0 . 1 : 8000/
http : // 127 .0 .0 . 1 : 8000/ add/?a=4&b=5
Conclusion : NOT needed.
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14.3 PHP-Python developmentInstall php:
Code
14.4 CONCLUSION: Server script is blocked!NA.
14.5 chrome debugChrome can be used to obtain necessary head and cookie, so that web scraper can fetch data on the different site.
Cleanup cookie :
c t r l+s h i f t+de l
Note: you need to cleanup all the cookies before further debugging.
Inspect head and cookies : input the url, then click, run below key
c t r l+s h i f t+i
In below figure, copy the head for phtyon 3 usage.
Figure 41: head inspection
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14.6 MarkdownMarkdown file simple example:
## This i s the F i r s t doc
Tried markdown because o f s e v e r a l t a r g e t s
− To f i nd an e f f e c t i v e way for web ed i t i n g− To f i nd an e f f e c t i v e way for doc ed i t i n g
There fore I use
| 1 | 2 | 3 || −−−− | −−−− | −−−− || 4 | 2 | 3 || 123 | 123 | 123 || 123 | 123 | 123 || 123 | 123 | 123 || 123 | 123 | 123 |
From above tab l e . .
The result is:
Figure 42: Markdown
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15 UnixThis section covers environment setup. My working environment is mainly based on csh (samba default isbsh). Therefore you can switch to csh by append below sentences into /.bashrc:
i f [ −f / bin / csh ] ; thenexec /bin / cshf i
To install gvim, run below command:
g i t c l one https : // github . com/vim/vim . g i tcd vim/ s r cmake i n s t a l l DESTDIR=~/. local
Useful vim tricks
:%s / \ ( . . \ . . . .m\)/0\1/ g
Show Japanese in vim:
: s e t encoding=utf−8: s e t f i l e e n c o d i n g s=i so −2022−jp , euc−jp , s j i s , ut f−8: s e t f i l e f o rma t s=unix , dos ,mac
Import windows python to unix python:
: s e t f i l e f o rma t s=unix
Kill a process
k i l l −9 PID# 9 means KILL (non−catchable , non−i gno rab l e k i l l )
List all the process and sort
ps | log_of_your_processtop then s h i f t+f then m. .
Check whether and access web content on line:
c u r l wttr . in /~Stat−use+Of+Liberty
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15.1 Shell experienceSend mail by execute:
echo ”ddddddddddddddd” | mailx −s ” t e s t mail ” j−chen@ist . osaka−u . ac . jp
Shutdown machine by execute:
sudo shutdown −h now
Grep multiple keywords by grep:
h sp i c e t e s t_ junc_t rans i s t o r . s p i | grep −E ’ imin | twidth ’
Concatenate file by column is:
paste name passwd
Check Centos Versio is:
rpm −−query centos−r e l e a s e
Check lib version is:
yum l i s t i n s t a l l e d | grep l i bu sb
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15.2 Update Unix Utility VersionThis section tells about unix utility version including gcc, unix build-in utilities and necessary libraries. For commonunix components, three libraries are required: GMP, MPFR and MPC. Then the build in utilities will be covered.
autoconf installation Unix program installation requires two steps, configuration and make. The configurepackage is performed by autoconf command. To download the package:
http : // f t p . gnu . org /gnu/ autoconf /
Then preform below command to install:
c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/ autoconf_jmakemake i n s t a l l
In the cshrc file, add below command:
setenv PATH /work/ j−chen/ junc_bin/ autoconf_j /bin :$PATH
GMP installation This package is required by later packages. Download GMP from below link:
https : // gmpl ib . org/#DOWNLOAD
Then install the package with below command:
c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/gmp_jmakemake i n s t a l l
The install result.
L i b r a r i e s have been i n s t a l l e d in :/work/ j−chen/ junc_bin/gmp_j/ l i b
I f you ever happen to want to l i n k aga in s t i n s t a l l e d l i b r a r i e sin a g iven d i r e c to ry , LIBDIR , you must e i t h e r use l i b t o o l , ands p e c i f y the f u l l pathname o f the l i b r a ry , or use the ’−LLIBDIR ’f l a g during l i n k i n g and do at l e a s t one o f the f o l l ow i ng :
− add LIBDIR to the ’LD_LIBRARY_PATH’ environment va r i ab l eduring execut ion
− add LIBDIR to the ’LD_RUN_PATH’ environment va r i ab l eduring l i n k i n g
− use the ’−Wl,− rpath −Wl, LIBDIR ’ l i n k e r f l a g− have your system admin i s t ra to r add LIBDIR to ’ / e t c / ld . so . conf ’
See any opera t ing system documentation about shared l i b r a r i e s formore informat ion , such as the ld (1 ) and ld . so (8 ) manual pages .−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−/bin /mkdir −p ’ /work/ j−chen/ junc_bin/gmp_j/ inc lude ’/ usr /bin / i n s t a l l −c −m 644 gmp . h ’ /work/ j−chen/ junc_bin/gmp_j/ inc lude ’
make i n s t a l l −data−hookmake [ 4 ] : Enter ing d i r e c t o r y ‘/work/ j−chen/vcs_case /gcc_j/gmp/gmp−6.1 .2 ’
MPFR installation This package depends on GMP. The package can be downloaded from
http : //www. mpfr . org /mpfr−current/#download
Then install the package with below command:
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c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/mdfr −−with−gmp=/work/ j−chen/ junc_bin/gmp_j/makemake i n s t a l l
The install result.
L i b r a r i e s have been i n s t a l l e d in :/work/ j−chen/ junc_bin/mdfr/ l i b
I f you ever happen to want to l i n k aga in s t i n s t a l l e d l i b r a r i e sin a g iven d i r e c to ry , LIBDIR , you must e i t h e r use l i b t o o l , ands p e c i f y the f u l l pathname o f the l i b r a ry , or use the ’−LLIBDIR ’f l a g during l i n k i n g and do at l e a s t one o f the f o l l ow i ng :
− add LIBDIR to the ’LD_LIBRARY_PATH’ environment va r i ab l eduring execut ion
− add LIBDIR to the ’LD_RUN_PATH’ environment va r i ab l eduring l i n k i n g
− use the ’−Wl,− rpath −Wl, LIBDIR ’ l i n k e r f l a g− have your system admin i s t ra to r add LIBDIR to ’ / e t c / ld . so . conf ’
See any opera t ing system documentation about shared l i b r a r i e s formore informat ion , such as the ld (1 ) and ld . so (8 ) manual pages .−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−/bin /mkdir −p ’ /work/ j−chen/ junc_bin/mdfr/ inc lude ’/ usr /bin / i n s t a l l −c −m 644 mpfr . h mpf2mpfr . h ’ /work/ j−chen/ junc_bin/mdfr/ inc lude ’
MPC installation This package depends on GMP and MPFR. The installation package can be downloaded at:
http : //www. mu l t i p r e c i s i on . org / index . php?prog=mpc&page=download
Then install the package with below command:
c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/mpc −−with−gmp=/work/ j−chen/ junc_bin/gmp_j/ −−with−mpfr=/work/ j−chen/ junc_bin/mdfr/makemake i n s t a l l
The install result
L i b r a r i e s have been i n s t a l l e d in :/work/ j−chen/ junc_bin/mpc/ l i b
I f you ever happen to want to l i n k aga in s t i n s t a l l e d l i b r a r i e sin a g iven d i r e c to ry , LIBDIR , you must e i t h e r use l i b t o o l , ands p e c i f y the f u l l pathname o f the l i b r a ry , or use the ’−LLIBDIR ’f l a g during l i n k i n g and do at l e a s t one o f the f o l l ow i ng :
− add LIBDIR to the ’LD_LIBRARY_PATH’ environment va r i ab l eduring execut ion
− add LIBDIR to the ’LD_RUN_PATH’ environment va r i ab l eduring l i n k i n g
− use the ’−Wl,− rpath −Wl, LIBDIR ’ l i n k e r f l a g− have your system admin i s t ra to r add LIBDIR to ’ / e t c / ld . so . conf ’
See any opera t ing system documentation about shared l i b r a r i e s formore informat ion , such as the ld (1 ) and ld . so (8 ) manual pages .
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Build-in Utility (ld) Installation The build-in utility can be downloaded from.http : // f t p . gnu . org /gnu/ b i n u t i l s /
Install process (May need to update library path beforehand):c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/bin_jmakemake i n s t a l l
Python 2.7 Installation The python can be downloaded from:https : //www. python . org /downloads/
Install process:. / c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/python27makemake i n s t a l lse tenv PYTHONHOME /work/ j−chen/ junc_bin/python27setenv PYTHONPATH /work/ j−chen/ junc_bin/python27/ l i b /setenv PATH /work/ j−chen/ junc_bin/python27/bin / :$PATHpushd /work/ j−chen/ junc_bin/python27/ l i b /python2 .7/ s i t e−packages /ln −s / usr / l i b 6 4 /python2 .6/ s i t e−packages /* .
Install pip for python 2.7.13. By default, pip is not install, you need to run below command:python −m ensurep ip −−default−pip
gcc installation Latest gcc version is 7.22. From 2017/2/2, the gcc supports RISC-V ISA. The package can bedownloaded at:
https : // gcc . gnu . org /The install command:
c on f i gu r e −−p r e f i x=/work/ j−chen/ junc_bin/gcc_j −−with−gmp=/work/ j−chen/ junc_bin/gmp_j/ −−with−mpfr=/work/ j−chen/ junc_bin/mdfr −−with−mpc=/work/ j−chen/ junc_bin/mpc −−d i sab l e−mu l t i l i bmakemake i n s t a l l
In the cshrc file, add:setenv LD_LIBRARY_PATH /work/ j−chen/ junc_bin/gcc_j/ l i b 6 4 : / work/ j−chen/ junc_bin/mpc/ l i b : / work/ j−chen/ junc_bin/gmp_j/ l i b : / work/ j−chen/ junc_bin/mdfr/ l i b :$LD_LIBRARY_PATHsetenv PATH /work/ j−chen/ junc_bin/gcc_j/bin :$PATH
title
Synopsys Open Utility The customSim provides newer version of gcc/ld under:/eda /6/ synopsys /xa_vM−2017.03/GNU/ l inux64 /
Update Library Setting To update related library to newest version, run below commandin c s h e l l :s e tenv LD_LIBRARY_PATH /work/ j−chen/ junc_bin/mpc/ l i b :
/work/ j−chen/ junc_bin/gmp_j/ l i b :/work/ j−chen/ junc_bin/mdfr/ l i b :$LD_LIBRARY_PATH
setenv PATH /work/ j−chen/ junc_bin/bin_j/bin :$PATH
In b s h e l l :export LD_LIBRARY_PATH= /work/ j−chen/ junc_bin/mpc/ l i b : / work/ j−chen/ junc_bin/gmp_j/ l i b : / work/ j−chen/ junc_bin/mdfr/ l i b :$LD_LIBRARY_PATH
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15.3 TexStudio SettingThis section tells some very useful tricks when using Texstudio for Latex editing.
• Disable ’ESC’ shortcut in Options->Config TexStudio->view->close something
• Add macros so that you can short hand many thing like table code etc.
• Add a picture, copy a picture in windows, and paste here. or setup short-key ctrl-T
• Add a new table, set new shortcut for Wizards->table
• to keep indention, change Options -> Editor -> Indentation Mode to ”Keep Indentation”.
• to support 日本語 中文, select XeLeTax as builder, and add below setting in the file: \usepackagexeCJK
15.4 Putty SettingBetter to X11 before putty start. use bufo as default, aoba as backup. You can use gvim and other gui tools in bufo.
Figure 43: Putty Setting
15.5 Reference:http://www.vim.org/download.php#unix
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16 Git Development16.1 Background of gitThis section is based on below ref:https://git-scm.com/book/en/v2
16.1.1 Difference between git and perforce
snapshoot based version Perforce is file based, which stores list of changes on each file. e.g., You can use belowcommand to see change list
p4 f i l e l o g some_code_fi le . c
While git will take snapshoot for each submit, for efficiency, git will merely make a link for unchanged files.
client organization In git every thing is local, means even change history is local. git is designed for work off-line.Where perforce have to work with server.You can commit all your changes locally, until connection is valid. Therefore git is design with two steps, commitand push.
server data organization Git generally only adds data. you can regularly push database into repository. (re-member, for unchanged part, link cost is very small)
three states flow Since some data under working directory is private or sensitive, git uses three states to controlpull/push.
Figure 44: git working tree
The basic Git workflow goes something like this:
• You modify files in your working tree.
• You selectively stage just those changes you want to be part of your next commit, which adds only thosechanges to the staging area.
• You do a commit, which takes the files as they are in the staging area and stores that snapshot permanentlyto your Git directory.
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16.1.2 git configuration
Three level configuration file:
• Global, level 0: /etc/gitconfig
• User, level 1: ~/.gitconfig or ~/.config/git/config
• Local, level 3: $working_dir/.git/config
Where higher level override lower level.
Step 1: Setup identity :By creating:
$ g i t c on f i g −−g l oba l user . name ”JohnDoe”$ g i t c on f i g −−g l oba l user . emai l johndoe@example . com
Step 2: Setup editor :In unix, run following:
g i t c on f i g −−g l oba l core . e d i t o r gvim
In windows, run following:
g i t c on f i g −−g l oba l core . e d i t o r ” ’/G/Program\ F i l e s /Vim/vim80/gvim . exe ’ −mul t i In s t −nos e s s i on ”
Step 3: Customize setting :Check git configuration by:
g i t c on f i g −− l i s tg i t c on f i g user . name
or d i r e c t l y run ( in l i nux ) :vim ~/. g i t c o n f i g
or d i r e c t l y run ( in windows ) :C: / Users / junc / . g i t c o n f i g
Alias setting in configure file:
[ user ]name = jun chenemai l = chen_jun_1982@163 . com
[ http ]s s l v e r i f y = f a l s e
[ a l i a s ]s t = s ta tu scmt = commit −mlp = log −ppu l l o = pu l l o r i g i npusho = push o r i g i nr ev e r t = checkout −− .f l u s h = ! g i t rm −r −−cached . && g i t add .
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Step 4: ignore files :Create .gitignore file:
$ cat . g i t i g n o r e* . [ oa ]i t_con f i g . i n i. s e s s i o n . bak*~# i gno r e a l l f i l e s in the bu i ld / d i r e c t o r ybu i ld /
# i gno r e doc/ notes . txt , but not doc/ s e r v e r / arch . txtdoc/* . t x t
# ignore a l l . pd f f i l e s in the doc/ d i r e c t o r y and any o f i t s s u b d i r e c t o r i e sdoc/**/ * . pdf
A complete ignore template can be found at:https://github.com/github/gitignore
After updating the ignore files, you must run below steps to refresh ignore files:
g i t rm −r −−cached .g i t add .(Or , use a l i a s ’ g i t f l u s h ’ )g i t commit −m ” f i x ed untracked f i l e s ”
If there is file you really want to add to server as template, run:
g i t add −f k e y f i l eg i t commit −m ” f o r c e add template ”
Step 5: token setup :Setup ssh token will speed-up develop process greatly. Otherwise, each check-in will require user-name and password.Creation process can be found at:https://gitlab.com/profile/keys
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16.1.3 Basic usage
Step 1: initial :
a . For a new l o c a l p r o i e c t :cd /c/ user /my_projectg i t i n i t
b . To c lone from a ex i s tng p r o j e c t :g i t c l one https : // g i t hub . com/ l i b g i t 2 / l i b g i t 2 my l i b g i t
Note: DO USE HTTPS connection!
Step 2: add file :
g i t add * . cg i t add LICENSEg i t commit −m ’ i n i t i a l p r o j e c t ve r s i on ’
Note: git add will create a stage automatically. Therefore remember to commit right after git add.
Step 3: check status :This command will help you track the git changes.
g i t s t a tu s(work with g i t add )
This command will show the difference:g i t d i f f −−staged
Step 5: remove and move changes :Remove file by :
g i t rm p r o j e c t s .md( remove f i l e in s tage area and l o c a l )
g i t rm −−cached README( only remove in the s tage area )
$ g i t rm log /\* . l og( remove pat t e rns )
Move file by:$ g i t mv f i l e_ f rom f i l e_ t o
Step 6: commit changes :By perform git commit
g i t commit ( This w i l l launch a ed i t o r for message input )
g i t commit −m ”Story 182 : Fixbenchmarks f o r speed ”( This w i l l use −m message )
g i t commit −a −m ’ addednewbenchmarks ’( This w i l l s tage a l l the changed f i l e s to the commit )( g i t add can be skiped , convenient but dangerous ! )
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16.1.4 Branch maintenance
check branch change log :
$ g i t c l one https : // g i t hub . com/schacon/ s imp l e g i t−p r o g i t$ g i t l og
Other detailed can be found:https://git-scm.com/book/en/v2/Git-Basics-Viewing-the-Commit-History
roll back with branch :
g i t checkout −− .( This command i s dangerous , s i n c e i t f o r c e change the f i l e s )
list remote info :Below command show your remotes:
$ g i t remoteo r i g i n
$ g i t remote −vo r i g i n https : // g i t hub . com/schacon/ t i c g i t ( f e t c h )o r i g i n https : // g i t hub . com/schacon/ t i c g i t ( push )
Sync with remote :Basically, sync with remote branches includes three steps, select branch, get content from branch, then merge conflicts.
%> g i t checkout loca lBranch%> g i t pu l l o r i g i n master%> g i t branch
To sync from remote without merge,
%> g i t checkout loca lBranch%> g i t f e t ch o r i g i n remoteBranch
To sync from remote git and do merging:
g i t pu l l
To submit to remote git:
$ g i t push o r i g i n master
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16.2 git hubMore detailed usage can be found in below link:https://git-scm.com/book/en/v2/GitHub-Account-Setup-and-Configuration
16.2.1 Core git setup flow:
#s tep 1 :setup github account
#s tep 2 :f o rk a new branch from author ’ s g i t p r o j e c t
#step 3 :g i t c l one the p r o j e c t to l o c a l
#step 4 :F i r s t : do the ed i t i n g with g i t add , g i t commit , and g i tpushSet g i t c on f i g by : ( fo rked ssh format )g i t remote set−u r l o r i g i n git@github . com : eva08/OpenRAM. g i t
$step 5 :c l i c k pu l l r eque s t on the author ’ s p r o j e c t
16.2.2 Github useful commands:
# To c r ea t e a new c l i e n tg i t c l one https : // g i t hub . com/mguthaus/OpenRAM. g i t
# To sync new changesg i t pu l l
# To add a new f i l eg i t add readme . txt
# To check c l i e n t s t a tu sg i t s t a tu s
# To check change logg i t l og
# To commit changesg i t commit −m ”This i s my f i r s t commit v ia Git ! ”
Git submodule commands:
# remove a submoduleg i t rm r i s cv−t o o l s −f
16.2.3 Sync fork from original branch
1 . Clone your f o rk :g i t c l one git@github . com :YOUR−USERNAME/YOUR−FORKED−REPO. g i t
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2 . Add remote from o r i g i n a l r e p o s i t o r y in your forked r epo s i t o r y :cd in to / c loned / fork−repog i t remote add upstream g i t : // g i t hub . com/ORIGINAL−DEV−USERNAME/REPO−YOU−FORKED−FROM. g i tg i t f e t ch upstream
3 . Updating your f o rk from o r i g i n a l repo to keep up with t h e i r changes :g i t pu l l upstream master
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16.3 Git labGit lib can be used as private code volt.Useful development command:
g i t add README.mdg i t commit −m ”Modifyreadme”g i t push −u o r i g i n master
16.4 Basic usageInitializing a repository in an existing directory :
$ g i t i n i t
Add and commit change$ g i t add * . c$ g i t add LICENSE$ g i t commit −m ’ i n i t i a l p r o j e c t ve r s i on ’
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17 Environment Experiences17.1 Python in windowsFor windows python setup. First, you need to download python from:https://www.python.org Then some useful package can be installed by:
python −m pip i n s t a l l numpypython −m pip i n s t a l l s c ipypython −m pip i n s t a l l matplot labpython −m pip i n s t a l l image
Since some packages only work under python2, you may also need to install multiple pythons. Remember to addpath for python :
Figure 45: Add python path
17.2 gvim in windowsIf you installed gvim in windows, it is important to add ”set ff=unix” in _vimrc , so that your script can beexecuted by unix.To edit the vimrc, find in below typical directory:
G: \ Program F i l e s \Vim\_vimrcLocal s c r i p t : source G:/ junc_ut i l / . gvimrc . junc
17.3 mail and calendarThis section covers mail and calendar in pc and mobile. To sync the calendar between outlook and googlecalendar, you need to download google calendar sync in below link: https://google-calendar-sync.en.softonic.com/ For Mail setting, use below link:
https : //www. mail . osaka−u . ac . jp / f i l e s /manual−ma i l c l i e n t . pd f
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Figure 46: Mail setting
17.4 Excel Statistical AnalysisEnable data analysis tool box in excel: https://support.office.com/en-us/article/Use-the-Analysis-ToolPak-to-perform-complex-data-analysis-6c67ccf0-f4a9-487c-8dec-bdb5a2cefab6
17.5 Webex usage experienceWebex is widely used in the company. It’s a commercial software so we can’t use it for free.Flow below steps to use the webex meeting.
Step 1 : Start webex by click the meeting link, in the explorer, download the webex program and run.
Figure 47: Start a webex session
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Step 2 : Setup headphone and microphone, then click OK.(Warn: iPhone wire microphone maybe too quiet... Use mobile phone if possible.)
Figure 48: Setup headphone and microphone
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Step 3 : Connect devices with computer.(Otherwise, you can’t hear or speak even with good devices)
Figure 49: Connect devices with computer
Step 4 : Text message if you need help or discussion. Remember to select ” 全員” for broadcasting.
Figure 50: Text message
Step 5 : Share your window or ppt. There are two approaches, pass the ball, and select ” 共有”
(a) pass the ball (b) share window
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18 Latex format18.1 IEEE conference experienceAlgorithm are presented in two forms:
\ documentclass IEEEtran\usepackage algor ithm , a l go r i thmi c \ begin document\ begin a lgor i thm\ capt ion Algorithm for . . . \ begin a l go r i thmi c [ 1 ]\renewcommand\ a l g o r i t hm i c r e qu i r e \ t ex tb f Input : \renewcommand\ a l go r i thmi c en su r e \ t ex tb f Output : \REQUIRE in\ENSURE out\\ \ t e x t i t I n i t i a l i s a t i o n :\STATE f i r s t statement
\\ \ t e x t i t LOOP Process \FOR $ i = l−2$ to $0$\STATE statements . .\IF ( $ i \ne 0$ )\STATE statement . .\ENDIF\ENDFOR
\RETURN $P$\end a l go r i thmi c \end algor i thm
\enddocument
Which shows:
Figure 51: IEEE algorithm 1
or:
\ usepackage a lgor i thm\usepackage a l go r i thmi c
\ begin a lgor i thm\ capt ion Ca lcu la t e $y = x^n$\ begin a l go r i thmi c \REQUIRE $n \geq 0 \vee x \neq 0$\ENSURE $y = x^n$\STATE $y \ l e f t a r r ow 1$\IF$n < 0$
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\STATE $X \ l e f t a r r ow 1 / x$\STATE $N \ l e f t a r r ow −n$\ELSE\STATE $X \ l e f t a r r ow x$\STATE $N \ l e f t a r r ow n$\ENDIF\WHILE$N \neq 0$\IF$N$ i s even\STATE $X \ l e f t a r r ow X \ times X$\STATE $N \ l e f t a r r ow N / 2$\ELSE[ $N$ i s odd ]\STATE $y \ l e f t a r r ow y \ times X$\STATE $N \ l e f t a r r ow N − 1$\ENDIF\ENDWHILE\end a l go r i thmi c \end algor i thm
Which shows:
Figure 52: IEEE algorithm 2
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equation is typically in below form:
\ begin equat ion \ l a b e l eqn_examplex = \sum\ l imi t s_ i=0ˆz 2ˆ i Q
\end equat ion
. . . as can be seen in (\ r e f eqn_example ) .
19 JUNC Utility19.1 Latex checker core engineObjective :Paper writing and refining requires huge manual works, which is time-consuming for co-authors.A python utility is developed to help authors to perform syntax, format, style check.The utility is highly expansible for local users. User can customize the check rule.The utility can perform the check in 2 seconds, while human might take over 10 minutes for one round proof read.Experiences can be shared in utility.Human can have more time on content writing.
Overall Structure : is shown in below
Figure 53: Latex checker
The utility is written in Python, and check rule dictionary in .cvs format. IEEE extractor is used as separate script.
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Usage :
Figure 54: Usage figure
Check rule format :keyword # warning messageBelow format is copied from rule check dictionary
# This f i l e i s used for texcheck . py to f i nd key words and correspond ing ac t i on .# Sh i f t ’#’ i s d e l im i t e r ( in middle ) , or comment ( at l ine beg inning )# Waive out the ac t i on by : Key word #PASS# Key support r e gu l a r exp r e s s i on : i . e . −> i \ . e \ .# General format : Key word #Action
. . . .(\d HZ|\dHZ)#Warning−Unit : For f requency use ’Hz ’ on l i n e %d(\d hz | \ dhz)#Warning−Unit : For f requency use ’Hz ’ on l i n e %d(\d hZ | \ dhZ)#Warning−Unit : For f requency use ’Hz ’ on l i n e %d(? i )\ bpe r f e c t \b#Warning−Sty l e : Nothing i s ’ p e r f e c t ’ . . . %. . . .
Reference :http://www.cs.columbia.edu/~hgs/etc/writing-style.htmlhttps://www.cs.purdue.edu/homes/dec/essay.dissertation.htmlAnd many helpful feedbacks from professor.
19.2 Mail based latex checkerSince previous version requires Python 3, which is not installed in many case.Therefore, I setup a mail based service.Usage:
• Send email to j-chen@ist
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• Set subject/title to: [eva_paper]
• Add .tex as attachment.
Then a python will return the check result within 5 minutes or so.
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