ECEN326: Electronic Circuits Fall 2017spalermo/ecen326/lecture03_ee326_differential_amps.pdf · ECEN326: Electronic Circuits Fall 2017 Lecture 3: Differential Amplifiers. Announcements

Sam PalermoAnalog & Mixed-Signal Center

Texas A&M University

ECEN326: Electronic CircuitsFall 2017

Lecture 3: Differential Amplifiers

Announcements

• Lab• Use the updated Lab3 specs posted on the

website• Get the actual 326 lab kit from the MSC Bookstore

• HW3 is posted on the website and due 10/4

• Reading• Razavi Chapter 10

2

Agenda

• General considerations

• Bipolar differential pair

• MOS differential pair

• Cascode differential amplifiers

• Common-mode rejection

• Differential pair with active load

3

CH 10 Differential Amplifiers 4

Audio Amplifier Example

An audio amplifier is constructed above that takes on a rectified AC voltage as its supply and amplifies an audio signal from a microphone.


“Humming” Noise in Audio Amplifier Example

However, VCC contains a ripple from rectification that leaks to the output and is perceived as a “humming” noise by the user.

rCC vV

invCCrCCout vARIvVV inDCin vV ,

Desired output signal

Undesired power supply noise component


Supply Ripple Rejection

Since both node X and Y contain the ripple, vr, their difference will be free of ripple.

invYX

rY

rinvX

vAvvvv

vvAv

rv


Ripple-Free Differential Output

Since the signal is taken as a difference between two nodes, an amplifier that senses differential signals is needed.

How can we construct this differential amplifier?

rv


Common Inputs to Differential Amplifier

Signals cannot be applied in phase to the inputs of a differential amplifier, since the outputs will also be in phase, producing zero differential output.

0

YX

rinvY

rinvX

vvvvAvvvAv


Differential Inputs to Differential Amplifier

When the inputs are applied differentially, the outputs are 180° out of phase; enhancing each other when sensed differentially.

Provides twice the output swing of the original amplifier

invYX

rinvY

rinvX

vAvvvvAv

vvAv

2


Differential Signals

A pair of differential signals can be generated, among other ways, by a transformer.

Differential signals have the property that they share the same average value to ground and are equal in magnitude but opposite in phase.


Single-ended vs. Differential Signals

• Single-Ended Signals• Measured with

respect to the common ground

• Reside on one “line” or node

CMoout VtVV sin

• Differential Signals• Measured between two nodes• Reside on two differential “lines” or nodes

CMo VtVV sin1

CMo VtVV sin2

tVVV o sin221

• A single-ended signal is measured with respect to a fixed potential (ground)

• A differential signal is measured between two equal and opposite signals which swing around a fixed potential (common-mode level)

• You can decompose differential signals into a differential mode (difference) and a common-mode (average)

Single-Ended & Differential Signals

122

outoutCMoutoutDM

VVVVVV

Differential SignalSingle-Ended Signal

Single-Ended & Differential Amplifiers

13

• Differential signaling advantages• Common-mode noise

rejection• Higher (ideally double)

potential output swing• Simpler biasing• Improved linearity

• Main disadvantage is area, which is roughly double• Although, to get the same

performance in single-ended designs, we often have to increase the area dramatically

TnGSDD VVV

SwingOutput Max

TnGSDD VVV 2

SwingOutput Max

Common-Mode Level Sensitivity

14

• A design which uses two single-ended amplifiers to realize a differential amplifier is very sensitive to the common-mode input level

• The transistors’ bias current and transconductance can vary dramatically with the common-mode input• Impacts small-signal gain• Changes the output common-mode, which impacts the maximum

output swing

Agenda







15


Differential Pair

With the addition of a tail current, the circuits above operate as an elegant, yet robust differential pair.


Common-Mode Response

2

221

21

EECCCYX

EECC

BEBE

IRVVV

III

VV

simplicityfor 1Assuming

2EEI

2EEI


Common-Mode Rejection

Due to the fixed tail current source, the input common-mode value can vary without changing the output common-mode value.

• Assuming VBC=0 for saturation (VCE~0.7V)• Often we allow for VBC=0.4V or VCE~0.3V and still consider “active” mode

operation, although this is formally “soft saturation”• In any problems, I’ll make it clear what assumptions to use

Lower limit of VCM also occurs due to the requirement of a minimum “compliance” voltage across a real current source


Differential Response I – Big Differential Input

CCY

EECCCX

C

EEC

VVIRVV

III

02

1

EEIV3.1~

Cutoff


Differential Response II – Big Differential Input

CCX

EECCCY

C

EEC

VVIRVV

III

01

2

EEIV3.1~

Cutoff


Differential Pair Characteristics

None-zero differential input produces variations in output currents and voltages, whereas common-mode input produces no variations.

Transistor Currents Output Voltages2

ModeCommon Output EECCC

IRV


Small-Signal Analysis

Since the input to Q1 and Q2 rises and falls by the same amount, and their bases are tied together, the rise in IC1 has the same magnitude as the fall in IC2.

III

III

EEC

EEC

2

2

2

1


Virtual Ground

For small changes at inputs, the gm’s are the same, and the respective increase and decrease of IC1 and IC2 are the same, node P must stay constant to accommodate these changes. Therefore, node P can be viewed as AC ground.

VgIVgI

V

mC

mC

P

2

1

0

21

2

1

Because CC

PmC

PmC

IIVVgI

VVgI


Small-Signal Differential Gain

Since the output changes by -2gmVRC and input by 2V, the small signal gain is –gmRC, similar to that of the CE stage. However, to obtain same gain as the CE stage, power dissipation is doubled.

CmCm

diff

YXv Rg

VVRg

VVVA

2

2

CmY

CmX

mC

mC

VRgVVRgVVgI

VgI

2

1


Large Signal Analysis

2

1

21

2121

2211

22

11

ln

lnln

networkinput thearound KVL a Writing2.

ln

ln

Using1.

C

CT

S

CT

S

CT

BEBEinin

BEinPBEin

S

CTBE

S

CTBE

VV

SC

IIV

IIV

IIV

VVVVVVVVV

IIVV

IIVV

eII TBE


Large Signal Analysis

T

inin

T

ininEE

T

inin

EEC

T

inin

EEC

EECT

ininC

EECC

VVV

VVVI

VVV

II

VVV

II

IIV

VVI

III

21

21

121

212

221

2

21

exp1

exp

exp1

symmetrycircuit From 5.

exp1

exp

KCL ith theequation w KVL previous Combining 4.

Pnodeat KCLa Writing3.

T

inin

EEC

T

inin

T

ininEE

C

VVV

II

VVV

VVVI

I

212

21

21

1

exp1

exp1

exp


Input/Output Characteristics

T

ininEEC

outout

VVVIR

VV

2tanh 21

21

• If Vin1-Vin2 ≥ 4VT = 104mV, the majority of the current is steered through Q1


Linear/Nonlinear Regions

The left column operates in linear region, whereas the right column operates in nonlinear region.


Small-Signal Model

• We can use the virtual GND concept discussed in Slide 24 to simplify this

Virtual GND Proof

300

thatimplieswhich 22

KVL above theusing and ,operation aldifferentiFor

and signals smallFor

0

P nodeat KCL 2.

networksinput thearoundKVL1.

11

11

21

21

2121

222

211

1

1

2211

vvv

vvvvvv

ggrr

vgrvvg

rv

vvvvv

inP

in

inin

mm

mm

inPin


Half Circuits

Since VP is grounded, we can treat the differential pair as two CE “half circuits”, with half the output swing on either side

If the circuit is symmetrical, we can just analyze the half-circuit with a virtual ground to get the gain equation

1outv 2outv

22

11

inCmout

inCmout

vRgvvRgv

Cminin

outout Rgvvvv

21

21


Example: Differential Gain

Ominin

outout rgvvvv

21

21

w/ finite ro


Extension of Virtual Ground

It can be shown that if R1 = R2, and points A and B go up and down by the same amount respectively, VX does not move.

0XV

Symmetry Axis


Half Circuit Example I

1311 |||| RrrgA OOmv

21 RR


Half Circuit Example II

1311 |||| RrrgA OOmv


Half Circuit Example III

mE

Cv

gR

RA 1

simplicityfor 1assuming


Half Circuit Example IV

m

E

Cv

gR

RA1

2

simplicityfor 1assuming

BJT Differential Pair Input Resistance

38

• In order to obtain the differential input resistance, apply a test differential voltage vX and find the developed current iX

rivR

irvvvrvi

rv

X

Xin

XX

X

2 alDifferenti

221

2

2

1

1

Agenda







39


MOS Differential Pair’s Common-Mode Response

Similar to its bipolar counterpart, MOS differential pair produces zero differential output as VCM changes.

2SS

DDDYXIRVVV 2

SSI2SSI


Equilibrium Overdrive Voltage

The equilibrium overdrive voltage is defined as the overdrive voltage seen by M1 and M2 when both carry an ISS/2 current

Larger tail current or smaller W/L results in a larger equilibrium overdrive voltage

LWC

IVVoxn

SSequilTHGS

2

SSI2SSI

22

Saturation Using THGSoxn

D VVLWCI


Minimum Common-mode Output Voltage

In order to maintain M1 and M2 in saturation, the common-mode output voltage cannot fall below the value above.

This value usually limits voltage gain.

THCMSS

DDD VVIRV 2


Differential Response


Small-Signal Response

Similar to its bipolar counterpart, the MOS differential pair exhibits the same virtual ground node and small signal gain.

Dmv

P

RgAV

0


Power and Gain Tradeoff

In order to obtain the source gain as a CS stage, a MOS differential pair must dissipate twice the amount of current (assuming the same MOSFET overdrive voltage). This power and gain tradeoff is also echoed in its bipolar counterpart.


MOS Differential Pair’s Large-Signal Response

2121212

21

212121

2

21

2211

2222sidesboth Squaring

2

2 and 2

Using

node tailat the KCL a Writing2.

networkinput thearound KVL a Writing1.

DDSS

oxn

DDDD

oxn

inin

DD

oxn

GSGSinin

oxn

DTHGSTHGS

oxnD

SSDD

GSinGSin

III

LWC

IIII

LWC

VV

II

LWC

VVVV

LWC

IVVVVLWCI

III

VVVV


MOS Differential Pair’s Large-Signal Response

2212121

212

122

221

211

42

442

442

thatshowcan 10.3.2),Razavi(seeonsmanipulati algebraic someAfter

inin

oxn

SSinin

oxnDD

ininoxnSSoxnininSS

D

ininoxnSSoxnininSS

D

VV

LWC

IVVLWCII

VVLWCI

LWCVVII

VVLWCI

LWCVVII

*Note, this equation is only valid for a certain maximum input differential voltage Vin1 – Vin2


Maximum Differential Input Voltage

There exists a finite differential input voltage that completely steers the tail current from one transistor to the other. This value is known as the maximum differential input voltage.

LWC

IVV

IVVVMM

VV

LWC

IVVLWCII

oxn

SSTHGS

SSGSTHGS

inin

oxn

SSinin

oxnDD

2

value. full a supports and when stops This on. are and both when only valid isequation above The

42

1

12

21

2212121

LWC

IVVVVoxn

SSequilTHGSinin

22max21


Contrast Between MOS and Bipolar Differential Pairs

In a MOS differential pair, there exists a finite differential input voltage to completely switch the current from one transistor to the other, whereas, in a bipolar pair that voltage is infinite.

MOS Bipolar

22121214

2 inin

oxn

SSinin

oxnDoutout VV

LWC

IVVLWCRVV

T

ininEECoutout V

VVIRVV2

tanh 2121


The effects of Doubling the Tail Current

Since ISS is doubled and W/L is unchanged, the equilibrium overdrive voltage for each transistor must increase by to accommodate this change, thus Vin,max increases by as well. Moreover, since ISS is doubled, the differential output swing will double.

Small signal gain also increases by Linear input range increases, assuming RD value is small

enough to keep transistors in saturation

22

2


The effects of Doubling W/L

Since W/L is doubled and the tail current remains unchanged, the equilibrium overdrive voltage will be lowered by to accommodate this change, thus Vin,maxwill be lowered by as well. Moreover, the differential output swing will remain unchanged since neither ISS nor RDhas changed

Small signal gain increases by Linear input range decreases

22

2


Small-Signal Analysis of MOS Differential Pair

When the input differential signal is small compared to 4ISS/nCox(W/L), the output differential current is linearly proportional to it, and small-signal model can be applied.

212121

2212121

224

2

42

ininmininSS

oxn

oxn

SSinin

oxn

inin

oxn

SSinin

oxnDD

VVgVVILWC

LWC

IVVLWC

VV

LWC

IVVLWCII


Virtual Ground and Half Circuit

Applying the same analysis as the bipolar case, we will arrive at the same conclusion that node P will not move for small input signals and the concept of half circuit can be used to calculate the gain.

Cmv

P

RgAV

0

1outv 2outv

22

11

inCmout

inCmout

vRgvvRgv

Small-Signal Impedance:Simple Current Source (Finite ro)

54

oout g

r 1

Small-Signal Impedance:“Diode” Load (Finite ro)

55

momo

mout ggg

rg

r 111

Small-Signal Impedance:Looking Into Source (Finite ro and gmb)

56

mo

mbmombmout

oombmo

oombmo

gr

gggggr

vgggrvvggi

1111

Small-Signal Impedance:Looking Into Source w/ RD (Finite ro and gmb)

57

o

D

ombmout r

Rggg

r 11


MOS Differential Pair Half Circuit Example I

3

113

31 ||||1

0

m

mOO

mmv g

grrg

gA

mo

mout g

rg

r 11


MOS Differential Pair Half Circuit Example II

3

1

0

m

mv g

gA


MOS Differential Pair Half Circuit Example III

mSS

DDv gR

RA122

0

Agenda







61

Maximum Differential Amplifier Gain

• With ideal current source loads, the differential gain is limited by the intrinsic transistor gain (gmro)

• How to increase the gain further?• Use a topology which boosts

the output resistance62

Ominin

outout rgvvvv

21

21

w/ finite ro

Bipolar Cascode Topology

63

o1 3

o3 o

o

m3 x

x

13331333133

33

13133

33

13

0

nodeoutput at the KCL a Writing

oomoomooo

oout

o

o

o

oooomo

o

xoxmo

oox

rrrgrrrgrrrivR

rv

rrri

rrigi

rvvvgi

rriv

The dominant term is the bottom effective resistance boosted by the gain of the top transistor (gm3ro3)


Bipolar Cascode Differential Pair

3133

3133313

rrrg

rrrgrrrR

oom

oomooout

Cascode Output Resistance

31331

31333131

rrrgg

rrrgrrrgA

oomm

oomoomv

• Gain is roughly squared relative to the simple differential pair

• Trade-off is reduced output voltage swing range

Slight approximation here. More when we study Cascodes in detail.


Bipolar Telescopic Cascode

575531331

575557531333131

rrrgrrrgg

rrrgrrrrrrgrrrgA

oomoomm

oomoooomoomv


Example: Bipolar Telescopic Parasitic Resistance

opOOmmv

OOmOOmOop

RrrrggA

RrrrgRrrRrrgrR

||)||(2

||||2

||||2

||||1

31331

15755

157

15755

MOS Cascode Topology

67

13313313

33

113

33

1

0


oomoomooo

oout

o

o

o

oooomo

o

xoxmo

oox

rrgrrgrrivR

rv

rririgi

rvvvgi

riv

The dominant term is the bottom effective resistance boosted by the gain of the top transistor (gm3ro3)

o1

o3 o

o

m3 x

x


MOS Cascode Differential Pair

1331

133131

oomm

oomoomv

rrggrrgrrgA

133

13313

oom

oomooout

rrgrrgrrR

CascodeOutput

Resistance

• Gain is roughly squared relative to the simple differential pair

• Trade-off is reduced output voltage swing range


MOS Telescopic Cascode

)(|| 7551331 OOmOOmmv rrgrrggA


Example: MOS Telescopic Parasitic Resistance

71551331

71557155715

oomoommv

oomoomooop

rRrgrrggA

rRrgrRrgrRrR

Agenda







71


Effect of Finite Tail Impedance

If the tail current source is not ideal, then when a input CM voltage is applied, the currents in Q1 and Q2 and hence output CM voltage will change.

mEE

C

CMin

CMout

gRR

VV

2/12/

,

,

2CR

Assuming =1


Input CM Noise with Ideal Tail Current


Input CM Noise with Non-ideal Tail Current

• Common-mode noise is now transferred to the single-ended outputs• However, output differential signal is still ideally unaffected by common-

mode noise


Comparison

As it can be seen, the differential output voltages for both cases are the same. So for small input CM noise, the differential pair is not affected.


CM to DM Conversion, ACM-DM

If finite tail impedance and asymmetry are both present, then the differential output signal will contain a portion of input common-mode signal.

SSm

D

CM

out

D

SSm

CMout

DDDDDDDoutoutout

SSm

CMD

SSm

DCM

SSDCM

SSD

DDD

o

Rg

RVV

RR

g

VV

RIRRIRIVVV

Rg

VI

Rg

IV

RIVRI

IIIr

21

21

21

21

2V through flow will2 ofcurrent net A

VVV and istorspair trans diff. in the high Assuming

21

GS

GSGS2GS121


Example: ACM-DM

31333131

31

21

21

rRrgrRrg

R

Rg

RVVA

omom

C

outm

C

CM

outDMCM


CMRR

CMRR defines the ratio of wanted amplified differential input signal to unwanted converted input common-mode noise that appears at the output.

C

EECmC

EEm

C

Cm

DMCM

DM

RRRgR

Rg

R

RgA

ACMRR

2

21

CC RR

Agenda







79


Differential to Single-ended Conversion

Many circuits require a differential to single-ended conversion, however, the above topology is not very good.

Simple OpAmp


Supply Noise Corruption

The most critical drawback of this topology is supply noise corruption, since no common-mode cancellation mechanism exists. Also, we lose half of the signal.


Gain Reduction

The most critical drawback of this topology is supply noise corruption, since no common-mode cancellation mechanism exists. Also, we lose half of the signal.

2221

2

1

Cm

in

inCm

inin

out

Cinmout

inin

inin

Rgv

vRgvv

vRvgv

vvvv

inv

inv


Better Alternative

This circuit topology performs differential to single-ended conversion with no loss of gain.

Current Mirror or “Active” Load


Active Load

With current mirror used as the load, the signal current produced by the Q1 can be replicated onto Q4.

This type of load is different from the conventional “static load” and is known as an “active load”.

IIEE 2

~


Differential Pair with Active Load

The input differential pair decreases the current drawn from RL by I and the active load pushes an extra I into RL by current mirror action; these effects enhance each other.

IIEE 2 I2

Lout IRV 2


Active Load vs. Static Load

The load on the left responds to the input signal and enhances the single-ended output, whereas the load on the right does not.

Active Load Static Load

I 2 I I


MOS Differential Pair with Active Load

Similar to its bipolar counterpart, MOS differential pair can also use active load to enhance its single-ended output.

IISS 2

IISS 2

IISS 2

I2

Lout IRV 2


Asymmetric Differential Pair

Because of the vastly different resistance magnitude at the drains of M1 and M2, the voltage swings at these two nodes are different and therefore node P cannot be viewed as a virtual ground.


Thevenin Equivalent of the Input Pair

oNThev

ininoNmNThev

rRvvrgv

2)( 21

To Find RThev


Simplified Differential Pair with Active Load

)||(21

OPONmNinin

out rrgvv

v

oPoNmNinin

out

oP

outThevout

Thev

oPoomPmmThevmom

o

outThevout

Thevom

Thevom

om

m

Thevom

Thevout

o

outAm

Thevout

Thevom

om

A

EA

rrgvv

vrvvv

R

rrrgggRgrg

rvvv

Rrg

Rrg

rg

g

Rrg

vvrvvg

vvRr

g

rg

v

vv

21

4343333

43

33

3

33

4

33

44

33

33

02 and and 1 and 1 since

01

11

1

01


1

1

of version divided a as viewedbecan

Next Time

• Cascode Stages & Current Mirrors• Razavi Chapter 9

91

Documents

ECEN326: Electronic Circuits Fall 2017spalermo/ecen326/lecture03_ee326_differential_amps.pdf · ECEN326: Electronic Circuits Fall 2017 Lecture 3: Differential Amplifiers. Announcements