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Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
ECEN326: Electronic CircuitsFall 2017
Lecture 6: Operational Transconductance Amplifiers (OTAs)
Announcements
• HW4 due today• HW5 due 11/1
2
OpAmps and OTAs
• High voltage gain• High input impedance• Voltage source output
(low impedance)3
OpAmp OTA
• High “voltage” gain• High input impedance• Current source output
(high impedance)
Simple OTA
• Important Parameters• Transconductance• Output Resistance• Differential Gain• Common-Mode Input Range
4
Simple OTA Transconductance: Rigorous Analysis
5
213
21
33
33
4
21
221
1
and find toneed we, find To2 and
3Lecture From
ininm
mnininONmn
ONOm
Om
A
Amp
npsc
ONThevininONmnThev
vvggvvrg
rrg
rg
v
vgi
iiirRvvrgv
mninin
scm
ininmnnpsc
ininmn
mON
ininONmnn
ininmn
Amp
gvv
iG
vvgiii
vvg
gr
vvrgi
vvgvgi
21
21
21
3
21
214
212
2
Simple OTA Transconductance: Informal Virtual Ground Approach
6
• As the differential circuit is not purely symmetric, we cannot formally assume a virtual ground at node P
• However, if the differential pair transistors M1 and M2 have high output resistance, a virtual ground can be approximated at node P to simplify the analysis
mninin
inminm
inin
scm
inminmnpsc
inmp
inmn
gvv
vgvgvv
iG
vgvgiii
vgi
vgi
21
2211
21
2211
11
22
loadmirror current idealan Assuming
Simple OTA Output Resistance
7
onopout
out
OnOpout
ggR
G
rrR
1econductancoutput theuse also tousefuloften isIt
Simple OTA Differential Gain
8
onop
mnOpOnmnv
OpOnmnoutmv
gggrrgA
rrgRGA
Simple OTA Common-Mode Input Range
9
• Common-mode input range set by transistor saturation conditions• Low-end set by tail current source
saturation
1,
15
152
nTH
oxn
SS
oxn
SSGSDSATicm V
LWC
I
LWC
IVVV
• High-end set by differential pair saturation
1,3,
3
1,31, nTHpTH
oxp
SSDDnTHGSDDnTHocmicm VV
LWC
IVVVVVVV
1,5,
3
1,
15
2nTHpTH
oxp
SSDDicmnTH
oxn
SS
oxn
SS VV
LWC
IVVV
LWC
I
LWC
I
Bipolar Simple OTA
10
• Following a similar procedure
opon
mnOpOnmnv
OpOnout
mnm
gggrrgA
rrRgG
• High-end Vicm set by keeping differential pair in active mode
VVVVVV onBEsatCEicm 17.03.0,,
• Low-end Vicm set by keeping tail current source in active mode
VVVVVVVVVVV
CCsatCECCicm
satCEonBEicmonBECCCE
3.0,
,,,1
3 Current Mirror OTA
11
V-I V+
io
M1M1
ITAIL
vO
B : 1 1 : B
1 : 1
MN
MP
2BITAIL
111
11
1
1
mmmsc
m
mmnpsc
mn
mp
Bgvv
vBgvBgvv
iG
vBgvBgiii
vBgi
vBgi
11
1
11 1
OOpmv
oopout
OOpOOp
out
rrgA
ggBG
rrBB
rB
rR
• While Gm has increased by the current mirror factor B, the voltage gain remains the same due to the output resistance being reduced by B-1
• Common-mode input range expression remains the same as the previous simple OTA
Bipolar 3 Current Mirror OTA w/ Degenerated Gm (Lab 7)
12
• In order to improve the distortion performance, emitter resistors have been added in the input differential pair
• In order to improve the output resistance, emitter resistance has been added to all the current mirror/source transistors
1111
1sistorsinput tran theof degnerated by theset is
mirrors,current theallfor ratio1:1aAssuming
EeEem
mm
RrRrG
GG
Bipolar 3 Current Mirror OTA w/ Degenerated Gm (Lab 7)
13
8447844m6478
888
6324633m6246
666
84886366
,g
,g
rRRrrRRRrr
rgg
rRRrrRRRrr
rgg
rRrgrRrgR
EEeEEEe
mm
EEeEEEe
mm
oEomoEomout
Bipolar 3 Current Mirror OTA w/ Degenerated Gm (Lab 7)
14
1112 Eeid RrR
onBEET
satCEBTEEicm VRIVRIVV ,1,3 2
• Low-end Vicm set by keeping tail current source in active mode
• High-end Vicm set by keeping differential pair in active mode
satCEET
CCicm
satCEonBEicmonBEET
CCCE
VRIVV
VVVVRIVV
,2
,,,21
2
2
• Maximum differential input amp. for good distortion
1max, ETid RIv
Simulating the 3 Current Mirror OTA
15
• To simulate differential amplifiers, use voltage-controlled voltage sources (VCVS or “E” elements) to generate the differential input signal and monitor the current through the load resistor
Single-ended input source
2 VCVS to generate differential inputs
DC voltage source to set input DC level
Monitor I(RL)Note: This example is designed for 2X the Lab 7 Gm
Simulating Transconductance
16
Single-ended input sourceDC=0AC=1
Gain=0.5DC voltage source to set input DC level
• Set Inputs E1 Gain=0.5 and E2 Gain=-0.5• With input source AC=1, simply plot the load resistor current I(RL)
to get the transconductance
Gain=-0.5
Monitor I(RL)
Simulating Transconductance
17
• Gm = 2.01mA/V
Simulating Differential Rind
18
• The differential input resistance is equivalent to the differential input (Vi) divided by the input current, where I use the base current of Q1 or IB(Q1)
• Rind = 159k
Simulating THD
19
• Set input source to differential input amplitude spec • For Lab 7, that is 2V
• Check the THD at 3 different common-mode points• 0V, VCM,min, VCM,max
VCM=0V
VCM=-2V
VCM=2V
Simulating Output Resistance
20
Ground input source
• Ground input source and apply an AC-coupled voltage stimulus at output• With output source AC=1, plot the ratio of V(Vout) over the current
through the coupling capacitorOutput stimulus
Simulating Ro
21
• The output resistance is equivalent to the output stimulus V(Vout) divided by the output current, which is equal to the current through the output capacitor I(C5)
• Ro = 25.4k