ECE380 Digital Logic - Mars at UMHBmars.umhb.edu/~wgt/engr3337/lecture_6.pdf · 4-to-2 priority encoder truth table Electrical & Computer Engineering Dr. D. J. Jackson Lecture 22-12

1

Dr. D. J. Jackson Lecture 21-1Electrical & Computer Engineering

ECE380 Digital Logic

Combinatorial Circuit Building Blocks:

Multiplexers


Multiplexers

• A multiplexer (MUX) circuit has– A number of data inputs– One (or more) select inputs– One output

• It passes the signal value on one of its data inputs to its output based on the value(s) of the select signal(s)

0

1

s

x1

x2

f=x1s’+x2s x21x10

f(s,x1,x2)s

2


Multiplexer implementations

x

y f

s

The preferredimplementation


4-input multiplexer

• A 4-input multiplexer ‘selects’ one of four data inputs to be output based on the values of 2 select lines

w0

w1

w2

w3

s0

s1

f

00

01

10

11

w311w201w110w000fs0s1

f=s1’s0’w0+s1’s0w1+s1s0’w2+s1s0w3

3


Building a 4-input MUX

• A 4-input multiplexer can be constructed using 2-input multiplexers

s0

0

1

w0

w1

0

1

w2

w3

0

1

s1

f


MUX application (a 2x2 crossbar)

• A circuit with n inputs and koutputs whose function is to provide a capability to connect any input to any output is called a nxkcrossbar switch– With 2 inputs and 2 outputs,

it is called a 2x2 crossbar– Useful in applications where

it is necessary to connect one set of wires to another set of wires, where the connection pattern changes from time to time

– Telephone switching networks are an example

x1

x2

y1

y2

s

0

1

s

x1

x2

0

1y1

y2

4


0/10/1

MUX application (prog. switch)

• In programmable devices (PLDs, CPLDs and FPGAs) programmable switches connect wires inside the device– These can be implemented with multiplexers

i1

i2

f

An FPGA logic blockwith programmable inputs

i1

i2

f

0/10/1

MUX implementation

storagecell


Logic functions using MUXs

• MUXs can be used to synthesize logic functions– The LUT implementations use MUXs to select a (constant)

value from a look-up table

• Consider the XOR function

011101110000fba

0

1

1

0

a

b

f

00

01

10

11

5



• The previous XOR solution is not particularly efficient

011101110000fba

when a=0, f=b

when a=1, f=b’b’1b0fa

0

1

a

bf



• Implement the following with a 2-input MUX and any additional logic gates

111001110100fba

6



• A 3-input XOR can be implemented with two 2-input MUXs

0101

0110

1001

0011

1

0

0

0

x

111

101

110

000

fzy

y⊕z

(y⊕z)’

z

f

0

1

y

0

1

x



• Implement the following with 2-input MUXs and any additional logic gates

0101

1110

1001

0011

1

0

0

0

x

111

001

110

100

fzy

7


Shannon’s expansion theorem

• Any Boolean function f(w1,…,wn) can be written in the formf(w1,…,wn)=(w1)’ ⋅ f(0,w2,…,wn)+(w1) ⋅ f(1,w2,…,wn)

• The expansion can be done using any of the n variables

• If f(w1,w2,w3)= w1w2+w1w3+w2w3– Expanding this in terms of w1 gives

f(w1,w2,w3)= w1(w2+w3)+(w1)’(w2w3)

f when w1=1 f when w1=0


Shannon’s expansion example

0 0

0 1

1 0

1 1

0

0

0

1

0 0

0 1

1 0

1 1

0

1

1

1

w 1 w 2 w 3 f

0

0

0

0

1

1

1

1

0 1

f w 1 w 2 w 3

w 2 w 3 +

f w

3

w 1 w

2

8



1101

1110

1001

0011

1

0

0

0

x

011

001

110

100

fzy f=x’y’z’+x’y’z+x’yz+xy’z’+xy’z

choose x as the expansion variable

f=x’(y’z’+y’z+yz)+x(y’z’+y’z)f=x’(y’+z)+x(y’)

f

x z

y



1101

1110

1001

0011

1

0

0

0

x

011

001

110

100

fzy f=x’y’z’+x’y’z+x’yz+xy’z’+xy’z

choose z as the expansion variable

1




Decoders, Demultiplexers, Encoders and Code Converters


Decoders

• Decoder circuits: decode encoded information• A binary decoder has n data inputs and 2n outputs• Only one output is asserted at any time (one-hot

encoded) and each output corresponds to one valuation of the inputs

• An enable input (En) is used to disable the outputs– If En=0, none of the decoder outputs is asserted– If En=1, one of the outputs is asserted according to the

valuation of the inputs

w0

wn-1

y0

y2n-1Enable

ninputs

2n

outputs

En

2


2-to-4 decoder circuit

0

0

0

0

1

y0

0

0

0

1

0

y1

0

0

1

0

0

y2

1111

0

1

1

1

En

0XX

001

010

000

y3w0w1

w0

w1

y0

Enable En

y1y2

y3

Truth table

w 1

w 0 y

0

y 1

y 2

y 3

En


3-to-8 decoder

w0

w1

En

y0

y1y2

y3

w0

w1

y0En

En

y1y2

y3

y0

y1y2

y3

y4

y5y6

y7

w0

w1

w2

3


74138 3-to-8 decoder

Note the ‘active low’ outputs


Decoder application

• A common decoder application is the decoding of address lines for memory chips

Sel0

Sel1

Sel2m-1

m-t

o-2

md

eco

der 0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

…..

…..

…..

.

.

.

.

.

.

.

.

.

.

a0

a1

am-1

Ad

dre

ss

read

4


Demultiplexers

• A multiplexer multiplexed n data inputs to a single output

• A circuit that performs the opposite, placing the value of a single input onto one for multiple outputs is called a demultiplexer

• An n-to-2n decoder implements a 1-to-ndemultiplexer

w0

w1

y0

Enable En

y1y2

y3Acts as thedata input

Act as theselect inputs


Encoders

• An encoder performs the opposite function of a decoder

• A binary encoder encodes information (data) from 2n inputs into an n-bit code (output)– Exactly one of the inputs should have a value of one– The outputs represent the binary number that identifies

which input is equal to 1

• Encoders reduce the number of bits needed to represent given information

• Practical use: transmitting information in a digital system

5


Encoders

y0

yn-1

w0

w2n-1

noutputs

2n

inputs

A 2n-to-n binary encoder

w 1

w 0

y 0 w

2

w 3

y 1 1

1

0

0

y1

1

0

1

0

y0

0

0

0

1

w0

1

0

0

0

w3

0

1

0

0

w2

0

0

1

0

w1


Priority encoders

• Another useful class of encoders is based on the priority of the input signals

• In a priority encoder, each input has a priority level associated with it

• The encoder outputs indicate the active input that has the highest priority– When an input with a high priority is asserted, the

other lower priority inputs are ignored

6


Priority encoders

• Assume that w0 has the lowest priority and w3has the highest

• The output z indicates when none of the inputs are 1

• Letting– i0=w3’w2’w1’w0

– i1=w3’w2’w1

– i2=w3’w2

– i3=w3

y0=i1+i3, y1=i2+i3z = i1+i2 +i3+i4

1

0

1

0

D

y0

0D0000

1

1

0

0

y1

1

1

1

1

z

X

X

X

1

w0

1

0

0

0

w3

X

1

0

0

w2

X

X

1

0

w1

4-to-2 priority encodertruth table


Code converters

• The purpose of code converter circuits is to convert from one type of input encoding to another type of output encoding

• For example:– A 3-to-8 decoder converts from a binary number

to a one-hot encoding at the output– A 8-to-3 encoder performs the opposite

• Many different types of code converter circuits can be constructed– One common example a a BCD-to7-segment

decoder

7


BCD-to-7-segment decoder

• Converts one binary-coded decimal (BCD) digit into information suitable for driving a digit-oriented display– A vending machine display is an example

• The circuit converts a BCD digit into 7 signals that are used to drive (activate) the segments in the display– Each segment is a small light-emitting diode

(LED), which glows when driven by an electrical signal



w 0

a

w 1

b c d w

2 w 3

e f g

c e

a

g

b f

d

11011011010

11111010110

00001111110

11111110001

0

0

0

1

0

1

e

1

1

0

0

0

1

f

111111100

1

0

1

0

1

d

1

1

0

1

1

c

1

1

1

1

1

b

010000

1

0

1

0

a

1

1

1

0

g

1

0

0

1

w0

1

0

0

0

w3

0

1

0

0

w2

0

0

1

0

w1

8



c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

c e

a

g

b f

d

1




VHDL for Combinational Circuits


Assignment statements

• VHDL provides several types of statements that can be used to assign logic values to signals– Simple assignment statements

• Used previously, for logic or arithmetic expressions

– Selected signal assignments– Conditional signal assignments– Generate statements– If-then-else statements– Case statements

2


Selected signal assignment

• A selected signal assignment allows a signal to be assigned one of several values, based on a selection criterion– Keyword WITH specifies that s is used for the selection

criterion– Two WHEN clauses state that f=w0 when s=0 and f=w1

otherwise– The keyword OTHERS must be used

ARCHITECTURE Behavior OF mux2to1 ISBEGIN

WITH s SELECTf <= w0 WHEN '0',

w1 WHEN OTHERS;END Behavior;


4-to-1 multiplexer VHDL code

ENTITY mux4to1 ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);f : OUT STD_LOGIC );

END mux4to1;


WITH s SELECTf <= w(0) WHEN "00",

w(1) WHEN "01",w(2) WHEN "10",w(3) WHEN OTHERS;

END Behavior;

3


2-to-4 binary decoder VHDL code

ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

En : IN STD_LOGIC;y : OUT STD_LOGIC_VECTOR(0 TO 3));

END dec2to4;ARCHITECTURE Behavior OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN

Enw <= En & w;WITH Enw SELECT

y <= "1000" WHEN "100","0100" WHEN "101","0010" WHEN "110","0001" WHEN "111","0000" WHEN OTHERS;

END Behavior;


Conditional signal assignment

• Similar to the selected signal assignment, a conditional signal assignment allows a signal to be set to one of several values– Uses WHEN and ELSE keyword to define the condition and

actions

ENTITY mux2to1 ISPORT (w0, w1, s : IN STD_LOGIC;

f : OUT STD_LOGIC );END mux2to1;ARCHITECTURE Behavior OF mux2to1 ISBEGIN

f <= w0 WHEN s = '0' ELSE w1;END Behavior;

4


Priority encoder VHDL code

ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);z : OUT STD_LOGIC );

END priority;

ARCHITECTURE Behavior OF priority ISBEGIN

y <="11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00";

z <='0' WHEN w = "0000" ELSE '1';END Behavior;


Generate statements

• Whenever we write structural VHDL code, we often create instances of a particular component– The ripple carry adder was one example

• If we need to create a large number of instances of a component, a more compact form is desired

• VHDL provides a feature called the FOR GENERATE statement– This statement provides a loop structure for

describing regularly structured hierarchical code

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4-bit ripple carry adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;ENTITY adder4 IS

PORT ( Cin : IN STD_LOGIC ;X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;

BEGINstage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;

END Structure ;


4-bit ripple carry adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;ENTITY adder4 IS

PORT ( Cin : IN STD_LOGIC ;X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder4 ;ARCHITECTURE Structure OF adder4 IS

SIGNAL C : STD_LOGIC_VECTOR(0 TO 4) ;BEGIN

C(0) <= Cin ;Cout <= C(4) ;G1: FOR i IN 0 TO 3 GENERATE

stages: fulladd PORT MAP (C(i), X(i), Y(i), S(i), C(i+1)) ;

END GENERATE ;END Structure ;

6


Process statement

• We have introduced several types of assignment statements– All have the property that the order in which they appear in

VHDL code does not affect the meaning of the code

• Because of this property, these statements are called concurrent assignment statements

• VHDL provides a second category of statements, sequential assignment statements, for which the ordering of the statements may affect the meaning of the code– If-then-else and case statements are sequential

• VHDL requires that sequential assignment statements be placed inside another statement, the process statement


Process statement

• The process statement, or simply process, begins with the PROCESS keyword, followed by a parenthesized list of signals called the sensitivity list– This list includes all the signals used inside the process

• Statements inside the process are evaluated in sequential order

• Assignments made inside the process are not visible outside the process until all statements in the process have been evaluated– If there are multiple assignments to the same signal inside a

process, only the last one has any visible effect

7


2—to-1 MUX as a PROCESS


PROCESS ( w0, w1, s )BEGINIF s = '0' THEN

f <= w0 ;ELSE

f <= w1 ;END IF ;

END PROCESS ;END Behavior ;

Sensitivity list,Whenever a list entrychanges, the processis reevaluated(activated)

IF-THEN-ELSE statementto implement the MUXfunction


Priority encoder (IF-THEN-ELSE)


PROCESS ( w )BEGIN

IF w(3) = '1' THENy <= "11" ;

ELSIF w(2) = '1' THEN y <= "10" ;

ELSIF w(1) = '1' THENy <= "01" ;

ELSEy <= "00" ;

END IF ;END PROCESS ;z <= '0' WHEN w = "0000" ELSE '1' ;

END Behavior ;

8


Priority encoder (alternative)


PROCESS ( w )BEGINy <= "00" ;IF w(1) = '1' THEN y <= "01" ; END IF ;IF w(2) = '1' THEN y <= "10" ; END IF ;IF w(3) = '1' THEN y <= "11" ; END IF ;

z <= '1' ;IF w = "0000" THEN z <= '0' ; END IF ;



Implied memory in a PROCESS

ARCHITECTURE Behavior OF c1 ISBEGIN

PROCESS ( A, B )BEGIN

AeqB <= '0' ;IF A = B THEN

AeqB <= '1' ;END IF ;


ARCHITECTURE Behavior OF c1 ISBEGIN

PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;

END IF ;END PROCESS ;

END Behavior ;

A B AeqBA

B AeqB

9


Case statement

• A case statement is similar to a selected assignment statement in that the case statement has a selection signal and includes WHEN clauses for various valuations of the selection signal– Begins with a CASE keyword– Each WHEN clause specifies the statements that

should be evaluated when the selection signal has a specified value

– The case statement must include a when clause for all valuations of the selection signal• Use the OTHERS keyword


2-to-1 MUX with CASE


PROCESS ( w0, w1, s )BEGINCASE s IS

WHEN '0' =>f <= w0 ;

WHEN OTHERS =>f <= w1 ;

END CASE ;END PROCESS ;

END Behavior ;

10


2-to-4 binary decoder with CASE

ARCHITECTURE Behavior OF dec2to4 ISBEGIN

PROCESS ( w, En )BEGIN

IF En = '1' THENCASE w IS

WHEN "00" => y <= "1000" ;WHEN "01" => y <= "0100" ;WHEN "10" => y <= "0010" ;WHEN OTHERS => y <= "0001" ;

END CASE ;ELSE

y <= "0000" ;END IF ;


Documents

ECE380 Digital Logic - Mars at UMHBmars.umhb.edu/~wgt/engr3337/lecture_6.pdf · 4-to-2 priority encoder truth table Electrical & Computer Engineering Dr. D. J. Jackson Lecture 22-12