ECE357: Introduction to VLSI haizhou/357/lec1.pdf¢  ECE357: Introduction to VLSI CAD Prof. Hai Zhou

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  • ECE357: Introduction to VLSI CAD

    Prof. Hai Zhou

    Electrical Engineering & Computer Science

    Northwestern University

    1

  • Logistics

    • Time & Location: MWF 11-11:50 TECH L160

    • Instructor: Hai Zhou haizhou@ece.northwestern.edu

    • Office: L461

    • Office Hours: W 3-5P

    • Teaching Assistant: Chuan Lin

    • Texts: VLSI Physical Design Automation: Theory & Practice, Sait

    & Youssef, World Scientific, 1999.

    • Reference: 2

  • An Introduction to VLSI Physical Design, Sarrafzadeh &

    Wong, McGraw Hill, 1996.

    • Grading: Participation-10% Project-30% Midterm-30% Homework-30%

    • Homework must be turned in before class on each due date, late: -40% per day

    • Course homepage: www.ece.northwestern.edu/~haizhou/ece357

    2

  • What can you expect from the course

    • Understand modern VLSI design flows (but not the details of tools)

    • Understand the physical design problem

    • Familiar with the stages and basic algorithms in physical design

    • Improve your capability to design algorithms to solve problems

    • Improve your capability to think and reason

    3

  • What do I expect from you

    • Active and critical participation

    – speed me up or slow me down if my pace mismatches

    yours

    – “Your role is not one of sponges, but one of whetstones;

    only then the spark of intellectual excitement can

    continue to jump over”

    • Read the textbook

    • Do your homeworks

    – You can discuss homework with your classmates, but

    need to write down solutions independently

    4

  • VLSI (Very Large Scale Integrated) chips

    • VLSI chips are everywhere

    – computers

    – commercial electronics: TV sets, DVD, VCR, ...

    – voice and data communication networks

    – automobiles

    • VLSI chips are artifacts

    – they are produced according to our will ...

    5

  • Design: the most challenging human activity

    • Design is a process of creating a structure to fulfill a requirement

    • Brain power is the scarcest resource

    – Delegate as much as possible to computers–CAD

    • Avoid two extreme views:

    – Everything manual: impossible–millions of gates

    – Everything computer: impossible either

    6

  • Design is always difficult

    A main task of a designer is to manage complexity

    • Silicon complexity: physical effects no longer be ignored

    – resistive and cross-coupled interconnects; signal

    integrity; weak and faster gates

    – reliability; manufacturability

    • System complexity: more functionality in less time

    – gap between design and fabrication capabilities

    – desire for system-on-chip (SOC)

    7

  • CAD: A tale of two designs

    • Target–hardware design

    – How to create a structure on silicon to implement a

    function

    • Aid–software design (programming)

    – How to create an algorithm to solve a design problem

    • Be conscious of their similarities and differences

    8

  • Emphasis of the course

    • Design flow

    – Understand how design process is decomposed into

    many stages

    – What are the problems need to be solved in each stage

    • Algorithms

    – Understand how an algorithm solves a design problem

    – Consider the possibility to extend it

    • Be conscious and try to improve problem solving skills

    9

  • Basics of MOS Devices

    • The most popular VLSI technology: MOS (Metal-Oxide-Semiconductor).

    • CMOS (Complementary MOS) dominates nMOS and pMOS, due to CMOS’s lower power dissipation, high regularity, etc.

    • Physical structure of MOS transistors and their schematic icons: nMOS, pMOS.

    • Layout of basic devices:

    – CMOS inverter

    – CMOS NAND gate

    – CMOS NOR gate

    10

  • MOS Transistors

    n n

    p−substrate

    drain source gate

    insulator (SiO )2

    substrate

    drain source

    gate

    n−transistor schematic icon

    conductor (polysilicon)

    diffusion

    The nMOS switch passes "0" well.

    drain source gate

    insulator (SiO )2

    substrate

    drain source

    gate

    schematic icon

    conductor (polysilicon)

    diffusion

    pp

    n−substrate

    p−transistor

    The pMOS switch passes "1" well.

    11

  • A CMOS Inverter

    A B

    GND

    VDD

    Metal Metal−diffusion contact

    Diffusion

    Polysilicon

    A B 1 0 0 1

    pMOS transistor

    nMOS transistor

    A B

    p−channel (pMOS)

    n−channel (nMOS)

    VDD

    GND

    layout

    12

  • A CMOS NAND Gate

    A

    GND

    VDD

    Metal

    Diffusion

    Polysilicon

    B C

    A B C

    0 0 1 1

    0 1 0 1

    A B

    VDD

    GND

    0

    C

    1 1 1

    layout

    13

  • A CMOS NOR Gate A B C

    0 0 1 1

    0 1 0 1

    A

    B

    VDD

    GND

    0 0

    1

    0

    C

    A

    GND

    VDD

    Metal

    Diffusion

    Polysilicon

    B C

    layout

    14

  • Current VLSI design phases

    • Synthesis (i.e. specification → implementation)

    1. High level synthesis (459 VLSI Algorithmics)

    2. Logic synthesis (459 VLSI Algorithmics)

    3. Physical design (This course)

    • Analysis (implementation → semantics)

    – Verification (design verification, implementation

    verification)

    – Analysis (timing, function, noise, etc.)

    – Design rule checking, LVS (Layout Vs. Schematic)

    15

  • Physical Design

    • Physical design converts a structural description into a geometric description.

    • Physical design cycle:

    1. Circuit partitioning

    2. Floorplanning

    3. placement, and pin assignment

    4. Routing (global and detailed)

    5. Compaction

    16

  • Design Styles

    Different design styles

    Full custom Standard cell Gate array FPGA CPLD SPLD SSI

    Issues of VLSI circuits

    Performance Area Cost Time−to−market

    Performance, Area efficiency, Cost, Flexibility

    17

  • Full Custom Design Style

    Data path

    ROM/RAM

    A/D converter

    I/O PLA

    Controller

    Random logic

    I/O padspins

    over−the−cell routing

    via (contact)

    18

  • Standard Cell Design Style

    D

    D D

    A

    A

    A

    A

    B

    B B

    B B

    C

    C

    Cell A Cell B

    Cell C Cell D Feedthrough Cell

    library cells

    19

  • Gate Array Design Style

    I/O pads

    pins

    prefabricated transistor array

    customized wiring

    20

  • FPGA Design Style

    logic blocks

    routing tracks

    switches Prefabricated all chip components

    21

  • SSI/SPLD Design Style x1 1y x2 y2 x3 y3 x4 y4

    F= i=1 4 xi yi

    x1

    1y

    x2

    y2

    x3

    y3

    x4

    y4

    F

    GND

    Vcc VccVcc

    GNDGND

    74LS86 74LS0074LS02

    x1

    1y

    x2 y2

    x3 y3 x4 y4

    F

    AND array

    OR array

    F

    x1 1y x2 y2

    x3 y3 x4 y4

    (a) 4−bit comparator. (b) SSI implementation.

    (c) SPLD (PLA) implementation. (d) Gate array implementation.

    22

  • Comparisons of Design Styles

    Full Standard Gate custom cell array FPGA SPLD

    Cell size variable fixed height∗ fixed fixed fixed Cell type variable variable fixed programmable programmable Cell placement variable in row fixed fixed fixed Interconnections variable variable variable programmable programmable

    * Uneven height cells are also used.

    23

  • Comparisons of Design Styles

    Full Standard Gate custom cell array FPGA SPLD

    Fabrication time − − − − − + +++ ++ Packing density +++ ++ + − − − − − Unit cost in large quantity +++ ++ + − − − Unit cost in small quantity − − − − − + +++ + Easy design and simulation − − − − − − ++ + Easy design change − − − − − − ++ ++ Accuracy of timing simulation − − − + + Chip speed +++ ++ + − −−

    + desirable − not desirable

    24

  • Design-Style Trade-offs

    1 10 102 103 104 105 10 6

    1

    10

    102

    103

    optimal solution

    SPLD’s CPLD’s

    FPGA’s

    SSI’s

    Logic Capacity (Gates)

    Turnaround Time (Days)

    Full custom

    104

    107

    semi− custom

    25

  • Algorithms 101

    • Algorithm: a finite step-by-step procedure to solve a problem

    • Requirements:

    – Unambiguity: can even be followed by a machine