ECE 410: VLSI Design Course Lecture ??ECE 410: VLSI Design Course Lecture Notes ... Prof. F. Salem Lecture Notes Page 2.5 VLSI Design Flow ... – Analog/mixed signal –

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  • Lecture Notes Page 2.1ECE 410, Prof. F. Salem

    ECE 410: VLSI DesignCourse Lecture Notes

    (Uyemura textbook)

    Professor Fathi Salem

    Michigan State University

    We will be updating the notes this Semester.

  • Lecture Notes Page 2.2ECE 410, Prof. F. Salem

    Electronics Revolution Age of electronics

    microcontrollers, DSPs, and other VLSI chips are everywhere

    Electronics of today and tomorrow higher performance (speed)

    circuits

    low power circuits for portable applications

    more mixed signal emphasis wireless hardware

    high performance signal processing

    Sensors, actuators, and microsystems

    (Digital Camera), Camcorder, PDAs

    MP3/CD Player Laptop Cell phone

    Games: Nintendo; xbox, etc.

  • Lecture Notes Page 2.3ECE 410, Prof. F. Salem

    Figure 1.1 (p. 2)The VLSI design

    funnel.

  • Lecture Notes Page 2.4ECE 410, Prof. F. Salem

    Figure 1.2 (p.4)

    General overview of the design heirarchy.

  • Lecture Notes Page 2.5ECE 410, Prof. F. Salem

    VLSI Design Flow VLSI

    very large scale integration

    lots of transistors integrated on a single chip

    Top Down Design digital mainly

    coded design

    ECE 411

    Bottom Up Design cell performance

    Analog/mixed signal

    ECE 410VLSI DesignProcedure

    System Specifications

    Logic SynthesisChip Floorplanning

    Chip-level Integration

    Manufacturing

    Finished VLSI Chip

    Schematic Design

    LVS(layout vs. schematic)

    Parasitic Extraction

    Post-LayoutSimulation

    Digital CellLibrary

    Mixed-signalAnalog Blocks

    DRC(design rule check)

    Simulation

    Physical Design

    Process ModelsSPICE

    ProcessCharacterization

    ProcessDesign

    Process Capabilitiesand Requirements

    ProcessDesign Rules

    Abstract High-level ModelVHDL, Verilog HDL

    TopDownDesign

    BottomUp

    Design

    Functional Simulation

    Functional/Timing/Performance Specifications

  • Lecture Notes Page 2.6ECE 410, Prof. F. Salem

    Integrated Circuit Technologies Why does CMOS dominate--Now?

    other technologies passive circuits III-V devices Silicon BJT

    CMOS dominates because: Silicon is cheaper preferred over other materials physics of CMOS is easier to understand??? CMOS is easier to implement/fabricate CMOS provides lower power-delay product CMOS is lowest power can get more CMOS transistors/functions in same chip area

    BUT! CMOS is not the fastest technology! BJT and III-V devices are faster

  • Lecture Notes Page 2.7ECE 410, Prof. F. Salem

    Physical Structure of a MOSFET Device

    Schematic Symbol for 4-terminal MOSFET

    Simplified Symbols

    MOSFET Physical View

    source drain

    Substrate, bulk, well, or back gate

    gate

    nMOS pMOS

    critical dimension = feature size

  • Lecture Notes Page 2.8ECE 410, Prof. F. Salem

    CMOS Technology Trends

    Variations over time # transistors / chip: increasing with time

    power / transistor: decreasing with time (constant power density)

    device channel length: decreasing with time

    power supply voltage: decreasing with time

    ref: Kuo and Lou, Low-Voltage CMOS VLSI Circuits, Fig. 1.3, p. 3

    transistors /

    chip

    power /

    transistor

    channel length

    supply voltage

    low power/transistor is critical for future ICs

  • Lecture Notes Page 2.9ECE 410, Prof. F. Salem

    Moores Law In 1965, Gordon Moore realized there

    was a striking trend; each new generation of memory chip contained roughly twice as much capacity as its predecessor, and each chip was released within 18-24 months of the previous chip. He reasoned, computing power would rise exponentially over relatively brief periods of time.

    Moore's observation, now known as Moore's Law, described a trend that has continued and is still remarkably accurate. In 26 years the number of transistors on a chip has increased more than 3,200 times, from 2,300 on the 4004 in 1971 to 7.5 million on the Pentium II processor.

    10m 1m 0.35m 45 nm

    (ref: http://www.intel.com/intel/museum/25anniv/hof/moore.htm)Feature Size

    180 130 90 60 40 30Feature Size (nm)1999 2001 2004 2008 2011 2014

    1.8 V

    1.5 V

    1.2 V

    0.9 V

    0.6 V 0.6 V

    Year

    Power Supply Tends

    Digital Core Voltage Projectionsfrom the 2000 ITRS*

    * http://public.itrs.net/Files/2000UpdateFinal/ORTC2000final.pdf

    2 Billion

  • Lecture Notes Page 2.10ECE 410, Prof. F. Salem

    MOSFET Device-- 1950+ to 2020

    New elements in nano technologies are emerging. These include: Fin-Transistor

    Memristor: memory resistor- see IEEE Spectrum

    Nano-tubes

    Molecular devices

    Quantum dots

    Etc.

    Electronics Building block(s)

  • Lecture Notes Page 2.11ECE 410, Prof. F. Salem

    VLSI Design Flow VLSI

    very large scale integration

    lots of transistors integrated on a single chip

    Top Down Design digital mainly

    coded design

    ECE 411

    Bottom Up Design cell performance

    Analog/mixed signal

    ECE 410VLSI DesignProcedure

    System Specifications

    Logic SynthesisChip Floorplanning

    Chip-level Integration

    Manufacturing

    Finished VLSI Chip

    Schematic Design

    LVS(layout vs. schematic)

    Parasitic Extraction

    Post-LayoutSimulation

    Digital CellLibrary

    Mixed-signalAnalog Blocks

    DRC(design rule check)

    Simulation

    Physical Design

    Process ModelsSPICE

    ProcessCharacterization

    ProcessDesign

    Process Capabilitiesand Requirements

    ProcessDesign Rules

    Abstract High-level ModelVHDL, Verilog HDL

    TopDownDesign

    BottomUp

    Design

    Functional Simulation

    Functional/Timing/Performance Specifications

  • Lecture Notes Page 2.12ECE 410, Prof. F. Salem

    Physical Structure of a MOSFET Device

    Schematic Symbol for 4-terminal MOSFET

    Simplified Symbols

    MOSFET Physical View

    source drain

    Substrate, bulk, well, or back gate

    gate

    nMOS pMOS

    critical dimension = feature size

  • Lecture Notes Page 2.13ECE 410, Prof. F. Salem

    What is a MOSFET? Digital integrated circuits rely on transistor switches

    most common device for digital and mixed signal: MOSFET

    Definitions MOS = Metal Oxide Semiconductor

    physical layers of the device

    FET = Field Effect Transistor

    What field? What does the field do?

    Are other fields important?

    CMOS = Complementary MOS

    use of both nMOS and pMOS to form

    a circuit with lowest power consumption.

    Primary Features gate; gate oxide (insulator) very thin (~10^(-10))-- exaggerated in Fig. source and drain channel bulk/substrate

    Poly

    OxideEEEE

    V

    gate

    insulator

    silicon substrate

    drain- - - - - - - - - - - -channel

    source

    Semi-

    conductor

    NOTE: Poly stands for polysilicon in modern MOSFETs

  • Lecture Notes Page 2.14ECE 410, Prof. F. Salem

    Fundamental Relations in MOSFET

    Electric Fields fundamental equation

    electric field: E = V/d

    vertical field through gate oxide determines charge induced in channel

    horizontal field across channel determines source-to-drain current flow

    Capacitance fundamental equations

    capacitor charge: Q = CV

    capacitance: C = A/d

    charge balance on capacitor, Q+ = Q- charge on gate is balanced by charge in channel

    what is the source of channel charge? where does it come from?

    EEEE

    Vgate

    insulator

    silicon substrate

    drain- - - - - - - - - -

    - -

    channelsource

    Q+Q+

    Q-

    W

    L

    Topview

  • Lecture Notes Page 2.15ECE 410, Prof. F. Salem

    CMOS Cross Section View Cross section of a 2 metal, 1 poly CMOS process

    Layout (top view) of the devices above (partial, simplified)

    Typical MOSFET Device (nMOS)

  • Lecture Notes Page 2.16ECE 410, Prof. F. Salem

    CMOS Circuit Basics

    nMOS

    gategate

    drain

    source

    source

    drain

    pMOS

    CMOS = complementary MOS

    uses 2 types of MOSFETs

    to create logic functions

    nMOS

    pMOS

    CMOS Power Supply

    typically single power supply

    VDD, with Ground reference

    typically uses single power supply

    VDD ranges from (0.6V) 1V to 5V

    Logic Levels (voltage-based)

    all voltages between 0V and VDD

    Logic 1 = VDD

    Logic 0 = ground = 0V

    +-VDD

    VDD

    =CMOSlogiccircuit

    CMOSlogiccircuit

    VVDD

    logic 1

    voltages

    logic 0

    voltages

    undefined

  • Lecture Notes Page 2.17ECE 410, Prof. F. Salem

    Transistor Switching Characteristics nMOS

    switching behavior on = closed, when Vin > Vtn

    off = open, when Vin < Vtn

    pMOS switching behavior

    on = closed, when Vin < VDD - |Vtp|

    off = open, when Vin > VDD - |Vtp|

    Digital Behavior nMOS

    pMOS

    pMOS

    nMOS

    nMOS Vgs > Vtn = on+

    Vgs-

    Vingate

    drain

    source

    Vin

    +Vsg

    -

    gate

    source

    drain

    pMOS Vsg > |Vtp| = on Vsg = VDD - Vin

    Rule to Remembersource is at lowest potential for nMOS highest potential for pMOS

    Vin

    VDDpMOS

    nMOS

    VDD-|Vtp|

    Vtn

    on

    off

    off

    on

    Vin Vout (drain)

    1 Vs=0 device is ON

    0 ? device is OFF

    Vin Vout (drain)

    1