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Množači
Dr Milunka Damnjanović, red.prof,Projektovanje VLSI
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Множење
• Број битова производа је m+n, ако је nброј битова множеника а m број битова множиоца.
• Обично множимо 32-битне бројеве и добијамо 32-битни производ па је могуће прекорачење!
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Множење1000 множеник (multiplicand)
× 1001 множилац (multiplier)1000
00000000
10001001000 производ (product)
• Очигледно, ако је текућа цифра множиоца 1, треба ставити на одговарајуће местомноженик, а када је 0 онда уписујемо нуле наодговарајуће место.
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Множење
• Циљ нам је да хардвер који вршимножење буде оптималан.
• Видећемо три верзије.
• За сада претпостављамо множење самоненегативих бројева.
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Множење
64-bit ALU
Control test
MultiplierShift right
ProductWrite
MultiplicandShift left
64 bits
64 bits
32 bits
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Множење
D o n e
1 . T e s t�M u l t ip lie r0
1 a . A d d m u l t ip li c a n d t o p ro d u c t a n d �p la c e th e re s u lt in P ro d u c t re g is t e r
2 . S h if t th e M u l t ip lic a n d re g is te r le f t 1 b it
3 . S h if t th e M u l t ip lie r re g is te r r ig h t 1 b i t
3 2 n d re p e t it io n ?
S ta r t
M u l t ip lie r0 = 0M u l t ip lie r0 = 1
N o : < 3 2 re p e t i t io n s
Y e s : 3 2 r e p e ti t io n s
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Multiplication• Multiplication can’t be that hard!
– It’s just repeated addition.– If we have adders, we can do multiplication also.
• Remember that the AND operation is equivalent to multiplication on two bits:
a b ab0 0 00 1 01 0 01 1 1
a b a×b0 0 00 1 01 0 01 1 1
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Binary multiplication example
1 1 0 1 Multiplicandx 0 1 1 0 Multiplier
0 0 0 0 Partial products1 1 0 1
1 1 0 1+ 0 0 0 0
1 0 0 1 1 1 0 Product
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A 2x2 binary multiplier
• The AND gates produce the partial products.
• For a 2-bit by 2-bit multiplier, we can just use two half adders to sum the partial products. In general, though, we’ll need full adders
B1 B0
x A1 A0
A0B1 A0B0
+ A1B1 A1B0
C3 C2 C1 C0
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A 4x4 multiplier circuit
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More on multipliers
• Notice that this 4-bit multiplier produces an 8-bit result.– We could just keep all 8 bits.– Or, if we needed a 4-bit result, we could
ignore C4-C7, and consider it an overflow condition if the result is longer than 4 bits.
• Multipliers are very complex circuits. – In general, when multiplying an m-bit number
by an n-bit number:• There are n partial products, one for each bit of the
multiplier.
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Multiplication: a special case• In decimal, an easy way to multiply by 10 is to shift all the digits to
the left, and tack a 0 to the right end.
128 x 10 = 1280
• We can do the same thing in binary. Shifting left is equivalent to multiplying by 2:
11 x 10 = 110 (in decimal, 3 x 2 = 6)
• Shifting left twice is equivalent to multiplying by 4:
11 x 100 = 1100 (in decimal, 3 x 4 = 12)
• As an aside, shifting to the right is equivalent to dividing by 2.
110 ÷ 10 = 11 (in decimal, 6 ÷ 2 = 3)
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Binary Multiplier
• Binary multiplication resembles decimal multiplication:– n-bit multiplicand is multiplied by each bit of
the m-bit multiplier, starting from LSB, to form n partial products.
– Each successive set of partial products is shifted 1 bit to the left.
– Derive result by addition the m rows of partial products.
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Binary Multiplier (cont.)
• Example:– Multiplier A=A1A0 and multiplicand B=B1B0
– Find C = AxB:
B1 B0x A1 A0
A0B1 A0B0+ A1B1 A1B0
C3 C2 C2 C0
-----------------
-------------------------------
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Half Adders are Sufficientsince there is no Carry-inin addition to the two inputsto sum
Binary Multiplier Circuit
2-bit by 2-bit multiplier
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4 bit by 3 bit yields a7 bit result
Binary Multiplier Circuit
4-bit by 3-bit multiplier
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Combinational MultiplierBasic Concept
multiplicand
multiplier
1101 (13)
1011 (11)
1101
1101
0000
1101
*
10001111 (143)
Partial products
product of 2 4-bit numbersis an 8-bit number
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Combinational MultiplierPartial Product Accumulation
A0
B0
A0 B0
A1
B1
A1 B0
A0 B1
A2
B2
A2 B0
A1 B1
A0 B2
A3
B3
A2 B0
A2 B1
A1 B2
A0 B3
A3 B1
A2 B2
A1 B3
A3 B2
A2 B3A3 B3
S6 S5 S4 S3 S2 S1 S0S7
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Combinational MultiplierPartial Product Accumulation
Note use of parallel carry-outs to form higher order sums
12 Adders, if full adders, this is 6 gates each = 72 gates
16 gates form the partial products
total = 88 gates!
A 0 B 0 A 1 B 0 A 0 B 1 A 0 B 2 A 1 B 1 A 2 B 0 A 0 B 3 A 1 B 2 A 2 B 1 A 3 B 0 A 1 B 3 A 2 B 2 A 3 B 1 A 2 B 3 A 3 B 2 A 3 B 3
HA
S 0 S 1
HA
F A
F A
S 3
F A
F A
S 4
HA
F A
S 2
F A
F A
S 5
F A
S 6
HA
S 7
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Množenje označenih brojevaMnoženjem dve n-tobitne celobrojne vrednosti X i Y, kreira se proizvod P koji je obima 2n bitova, P = X*Y. Ako su X i Y označene celobrojne vrednosti, proizvod će biti obima 2n-1 bitova. Strukture množača označenih brojeva razlikuju se u odnosu na strukture množača neoznačenih brojeva. Mi ćemo ukazati samo na neke najstandardnije. Jedna od takvih metoda prikazana je na slici
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Blok dijagram množača označenih brojeva ("sign complemented array multiplier“)
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Princip rada množača označenih brojeva:
• Princip rada je sledeći: Pomoću prekomplementera izvrši se prvo konverzija označenih u neoznačene brojeve. Nakon toga se vrši množenje neoznačenih brojeva. Na kraju, poštujući pravila formiranja znaka, pomoću postkomplementera se vrši konverzija rezultata u označenu vrednost.
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Četvorobitni komplementer dvojičnog komplementa:
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Shift-and-Add Multiplier
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An algorithm for multiplication
(a) Manual method
Multiplicand11
Product
Multiplier10
01
11
11011011
00001011
01 001111
×
Binary
1311×
1313143
Decimal P = 0 ; for i = 0 to n 1 do
if b i = 1 thenP = P + A ;
end if; Left-shift A ;
end for;
(b) Pseudo-code
–
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ASM chart
for the multiplier
Shift left A , Shift right B Done
P P A + ← B 0 = ?
P 0 ←
s
Load A
b 0
Reset
S3
0
1
0
1
0 1
s
S1
S2
1
0
Load B
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Expected behavior of the multiplier
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Datapathfor the
multiplier
E
L E
L E
0 DataA LA
EA
A Clock
P
DataP
RegisterEP
Sum 0
z
B
b 0
DataB LB
EB
+
2n
n n
Shift-leftregister
Shift-right register
n
n
2n 2n
Psel 1 0
2n
2n
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ASM chart for the multiplier control circuit
EP z
b 0
Reset
S3
0
1
0 1
s
0
1
Done
Psel 0 = EP,
s 0
1
S1
S2
Psel 1 = EA EB, ,
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VHDL code of multiplier circuit (1)
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;USE work.components.all ;
ENTITY multiply ISGENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ;PORT ( Clock : IN STD_LOGIC ;
Resetn : IN STD_LOGIC ;LA, LB, s : IN STD_LOGIC ;DataA : IN STD_LOGIC_VECTOR(N–1 DOWNTO 0) ;DataB : IN STD_LOGIC_VECTOR(N–1 DOWNTO 0) ;P : BUFFER STD_LOGIC_VECTOR(N–1 DOWNTO 0) ;Done : OUT STD_LOGIC ) ;
END multiply ;
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VHDL code of multiplier circuit (2)ARCHITECTURE Behavior OF multiply IS
TYPE State_type IS ( S1, S2, S3 ) ;SIGNAL y : State_type ;SIGNAL Psel, z, EA, EB, EP, Zero : STD_LOGIC ;SIGNAL B, N_Zeros : STD_LOGIC_VECTOR(N–1 DOWNTO 0) ;SIGNAL A, Ain, DataP, Sum : STD_LOGIC_VECTOR(NN–1 DOWNTO 0) ;
BEGINFSM_transitions: PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0’ THENy <= S1 ;
ELSIF (Clock'EVENT AND Clock = '1') THENCASE y IS
WHEN S1 =>IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;
WHEN S2 =>IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;
WHEN S3 =>IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;
END CASE ;END IF ;
END PROCESS;
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VHDL code of multiplier circuit (3)
FSM_outputs: PROCESS ( y, s, B(0) )BEGIN
EP <= '0' ; EA <= '0' ; EB <= '0' ; Done <= '0' ; Psel <= '0';CASE y IS
WHEN S1 =>EP <= '1‘ ;
WHEN S2 =>EA <= '1' ; EB <= '1' ; Psel <= '1‘ ;IF B(0) = '1' THEN
EP <= '1' ; ELSE
EP <= '0' ; END IF ;
WHEN S3 =>Done <= '1‘ ;
END CASE ;END PROCESS ;
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VHDL code of multiplier circuit (4)
- - Define the datapath circuitZero <= '0' ;N_Zeros <= (OTHERS => '0' ) ;Ain <= N_Zeros & DataA ;
ShiftA: shiftlne GENERIC MAP ( N => NN )PORT MAP ( Ain, LA, EA, Zero, Clock, A ) ;
ShiftB: shiftrne GENERIC MAP ( N => N )PORT MAP ( DataB, LB, EB, Zero, Clock, B ) ;
z <= '1' WHEN B = N_Zeros ELSE '0' ;Sum <= A + P ;
- - Define the 2n 2-to-1 multiplexers for DataPGenMUX: FOR i IN 0 TO NN–1 GENERATE
Muxi: mux2to1 PORT MAP ( Zero, Sum(i), Psel, DataP(i) ) ;END GENERATE;
RegP: regne GENERIC MAP ( N => NN )PORT MAP ( DataP, Resetn, EP, Clock, P ) ;
END Behavior ;
