Donovan T. Lee

Donovan T. Lee

Integrated Circuit Technology

EE40

6 August 2008

Donovan T. Lee

Integrated Circuit Fabrication

Goal:

Mass fabrication (i.e. simultaneous fabrication) of many “chips”, each a circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors

Methods for Top Down processing:

1. Addition of material

2. Subtraction of unwanted material

3. Thermal/Doping modification of material

Analogous to making Gingerbread men… yeah.

Donovan T. Lee

Still in Infancy: Bottom-up Processing

Cheap electronics

Organic Printed Electronics – Process is serial (slow) and resolution is poor

High-performance transistors

Catalyzed Growth – Nanotubes/Nanowires hard to place and grow in the desired direction.

Donovan T. Lee

• Si substrate – selectively doped in various regions• SiO2 insulator – MOST IMPORTANT component• Polycrystalline silicon – used for the gate electrodes• Metal contacts and wiring

Standard Materials Set

Donovan T. Lee

Si Substrates (Wafers)Why are wafers round?

We pull crystalline-Si out of hot ingots, starting with a seed crystal.

Crystalline-Si exhibits the best electronic properties for transistors.

Typical wafer cost: $50 (!!!)

Sizes: 150 mm, 200 mm, 300 mm diameter

300 mm

“notch” indicatescrystal orientation

Donovan T. Lee

Doping

Makes the Silicon N-type or P-type

Donovan T. Lee

Suppose we have a wafer of Si which is p-type and we want to change the surface to n-type. The way in which this is done is by ion implantation. Dopant ions are shot out of an “ion gun” called an ion implanter, into the surface of the wafer.

Typical implant energies are in the range 1-200 keV. After the ion implantation, the wafers are heated to a high temperature (~1000oC). This “annealing” step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites.

Adding Dopants into Si

Eaton HE3High-Energy Implanter,showing the ion beam hitting theend-station x

SiO2

Si

+ + + +++As+ or P+ or B+ ions

x

SiO2

Si

++ ++ ++ ++++++As+ or P+ or B+ ions

Donovan T. Lee

e.g. AsH3 gaseous sourceAs+, AsH+, H+, AsH2

+

Ionsource

translationalmotion

As+

accelerator

Energy: 1 to 200 keVDose: 1011 to1016/cm2

Inaccuracy of dose: <0.5%Nonuniformity: <1%Throughput: ~60 wafers/hr

ion beam

wafer

spinning waferholder

Ion Implanter

F = q( v B )

analyzer magnet

resolving aperture

Donovan T. Lee

Dopant Diffusion• The implanted depth-profile of dopant atoms is peaked.

• In order to achieve a more uniform dopant profile, high-temperature annealing is used to diffuse the dopants

• Dopants can also be directly introduced into the surface of a wafer by diffusion (rather than by ion implantation) from a dopant-containing ambient or doped solid source

dopant atomconcentration(logarithmic scale)

as-implanted profile

depth, x

Donovan T. Lee

Annealing

Fixes the damage caused by ion implantation.

Donovan T. Lee

Rapid Thermal Annealing (RTA)Sub-micron MOSFETs need ultra-shallow junctions (xj<50 nm)

Dopant diffusion during “activation” anneal must be minimized Short annealing time (<1 min.) at high temperature is required

• Ordinary furnaces (e.g. used for thermal oxidation and CVD) heat and cool wafers at a slow rate (<50oC per minute)

• Special annealing tools have been developed to enable much faster temperature ramping, and precise control of annealing time– ramp rates as fast as 200oC/second– anneal times as short as 0.5 second– typically single-wafer process chamber:

Donovan T. Lee

Rapid Thermal Annealing Tools• There are 2 types of RTA systems:

1. Furnace-based • steady heat source + fast mechanical wafer transport

2. Lamp-based• stationary wafer + time-varying optical output from lamp(s)

Lamp RTA

Furnace RTA

A.T. Fiory, Proc. RTP2000

Donovan T. Lee

Film Growth

Allows formation of high-quality films (usually SiO2) necessary for low

leakage.

Donovan T. Lee

Formation of Insulating Films• The favored insulator is pure silicon dioxide (SiO2).

• A SiO2 film can be formed by one of two methods:

1. Oxidation of Si at high temperature in O2 or steam ambient

2. Deposition of a silicon dioxide film

ASM A412batchoxidationfurnace

Applied Materials low-pressure chemical-vapor deposition (CVD) chamber

Donovan T. Lee

22 SiOOSi Thermal Oxidation

• Temperature range: 700oC to 1100oC

• Process: O2 or H2O diffuses through

SiO2 and reacts with Si at the interface to form more SiO2

• 1 m of SiO2 formed consumes ~0.5 m of Si

oxidethickness

t

ttime, t

222 22 HSiOOHSi or

“dry” oxidation “wet” oxidation

Donovan T. Lee

Thermal oxidation grows SiO2 on Si, but it consumes Si, so the wafer gets thinner. Suppose we grow 1 m of oxide:

Silicon wafer, 100 m thick

Example: Thermal Oxidation of Silicon

99 m thick Si, with 1 m SiO2 all around total thickness = 101 m

99m101m

Donovan T. Lee

Oxidation Rate Dependence on Thickness

• The thermal oxidation rate slows with oxide thickness.

Consider a Si wafer with a patterned oxide layer:

Now suppose we grow 0.1 m of SiO2:

SiO2 thickness = 1 m

SiO2 thickness = 1.02 m SiO2 thickness = 0.1 m

Si

Note the 0.04m step in the Si surface!

Donovan T. Lee

Local Oxidation (LOCOS)Window Oxidation

Selective Oxidation Techniques

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Deposition

Allows you to put down conformal films that cannot be grown from the substrate.

Donovan T. Lee

Chemical Vapor Deposition (CVD) of SiO2

2224 2HSiOOSiH • Temperature range:

350oC to 450oC for silane ~700oC for TEOS

• Process: Precursor gases dissociate at

the wafer surface to form SiO2

No Si on the wafer surface is consumed

• Film thickness is controlled by the deposition time

oxidethickness

t

time, t

OHCSiOOHOHCSi 6222452 42)( or “LTO”“TEOS”

Donovan T. Lee

CVD Properties:

•Can be deposited on top of anything.

•Can follow ups & downs (topography) of pre-existing layers

Conformality

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Lithographic Patterning

Film-camera-like process that lets you define shapes in your thin films.

Donovan T. Lee

Patterning the Layers

Lithography refers to the process of transferring a pattern to the surface of the waferEquipment, materials, and processes needed:• A mask (for each layer to be patterned) with the desired pattern

• A light-sensitive material (called photoresist) covering the wafer so as to receive the pattern

• A light source and method of projecting the image of the mask onto the photoresist (“printer” or “projection stepper” or “projection scanner”)

• A method of “developing” the photoresist, that is selectively removing it from the regions where it was exposed

Planar processing consists of a sequence of additive and subtractive steps with lateral patterning

oxidationdeposition

ion implantation

etching lithography

Donovan T. Lee

Photoresist Exposure• A glass mask with a black/clear pattern is used to

expose a wafer coated with ~1 m thick photoresist

Areas exposed to UV light are susceptible to chemical removal

Mask

UV light

Lens

Si wafer

Image of mask appears here (3 dark areas, 4 light areas)

Mask image is demagnified by nX

“10X stepper”“4X stepper”“1X stepper”

photoresist

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Exposure using “Stepper” Tool

wafer

scribe line

1 2

images

field size increases with technology

generation

Translationalmotion

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Commercial Stepper Tool (ASM Lithography)

Donovan T. Lee

Photoresist Development• Solutions with high pH dissolve the areas which were

exposed to UV light; unexposed areas are not dissolved

Developed photoresist

Exposed areas of photoresist

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Lithography Example

• Look at cuts (cross sections) at various planes

• Mask pattern (on glass plate)

BB

A A

(A-A and B-B)

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“A-A” Cross-Section

The resist is exposed in the ranges 0 < x < 2 m & 3 < x < 5 m:

x [m]0 1 2 3 4 5

resist

resist after development

x [m]0 1 2 3 4 5

maskpattern

x [m]0 1 2 3 4 5

The resist will dissolve in high pH solutions wherever it was exposed:

Donovan T. Lee

In order to transfer the photoresist pattern to an underlying film, we need a “subtractive” process that removes the film, ideally with minimal change in the pattern and with minimal removal of the underlying material(s) Selective etch processes (using plasma or aqueous chemistry) have been developed for most IC materials

Jargon for this entire sequence of process steps: “pattern using XX mask”

photoresist

SiO 2

First: pattern photoresist

Si

We have exposed mask pattern, and developed the resist

etch stops on silicon (“selective etchant”)

oxide etchant … photoresist is resistant.

Next: Etch oxide

only resist is attackedLast: strip resist

Pattern Transfer by Etching

Donovan T. Lee

Photolithographychromiumquartz plate

• 2 types of photoresist:

– positive tone:portion exposed to light will be dissolved in developer solution

– negative tone:portion exposed to light will NOT be dissolved in developer solution

from Atlas of IC Technologies by W. Maly

Donovan T. Lee

Projection Printing Considerations

Small lm is desired!

minimum feature size lm :

Intel’s Lithography Roadmap

Donovan T. Lee

Depth of Focus

Large z is desirable.

depth of focus z :

Donovan T. Lee

Etching

Remove material that you don’t want

Donovan T. Lee

Etching: Ion vs. Wet

better etch selectivity better control of etched feature sizes

from Atlas of IC Technologies by W. Maly

Donovan T. Lee

RIE-based Stringers / Spacers

Leftover material must be removed by overetching

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D’oh! Stringers

Donovan T. Lee

Example Process Flow

CMOS Technology

Donovan T. Lee

Challenge: Build both NMOS & PMOS transistors on a single silicon chip

• NMOSFETs need a p-type substrate

• PMOSFETs need an n-type substrate

Requires extra process steps!

CMOS Technology

oxide

p-welln-type Si

n+ n+p+p+

Donovan T. Lee

oxiden-type wafer

*Create “p-well”

Grow thick oxide

*Remove thick oxide in transistor areas (“active region”)

Grow gate oxide

Deposit & *pattern poly-Si gate electrodes

*Dope n channel source and drains (need to protect PMOS areas)

Deposit insulating layer (oxide)

*Open contact holes

Deposit and *pattern metal interconnects

*Dope p-channel source and drains (need to protect NMOS areas)

→ At least 3 more masks, as compared to NMOS process

Conceptual CMOS Process Flow

p-welln-type Si

n+ n+p+p+

Grow thick oxide

*Remove thick oxide in transistor areas (“active region”)

Donovan T. Lee

Cross-sectional view of wafer

SiO2

n-type Si

1. Well Formation

• Before transistor fabrication, we must perform the following process steps:

1. grow oxide layer; pattern oxide using p-well mask

2. implant phosphorus; anneal to form deep p-type regions

Additional Process Steps Required for CMOS

boron

Top view of p-well mask(dark field)

p-well

Donovan T. Lee

We must protect the n-channel devices during the boron implantation step, and

We must protect the p-channel devices during the arsenic implantation step

“Select n-channel”

photoresist

Example: Select p-channel

2. Masking the Source/Drain Implants

“Select p-channel”

boron

oxide

p-welln-type Si

n+ n+p+p+

Donovan T. Lee

Modify oxide mask and “select” masks:

1. Open holes in original oxide layer, for body contacts

2. Include openings in select masks, to dope these regions

Forming Body Contacts

oxide

p-welln-type Si

n+ n+p+p+ p+n+

Donovan T. Lee

Select MasksN-select:

oxide

p-welln-type Si

n+ n+n+

P-select:

oxide

p-welln-type Si

n+ n+p+p+ p+n+

Donovan T. Lee

Example MEMS Flow

Micro Electro Mechanical Systems

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MEMS Switch

DrainSource Gate(s)

• Contact Areas: 0.4x0.4 um2 to 8x8 um2

• Devices from 50 um to 250 um long

Drain

Donovan T. Lee

Process Flow

Isolation

Elec0 Layer

Si Substrate

Dimple hole

Main Sacrificial (LTO)

Pattern Elec0

Pre-alignment

Isolation Growth 6000A Low Temp Oxide 1000A Stoichiometric Silicon Nitride

Poly 0 Deposition

Poly 0 Formation RIE to isolation w/ overetch

Main Sacrificial Deposition 5500A Low Temp Oxide

Dimple Formation DRIE to Isolation or timed DRIE

Donovan T. Lee

Fine refill sacrificial (HTO)

Anchor holes

Elec1 Layer

Sacrificial Release

Fine Sacrificial Deposition 650A High Temp Oxide

Anchor Formation DRIE to isolation layer

Poly 1 Deposition 5500A @ 615C n-doped Poly 1 Formation RIE etch to Main Sac

Sacrificial Release HF:HCl 20’ then critical pt. dry

Process Finished

Process Flow