EE40 Lec 20 MOS Circuits

Slide 1EE40 Fall 2009 Prof. Cheung

EE40 Lec 20

MOS Circuits

Reading: Chap. 12 of Hambley

Supplement reading on MOS Circuitshttp://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/EE40_MOS_Circuit.pdf


OUTLINE

–Bias circuits–Small-signal equivalent circuits –Examples:Common source amplifier Source follower Common gate amplifier

–Digital Gates–CMOS


Bias Circuits

• Use load line to find Quiescent operating point.• Remember no current flow through the gate.

VDD

RDR1

R2 RS

VDD

RD

VG+vin

Fixed-plus Self-Bias CKT


Steps for MOSFET Circuit Analysis

• 1) Look at DC case to find Q point– Use load line technique– All capacitors are open circuit, Inductors are

short circuit

– Determine Q-point, get gm and rd for small signal AC model

• 2) AC Small signal analysis– DC source is ac ground (because there is no

AC signal variation).– All capacitors are approximated as short

circuit (unless otherwise specified).


Example: Common Source Amplifier

VDD

RDR1

R2 RS C

C

RL

+

-voC

+

-vin

+

-v(t)

VG


Step 1: find Q point

VDD

RDR1

R2 RS C

C

RL

+

-voC

+

-vin

+

-v(t)

VGVDS

2

1 2

( )

G DD

GS G D S

DD D D S DS

RV V

R R

V V I R

V I R R V

Not connectedfor DC component

Not connectedfor DC component


Load line to determine Q Point by graphical method

From load lines, we get ID and hence gm and rd

S

GSGD R

VVI

Loadline to determine VGSQ

S

GSGD R

VVI

S0

DSDDD RR

VVI

S0

DSDDD RR

VVI

Loadline to determine VDSQVGSQ


Load line to determine Q Point by analytical method

From load lines, we get ID and hence gm and rd

2tGSQDQ

S

GSQGDQ

)VV(KI

R

VVI

Solve VGSQ assume saturation region first

IDQ is known, then solve VDSQ

DSQSDDQDD V)RR(IV

Check VDSQ value is consistent with saturation region ( i.e. VDS> VGSQ-Vt)


Determination of gm and rd graphically

Example: Q point is known to be VGS=2.5V, VDS=6V

kror

SiemensV

mA

v

i

r

d

DS

D

d

20

1005.0)214(

)3.29.2(1 3


Determination of gm and rd by Analytical Models

DQDS

Dd

DQtGSGS

Dm

2tGSD

iv

ir/1

iK2)Vv(K2v

ig

)Vv(Ki

factorulationmodchannelL

W

2

KPK

In Saturation Region

In Triode Region

]v2)Vv(2[Kv

ir/1

Kv2v

ig

]vv)Vv(2[Ki

DSQtGSQDS

Dd

DSQGS

Dm

DS2

DStGSD


Small Signal Model

1 2

1 2

, 0

( )

g in s gs in

L Do m gs

L D

o L Dv m

in L D

inin

in

v v v v v

R Rv g v

R R

v R RA g

v R R

v R RR

i R R

For output impedance Rout:1. Turn off all independent

sources.2. Take away load impedance

RL

0, 0, 0in gs m gs

d Dout

d D

v v g v

r RR

r R

Inverting


Example: Source Follower

VDD

R1

R2 RS

C

RL

+

-vo

C

+

-vin

+

-v(t)

VG



2

1 2G DD

GS G D S

DD D S DS

RV V

R R

V V I R

V I R V

VDD

R1

R2 RS

C

RL

+

-vo

C

+

-vin

+

-v(t)

VG


Small Signal Model

1 1 1

1 2

1 2

1

(1 )

1

Ld S L

gs in o

o m gs L

in gs m L

o m Lv

in m L

inin

in

Rr R R

v v v

v g v R

v v g R

v g RA

v g R

v R RR

i R R

For output impedance Rout:1. Turn off all independent sources.2. Take away RL

3. Add Vx and find ix

1

1 1

, 0,

, ( )

1

x s g gs x

d s xs x m x x s m

d s s

outm d s

v v v v v

r R vR i g v v R g

r R R

Rg r R

Non-inverting, Voltage Gain 1Rin highCurrent gain can be high

Rout is small


Example: Common Gate Amplifier

VDD

RD

RS

C

RL

+

-vo

C+

-vin

+

-v(t)

VG

-VSS



VDD

RD

RS

C

RL

+

-vo

C+

-vin

+

-v(t)

VG

-VSS

0

( )GS D S SS

DD SS D D S DS

V I R V

V V I R R V


Load line

The only difference in all three circuits are the intercepts at the axes.Again from load lines, we get ID and hence gm and rd


Small Signal Model

1 1

1

1

( )

1

LL D

gs in

o m gs L

ov m L

in

gsin m gs

s

inin

in m s

RR R

v v

v g v R

vA g R

v

vi g v

R

vR

i g R

For output impedance Rout:1. Turn off all independent sources.2. Take away RL

3. Add Vx and find ix

, 1 0

s

s

xx m gs

D

gs m gs m gs

out D

RRR

R R

vi g v

R

v g v R but g R v

R R

Non-inverting


Logic Gates : Pull-Up and Pull-Down

PMOS or Resistor

NMOS or Resistor


Inverter = NOT Gate

VoutVin

Vin

Vout

VV/2

Ideal Transfer Characteristics


VDD/RD

VDD

NMOS Inverter: Resistor Pull-Up

vDS

iD

0

vOUT

vIN0

VDD

RD

+

vDS = vOUT

–

iD

+

vIN

–

VDD

RD

+

vDS = vOUT

–

iD

+

vIN

–

Circuit: Voltage-Transfer Characteristic

VDD

VT

A F0 11 0

AF

increasingvGS = vIN > VT

vGS = vin VT

vIN = VDD

VDD


NMOS NAND Gate

• Output is low only if both inputs are highVDD

RD

A

B

F

A B F0 0 10 1 11 0 11 1 0

Truth Table


NMOS NOR Gate

• Output is low if either input is highVDD

RD

A B

F

A B F0 0 10 1 01 0 01 1 0

Truth Table


Disadvantages of NMOS Logic Gates

• Large values of RD are required in order to

– achieve a low value of VLOW– keep power consumption low

Large resistors are needed, but these take up a lot of space.


CMOS Inverter: Intuitive Perspective

VDD

Rn

VIN = VDD

CIRCUIT SWITCH MODELS

VDD

Rp

VIN = 0 V

VOUT VOUT

VOL = 0 V VOH = VDD

Low static power consumption, sinceone MOSFET is always off in steady state

VDD

VIN VOUT

S

D

G

G S

D


The CMOS Inverter: Current Flow

VIN

VOUT

VDD

VDD00

N: offP: lin

N: linP: off

N: linP: sat

N: satP: lin

N: satP: sat

A B D E

C

ii

I

S

D

G

GS

D

VDD

VOUTVIN


Power Dissipation: Direct-Path Current

VDD-VT

VT

time

vIN:

i:

Ipeak

VDD

0

0

i

S

D

G

GS

D

VDD

vOUTvIN

peakDDscdp IVtE Energy consumed per switching period:

tsc


CMOS NAND Gate

A B F0 0 10 1 11 0 11 1 0

A

F

B

A B

VDD

Notice that the pull-up network is related to the pull-down network by DeMorgan’s Theorem!

NMOS, Pull-down PMOS, Pull-up


CMOS NOR Gate

A

F

B

A

B

VDD A B F0 0 10 1 01 0 01 1 0

Notice that the pull-up network is related to the pull-down network by DeMorgan’s Theorem!

NMOS, Pull-down PMOS, Pull-up


Multiple Input NOR Gate


Features of CMOS Digital Circuits

• The output is always connected to VDD or GND in steady state Full logic swing; large noise margins Logic levels are not dependent upon the relative sizes of the

devices (“ratioless”)

• There is no direct path between VDD and GND in steady state no static power dissipation

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EE40 Lec 20 MOS Circuits