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Design Techniques for Analog PLLs: Moving Beyond Classical Topologies
CICC 2010
Michael PerrottSeptember 2010
Copyright © 2010 by Michael H. PerrottAll rights reserved.
2
What is a Phase-Locked Loop (PLL)?
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
ref(t)
out(t)
e(t) v(t)
ref(t)
out(t)
e(t) v(t)
de BellescizeOnde Electr, 1932
VCO efficiently provides oscillating waveform with variable frequency
PLL synchronizes VCO frequency to input reference frequency through feedback- Key block is phase detector
Realized as digital gates that create pulsed signals
3
Integer-N Frequency Synthesizers
Use digital counter structure to divide VCO frequency- Constraint: must divide by integer values
Use PLL to synchronize reference and divider output
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
ref(t)
div(t)
e(t) v(t)
Divider
N
Fout = N Fref
div(t) Sepe and JohnstonUS Patent (1968)
Output frequency is digitally controlled
4
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
Divider
N[k]
Fout = M.F Fref
div(t)
Nsd[k] Σ−ΔModulator
M.F
ref(t)
div(t)
e(t) v(t)
Fractional-N Frequency Synthesizers
Dither divide value to achieve fractional divide values- PLL loop filter smooths the resulting variations
Very high frequency resolution is achieved
WellsUS Patent (1984)
RileyUS Patent (1989)
JSSC ‘93
Kingsford-SmithUS Patent (1974)
5
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
Divider
N[k]
Fout = M.F Fref
div(t)
Nsd[k] Σ−ΔModulator
M.F
ref(t)
div(t)
e(t) v(t)
f
Σ−Δ Quantization Noise
The Issue of Quantization Noise
Limits PLL bandwidth Increases linearity requirements of
phase detector
6
Analog Phase Detection
Phase detector varies pulse width with phase error Loop filter smooths pulses to extract average value
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
Reg
D Q
ref(t)
div(t)
phase errorD Q
reset
1
1
ref(t)
error(t)
div(t)
error(t)
Dividerdiv(t)
7
Issues with Analog Loop Filter
Charge pump: output resistance, mismatch, noise, leakage- Analog design requires significant effort, hard to port
RC Network: large area
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
error(t)Icp
VoutCharge
Pump
Cint
Divider
8
Should We Go All Digital ?
Digital loop filter: compact area, digital flow Issue: difficult to achieve low area and power in older
processes such as 0.18u CMOS- May not be worth the effort unless advanced CMOS available
Staszewski et. al.,TCAS II, Nov 2003
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
Time
-to-
Digital
out(t)ref(t) Digital
Loop Filter
DCO
Divider
Divider
Can We Achieve an Analog PLL with Lower Design Complexity and Adequate Performance?
10
Outline
Background information on traditional analog PLL implementations and analysis
Moving away from the traditional approach- XOR-based phase detection- Switched resistor loop filter- Switched capacitor frequency detection
MEMS oscillator example
11
ref(t)
out(t)
error(t)
Phase Detector
Characteristic
Phase Detector Signals
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
phase error
Ave
rag
e o
ferr
or(
t)
Key Characteristics of a Phase Detector
Adequate phase detection range- Fractional-N PLLs need more range than Integer-N PLLs
Linearity across operating range of phase detector- Fractional-N PLLs have issues with noise folding
12
XOR Phase Detector
Creates pulse widths that vary according to the phase difference between reference and divider output signals
Simple implementation Divide-by-2 is used to
eliminate impact of falling edges- Duty cycle of Ref(t) and
Div(t) signals is no longer of concern
D
Q
Q
D
Q
Q
Ref/2(t)
Div/2(t)
Ref(t)
Div(t)
e(t)
Divide-by-2
Ref(t)
Div(t)
Ref/2(t)
Div/2(t)
e(t)
13
Modeling of XOR Phase Detector
Average value of pulses is extracted by loop filter- Look at detector output over one cycle:
Equation:
Notice that the average error is a linear functionof the pulse width W regardless of mismatch
T
W
1
-1
e(t)
14
Overall XOR Phase Detector Characteristic
Ref/2(t)
Div/2(t)
Ref(t)
Div(t)
0
e(t)
2π 4π
avg{e(t)}
Φref(t) - Φdiv(t)
Gain flips in sign according to phase error region of phase detector
15
Assume phase difference is confined to same slope region- XOR PD model becomes a highly linear gain element
Corresponding frequency-domain model
Modeling of XOR Phase Detector
Φref(t) - Φdiv(t)2ππ-π-2π 0
avg{e(t)}
1
-1
phase detector
range = 2π
gain = 1/πgain = -1/π
Ref(t)PD
e(t)
PD gainDiv(t)
Φref(t)
Φdiv(t)
1π
e(t)
16
Overall PLL Model with XOR Phase Detector
Define A(f) as open loop response
Define G(f) as a parameterizing closed loop function
- Where Kpd is defined as PD gain (1/ for XOR PD)
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
KvKpd
XOR PD: Kpd =1π
17
Key Properties of G(f) Function
G(f) always has a DC gain of 1- True since A(f) goes to infinity as f goes to 0
G(f) is lowpass in nature- True since A(f) goes to 0 as f goes to infinity
G(f) has bandwidth close to unity gain frequency of A(f)
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
KvKpd
XOR PD: Kpd =1π
18
Closed Loop Response From Ref to PLL Output
Lowpass with DC gain of N
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
KvKpd
XOR PD: Kpd =1π
19
Closed Loop Response From PD to PLL Output
Lowpass with DC gain of N/Kpd
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
Kv
en(t)
Kpd
XOR PD: Kpd =1π
20
Closed Loop Response From VCO to PLL Output
Highpass with high frequency gain of 1
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
Kv
Φvn(t)
Kpd
XOR PD: Kpd =1π
21
Consider A First Order Loop Filter
First order loop filter
C1
R1e(t) v(t)
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
KvKpd
XOR PD: Kpd =1π
22
Closed Loop Poles Versus Open Loop Gain
Higher open loop gain leads to an increase in bandwidth but decrease in phase margin- Closed loop poles start exhibiting higher Q
-90o
-180o
-120o
-150o
20log|A(f)|
f
angle(A(f))
Open loopgain
increased
0 dB
PM = 33o for C
PM = 45o for B
PM = 59o for A
A
A
A
B
B
B
C
C
C
Evaluation ofPhase Margin
Closed Loop PoleLocations of G(f)
Dominantpole pair
fp
Re{s}
Im{s}
0
23
Corresponding Closed Loop Response
Decrease in phase margin leads to- Peaking in closed loop frequency response- Ringing in closed loop step response
5 dB0 dB
-5 dB
f
A
C
fp
B
Frequency Response of G(f)
1.4
0
1
0.6
t
AB
C
Step Response of G(f)
Design of PLL dynamics is similar toopamps and other classical feedback systems
24
The Problem with a First Order Loop Filter
To achieve good phase margin, fp >> unity gain frequency- Implies that H(f) ≈ 1 at unity gain frequency- Bandwidth of G(f) purely set by Kpd, Kv, and N
Recall that bandwidth of G(f) is roughly the same as unity gain frequency of A(f)
-90o
-180o
-120o
-150o
20log|A(f)|
f
angle(A(f))
Open loopgain
increased
0 dB
fp
Unity GainFrequency
Limited freedom to choose desired closed loop bandwidth
25
Inclusion of a Charge Pump
Charge pump current adds a new parameter that allows more freedom in choosing the PLL bandwidth
Lead/lag filter is a common loop filter with charge pump- Current into a capacitor forms integrator- Add extra pole/zero using resistor and additional capacitor
C1
C2
R1
v(t)i(t)
Icp
Icp
Up
Down
e(t) Where:
Forms a Type II PLL
26
Type I versus Type II PLL Implementations
Type I: one integrator in PLL open loop transfer function A(f)- VCO adds one integrator- Loop filter, H(f), has no integrators
Type II: two integrators in PLL open loop transfer function A(f)- Loop filter, H(f), has one integrator
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1
Loop Filter VCO
Divider
KvKpd
XOR PD: Kpd =1π
27
DC output range of gain block versus integrator
Issue: often need to provide attenuation through loop filter to achieve a desired closed loop bandwidth- Loop filter output fails to cover full input range of VCO
VCO Input Range Issue for Type I PLL Implementations
PFDLoopFilter
N[k]
ref(t) out(t)
Divider
e(t) v(t)
VDD
Gnd
Output Rangeof Loop Filter
NoIntegrator
VCO
0Ks
Integrator0
Gain Block
K
28
Options for Achieving Full Range Span of VCO
LoopFilter
D/A
e(t) v(t)C.P.
VDD
Gnd
Output Rangeof Loop FilterCourse
Tune
NoIntegrator
LoopFilter
e(t) v(t)C.P.
VDD
Gnd
Output Rangeof Loop Filter
ContainsIntegrator
Type I Type II
Type I- Add a D/A converter to provide coarse tuning
Adds power and complexity Steady-state phase error inconsistently set
Type II- Integrator automatically provides DC level shifting
Low power and simple implementation Steady-state phase error always set to zero
29
Design of Type II, Charge Pump PLL
Place fz and fp based on phase margin, and open loop gain based on desired PLL bandwidth- Charge pump offers high flexibility in choosing PLL bandwidth
Non-dominantpole
Dominantpole pair
Open loopgain
increased
120o
-180o
-140o
-160o
20log|A(f)|
ffz
0 dB
PM = 55o for CPM = 53o for APM = 54o for B
angle(A(f))
A
A
A
A
B
B
B
B
C
C
C
C
Evaluation ofPhase Margin
Closed Loop PoleLocations of G(f)
fp
Re{s}
Im{s}
0
30
Negative Issues For Type II PLL Implementations
Parasitic pole/zero pair causes- Peaking in the closed loop frequency response
Increases PLL phase noise- Extended settling time due to parasitic “tail” response
Bad for applications demanding fast settling time
ffofz
fzfcp
|G(f)|Peaking caused by
undesired pole/zero pair
0
1
Frequency (Hz)
0 1 2 3 4
0.6
1
1.4
Normalized time: t*foN
orm
aliz
ed A
mpl
itude
Step Responses for a Second OrderG(f) implemented as a Bessel Filter
Type II: fz/fo = 1/3
Type II: fz/fo = 1/8
Type I
The Need for Frequency Detection
32
Response of PLL to Divide Value Changes
Change output frequency by changing the divide value Classical approach provides no direct model of impact of
divide value variations- Treat divide value variation as a perturbation to a linear system
and use the PLL closed loop response More advanced PLL models include divide value variations
- M.H. Perrott, M.D. Trott, C.G. Sodini, "A modeling approach for Σ-∆ fractional-N frequency synthesizers allowing straightforward noise analysis,“ JSSC, vol. 37, pp. 1028-1038, Aug. 2002.
N
Φref(t) Φout(t)
Φdiv(t)
e(t) v(t)H(f)
jf
1π
1
Loop FilterXOR PD
VCO
Divider
NN+1
t
Kv
33
Response of an Actual PLL to Divide Value Change
Example: Change divide value by one
40 60 80 100 120 140 160 180 200 220 24091.8
92
92.2
92.4
92.6
92.8
93
N (
Div
ide
Val
ue)
Synthesizer Response To Divider Step
40 60 80 100 120 140 160 180 200 220 2401.83
1.84
1.85
1.86
1.87
Out
put F
requ
ency
(G
Hz)
Time (microseconds)
PLL responds according to linear model of closed loop response!
34
What Happens with Large Divide Value Variations?
PLL response does not fit linear model
- What is happening here?
40 60 80 100 120 140 160 180 200 220 240
92
93
94
95
96N
(D
ivid
e V
alue
)Synthesizer Response To Divider Step
40 60 80 100 120 140 160 180 200 220 240
1.84
1.86
1.88
1.9
1.92
Out
put F
requ
ency
(G
Hz)
Time (microseconds)
35
Recall Phase Detector Characteristic
To simplify modeling, we assumed that we always operated in a confined phase range (0 to 2)- Led to a simple PD model
Large perturbations knock us out of that confined phase range- PD behavior varies depending on the phase range it
happens to be in
Φref(t) - Φdiv(t)2ππ-π-2π 0
avg{e(t)}
1
-1
phase detector
range = 2π
gain = 1/πgain = -1/π
36
Cycle Slipping
Consider the case where there is a frequency offset between divider output and reference- We know that phase difference will accumulate
Resulting ramp in phase causes PD characteristic to be swept across its different regions (cycle slipping)
ref(t)
div(t)
Φref(t) - Φdiv(t)2ππ-π-2π 0
avg{e(t)}
1
-1
gain = 1/πgain = -1/π
37
Impact of Cycle Slipping
Loop filter averages out phase detector output Severe cycle slipping causes phase detector to
alternate between regions very quickly- Average value of XOR characteristic can be close to
zero- PLL frequency oscillates according to cycle slipping- In severe cases, PLL will not re-lock
PLL has finite frequency lock-in range!
2π-2π 4π n2π (n+1)2π
1
-1
XOR DC characteristic
cycle slipping
Φref - Φdiv
38
Back to PLL Response Shown Previously
PLL output frequency indeed oscillates- Eventually locks when frequency difference is small enough
- How do we extend the frequency lock-in range?
40 60 80 100 120 140 160 180 200 220 240
92
93
94
95
96
N (
Div
ide
Val
ue)
Synthesizer Response To Divider Step
40 60 80 100 120 140 160 180 200 220 240
1.84
1.86
1.88
1.9
1.92
Out
put F
requ
ency
(G
Hz)
Time (microseconds)
39
Phase Frequency Detectors (PFD)
D
Q
Q
D
Q
Q
R
Rref(t)
div(t)
Ref(t)
Div(t)
1
1
up(t)
e(t)
down(t)
Up(t)
Down(t)
10
-1
E(t)
Example: Tristate PFD
40
Tristate PFD Characteristic
Calculate using similar approach as used for XOR phase detector
Note that phase error characteristic is asymmetric about zero phase- Key attribute for enabling frequency detection
2π−2π
1
−1
avg{e(t)}
phase detectorrange = 4π
gain = 1/(2π)
Φref - Φdiv
41
PFD Enables PLL to Always Regain Frequency Lock
Asymmetric phase error characteristic allows positive frequency differences to be distinguished from negative frequency differences - Average value is now positive or negative according to
sign of frequency offset- PLL will always relock for type II PLL
Φref - Φdiv2π 4π 2nπ−2π
1
-1
Tristate DC characteristic
cycle slipping
0
lock
42
The Issue of Noise
Each PLL component contributes noise that impacts overall PLL output phase noise
Achievement of adequately low PLL phase noise is a key issue when designing a PLL
PFD ChargePump
e(t) v(t)
N
LoopFilter
DividerVCO
ref(t)
div(t)
f
Charge PumpNoise
VCO Noise
f
-20 dB/dec
1/Tf
ReferenceJitter
f
ReferenceFeedthrough
T
f
DividerJitter
43
Modeling the Impact of Noise on Output Phase of PLL
Determine impact on output phase by deriving transfer function from each noise source to PLL output phase- There are a lot of transfer functions to keep track of!
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
espur(t)Φjit[k] Φvn(t)Icpn(t)
Icp
VCO Noise
f0
SΦjit(f)
f0
SIcpn(f)
f0
Sespur(f)
Divider/ReferenceJitter
ReferenceFeedthrough
Charge PumpNoise
1/T f0
SΦvn(f)
-20 dB/dec
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
44
Simplified Noise Model
Refer all non-VCO PLL noise sources to the PFD output- PFD-referred noise corresponds to the sum of these noise
sources referred to the PFD output- Typically, charge pump noise dominates PFD-referred noise
VCO-referredNoise
f0
SEn(f)
PFD-referredNoise
1/T f0
SFvn(f)
-20 dB/dec
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)
Icp
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
H(f)
45
Leverage Previous Transfer Function AnalysisVCO-referred
Noise
f0
SEn(f)
PFD-referredNoise
1/T f0
SFvn(f)
-20 dB/dec
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)
Icp
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
H(f)
PFD-referred noise- Lowpass with DC gain of N/Kpd
VCO-referred noise- Highpass with gain of 1
46
Transfer Function View of PLL Phase Noise
PFD-referred noise dominates at low frequencies- Corresponds to close-in phase noise of synthesizer
VCO-referred noise dominates at high frequencies- Corresponds to far-away phase noise of synthesizer
Φvn(t)en(t)
Φout(t)
Φnvco(t)Φnpfd(t)
fo1-G(f)
foG(f)
N
VCO-referredNoise
f0
Sen(f)
PFD-referredNoise
1/T f0
SΦvn(f)
-20 dB/dec
Sen(f)
2
Radia
ns
2/H
z
SΦvn(f)
f0
Radia
ns
2/H
z SΦnpfd(f)
SΦnvco(f)
f0
Kcp
N
Kcp
47
Spectral Density of PLL Phase Noise Components
Φvn(t)en(t)
Φout(t)
Φnvco(t)Φnpfd(t)
fo1-G(f)
foG(f)
N
VCO-referredNoise
f0
Sen(f)
PFD-referredNoise
1/T f0
SΦvn(f)
-20 dB/dec
Sen(f)
2
Radia
ns
2/H
z
SΦvn(f)
f0
Radia
ns
2/H
z SΦnpfd(f)
SΦnvco(f)
f0
Kcp
N
Kcp
PFD-referred noise: VCO-referred noise:
Overall:
48
Take a Closer Look at Charge Pump Noise
Spectral density of charge pump noise is a function of device noise and pulse width- Short pulse widths reduce effective charge pump noise
Tristate PFD has an advantage of allowing short pulsewidths (i.e., lower noise) during steady-state operation
WP
M2M1
Ibias
currentsource
current bias
Icp
idbias
2id
2
Cbig
W
L
49
Impact of Transistor Current Magnitude on Noise
Charge pump noise will be related to the current it creates as
Recall that gdo is the channel resistance at zero Vds- At a fixed current density, we have
- Therefore, charge pump noise is proportional to Icp
M2M1
Ibias
currentsource
current bias
Icp
idbias
2id
2
Cbig
W
L
50
Analysis of Charge Pump Noise Impact
Transfer function from charge pump noise to PLL output is found by referring noise to PFD output by factor 1/Icp
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)Icpn(t)
Icp
VCO Noise
f0
SIcpn(f)
Charge PumpNoise
f0
SΦvn(f)
-20 dB/dec
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
PFD-Referred
Noise
51
Increasing Icp Leads to Reduced Noise at PLL Output
Output phase noise due to charge pump:
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)Icpn(t)
Icp
VCO Noise
f0
SIcpn(f)
Charge PumpNoise
f0
SΦvn(f)
-20 dB/dec
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
PFD-Referred
Noise
52
Issue: Increasing Icp Leads to Larger Loop Filter
Area gets larger since increasing Icp leads toincreased loop filter capacitance (C1+C2)
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)Icpn(t)
Icp
VCO Noise
f0
SIcpn(f)
Charge PumpNoise
f0
SΦvn(f)
-20 dB/dec
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
PFD-Referred
NoiseZl(s)
s(C1+C2)
To keep PLL BW unchanged, assume Icp/(C1+C2) is held constant (to maintain open loop gain)
53
Better Approach: Increase PD Gain to Lower Noise
To keep PLL BW unchanged, assume IcpKpd held constant- Loop filter can remain unchanged as Kpd is increased
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)Icpn(t)
Icp
VCO Noise
f0
SIcpn(f)
Charge PumpNoise
f0
SΦvn(f)
-20 dB/dec
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
PFD-Referred
Noise
54
Can We Increase PD Gain for a Charge Pump PLL?
XOR-based PD provides factor of two higher gain than a tristate PFD- Key issue: carries an overall noise penalty since the charge
pump is never gated off (i.e., generates long pulses)- XOR PD rarely used due to its noise penalty
Φdiv[k]
Φref [k] KV
jf
v(t) Φout(t)Z(f)
1N
e(t)
en(t)Φjit[k] Φvn(t)Icpn(t)
Icp
VCO Noise
f0
SIcpn(f)
Charge PumpNoise
f0
SΦvn(f)
-20 dB/dec
PFDChargePump
Loop FilterImpedance
Divider
VCO
Kpd
PFD-Referred
Noise
55
Key Issue of Tristate PFD: Charge Pump Mismatch
Mismatch of charge pump Up/Down currents leads to nonlinearity in the PLL phase comparison path when tristate PFD used
Reg
D QDiv(t)
D Q
reset
1
1
Ref(t)
Up(t)
Down(t)
PD & Charge Pump Characteristic
Div(t)
Ref(t)
Up(t)
Down(t)
2
2error
avg{Iin(t)}
-2
-IcpGain =
2
Icp
Icp+ε
RC
Network
Icp
Iin
Icp+ε Gain = 2
Icp+ε
Nonlinearity
56
Nonlinearity Causes Noise Folding with Frac-N PLLs
Significant analog design effort is often required to avoid this issue
Reg
D QDiv(t)
D Q
reset
1
1
Ref(t)
Up(t)
C1Down(t)
R1
C2
Vtune(t)
Divider
Out(t)
Tristate PFD
VCO
2π
-2π
avg{IIN}
I-ε1
-I
Nonlinearityat origin
Φref(t) - Φdiv(t)
IIN
f
Σ−Δ Quantization Noise
N[k] M.F
57
Summary of Charge Pump PLL Issues
Tristate PFD has issues with- Low PD gain – leads to increased loop filter for given PLL noise- Charge pump nonlinearity – causes quantization noise folding
Charge Pump has issues with- Nontrivial analog design effort for wide range, high output
impedance, low leakage, reasonable matching, low noise
Reg
D Qdiv(t)
D Q
reset
1
1
ref(t)
up(t)
C1down(t)
R1
C2
vtune(t)
Divider
Are there alternative analog PLL architectures?
58
How Do We Achieve Higher PD Gain?
Use tristate PD as our starting point- Range of detector spans 2 Reference periods (i.e., 4 radians)- PD gain is 2/(PD range) = 2/(4) = 1/(2)
Reg
D QDiv(t)
D Q
reset
1
1
Ref(t)
Up(t)
Down(t)
Phase Detector Characteristic
Div(t)
Ref(t)
Up(t)
Down(t)
2
2error
avg{Up(t)-Down(t)}
-2
1
-1
PD Gain = 2
1
Ipump
RC
Network
Ipump
59
Sampled PD Achieves Much Higher PD Gain
Directly sample VCO signal at reference edges- PD gain becomes 2/(/N) = 2N/assuming
N = VCO Frequency)/(Ref Frequency) PD output voltage range assumed to be -1 to 1
Gao, Klumperink, Bohsali, Nauta, JSSC, Dec 2009
Yields much lower in-band PLL noise, but constrainedto integer-N PLL structures
C1
Vtune(t) Out(t)
Sampling PD
VCO
RemainingLoop Filter
Ref(t)
PD Range = π/N
1
-1
C2
60
Div(t)
Ref(t)
Up(t)
Down(t)
High
Gain
PD
1
-1
R1
C1 Vc1(t)
2
Div_4x(t)
Ref(t)
Up(t)
Down(t)
2 /8error
avg{Vc1(t)}
-2 /8
1
-1
PD Gain = 2
8
Achieving Higher PD Gain for a Fractional-N PLL
Develop a PD with reduced phase error range in which Up/Down pulses vary in width in opposite directions- Need an appropriate loop filter topology that properly leverages
the reduced PD range for higher PD gain
61
Div(t)
Ref(t)
Up(t)
Down(t)
High
Gain
PD
1
-1
R1
C1 Vc1(t)
2
Div_4x(t)
Ref(t)
Up(t)
Down(t)
2 /8error
avg{Vc1(t)}
-2 /8
1
-1
PD Gain = 2
8
Key Implementation Detail: Use Switched Resistor
Switching to voltage Supply/Gnd causes Vc1(t) to reflect the average of the Up/Down pulses within the reduced PD range- PD gain is increased since full voltage range at Vc1 achieved
across a reduced phase error range
See also: Hedayati, Bakkaloglu
RFIC 2009
62
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
QRef(t)
Div_4x(t)
Up(t)
Down(t)
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Tdiv
Tref
Tdiv
Tref2
avg{Up(t) - Down(t)}
Phase Detector Characteristic
PD Gain = Tdiv
Tref
2
12
error
Delay Buffer For Non-Overlapping Up/Down Pulses
1
-1
= 2
8
Implementation of High Gain Phase Detector
Use 4X higher divider frequency- Simple digital implementation
63
Multi-Phase Pulse Generation (We’ll Use it Later…)
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
QRef(t)
Div_4x(t)
Up(t)
Down(t)
Mid(t)
Last(t)
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Mid(t)
Last(t)
Tdiv
Tref
Short PulseGenerator
Tdiv
Tref2
avg{Up(t) - Down(t)}
Phase Detector Characteristic
error
1
-1
PD Gain = Tdiv
Tref
2
12 =
2
8
64
Div(t)
Ref(t)
Up(t)
Down(t)
Phase Detector Characteristic
2error
avg{Up(t)-Down(t)}
-2
1
-1
PD Gain = 2
2
Ipump
RC
Network
Ipump
High
Gain
PD
2
Div_4x(t)
Ref(t)
Up(t)
Down(t)
What If We Use A Charge Pump with the High Gain PD?
PD Gain increased by 2 compared to tristate PFD- Reduced phase error range and max/min current occurs
High linearity despite charge pump current mismatch- Similar to XOR PD, but noise is reduced
65
Increasing Feedforward Gain While Utilizing Charge Pump
Can we remove the charge pump to reducethe analog design effort?
We can use the high gain PD in a dual-path loop filter topology- But we want a simple design!
See also: Craninckx, JSSC, Dec
1998
High
Gain
PD
Ref(t)
Div_4x(t)
w
H(w)C2
Vtune(t)
(High Kv)
Vdd
Gnd
Up(t)
R1
C1
Down(t)
Ipump
Ipump
Vtune(t)
(Low Kv) ref(t)
div(t)
2
8
PDGain
2
2
PDGain
2
Vdd
SupplyGain
ChargePump
Ipump
1+sR1_effC1
1
sC2
1
RCNetwork
IntegrationCap
wz
66
Passive RC Network Offers a Simpler Implementation
Capacitive feedforward path provides stabilizing zero
Design effort is simply choosing switch sizes and RC values
Regulated Vdd
Gnd
High
Gain
Phase
Detector
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R1
C1 C2 C3Cf
Ref(t)
Div_4x(t)
Up(t)
Down(t)
w
Cf+C3
Cf
DC Gain = 1
H(w)
R2
R3
Vc1(t)
Vtune(t)
wz
67
The Issue of Reference Spurs
Ripple from Up/Down pulses passes through to VCO tuning input
Is there an easy way toreduce reference spurs?
Regulated Vdd
Gnd
High
Gain
Phase
Detector
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R1
C1 C2 C3Cf
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R2
R3
Vc1(t)
Vc1(t)
Vtune(t)
Vtune(t)
68
Leverage Multi-Phase Pulsing
Ripple from Up/Down pulses blocked before reaching VCO- Reference spurs reduced!- Similar to sample-and-hold
technique (such as Zhang et. al., JSSC, 2003)
There is a nice side benefitto pulsing resistors…
Regulated Vdd
Gnd
High
Gain
Phase
Detector
Ref(t)
Div_4x(t)
Up(t)
Down(t)
R1
C1 C2 C3Cf
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Vc1(t)
Vc1(t)
Mid(t)
Last(t)
R2/2 R2/2
R3/2 R3/2
Cf
Mid(t)Last(t)
Vtune(t)
Vtune(t)
69
Pulsing Resistor Multiplies Resistance!
Resistor only passes current when pulsed on- Average current through resistance is reduced according
to ratio of On time, Ton, versus pulsing Period, Tperiod- Effective resistance is actual resistance multiplied by ratio Tperiod/Ton
Resistor multiplication allows a large RC time constantto be implemented with smaller area
Pulse_On(t)
Ton
Tperiod
R/2R/2 Ton
TperiodRR_eff =
J. A. Kaehler, JSSC, Aug. 1969and
P. Kurahashi, P. K. Hanumolu, G. C. Temes, and U.-K. Moon,
JSSC, Aug. 2007
70
Parasitic Capacitance Reduces Effective Resistance
Spice simulation and measured results reveal that>10X resistor multiplication can easily be achieved
Parasitic capacitance stores charge during the pulse “On” time- Leads to non-zero current through resistor during pulse
Off time- Effective resistance reduced
Ton
Tperiod
Pulse_On(t)
CpCp Cp CpCpCp
R/4R/4 R/4 R/4 Ton
TperiodR<R_eff
71
Multi-Modulus Divider Allows Short Pulse Generation
Creates well controlled pulse widths corresponding to multiples of the period of its high speed input- Standard circuit used in many fractional-N PLL structures- Pulse width can be changed by tapping off different stages
Divide-By-2/3 Stage
clk
modout
con
out
modin
clk
modout
con
out
modin
clk
modout
con
out
modin
Vdd
Divide-By-2/3 Stage Divide-By-2/3 Stage
out(t)
in(t)
pulse_width_2x
con0 con1 con2
out(t)
out(t)
in(t)
DQDQ
D Q D Q
Latch Latch
Latch Latch
clk
modin
modoutcon
out
pulse_width_2x = 0
pulse_width_2x = 1
ck ck
ck ck
72
D Q
Q
D Q
Q
D Q
Q
D Q
Q
D Q
QRef(t)
Div_4x(t)
Up(t)
Down(t)
Mid(t)
Last(t)
Ref(t)
Div_4x(t)
Up(t)
Down(t)
Mid(t)
Last(t)
Tdiv
Tref
Short PulseGenerator
Utilize Short Pulses from Divider in the High Gain PD
Short pulses from divider output are used to clock the PD registers
PD state is used to gate divider output every 4 cycles to form Last pulse- Lower pulse frequencies
can also be implemented
73
Regulated Vdd
Gnd
Up(t)
Down(t)
R1
C1 C2Cf
Vc1(t)
R2/2 R2/2
R3/2 R3/2
Cf
Mid(t)
Last(t)
Vtune(t)
w
Cf+C3
Cf
1
H(w)
wz
R3_eff Cf
1wz =
Ton
Tperiod
C3
Switched Resistor Achieves PLL Zero with Low Area
For robust stability, PLL zero should be set << PLL BW- Example: PLL BW = 30kHz- Assume desired wz = 4 kHz- Set Cf = 2.5pF (for low area)- Required R3_eff = 16 MegaOhms
Large area
Example: Proper choice of Ton and Tperiod allows R3_eff = 16 MegaOhms to be achieved with R3 = 500 kOhms!
74
Overall Design of Loop Filter
Apply standard transfer function analysis to achieve desired PLL bandwidth and phase margin
1
fz fp2 fp3fp1
H(f)
f
Cf
Cf + C3
Overall PLL Unity GainCrossover Region
R1_eff R2_eff
R3_eff
C1 C2 C3Cf
1 + s/wz
(1 + s/wp1)
Φref(t)
Φdiv(t)
(1 + s/wp2)(1 + s/wp3)
H(s)
2π Kv
s
VCO
1
Nnom
α
2π
Vdd
2
PDGain
SupplyGain
Φout(t)Vtune(t)Vlf(t)
Vtune(t)Vlf(t)
Examples: (assume C1 = C2)
β2=2.62β1=0.38,
fz2πR3_effCf
1fp2
2πβ1R1_effC1
1
fp32πβ2R1_effC1
1fp1
2πR3_eff(Cf +C3)
1
R2_eff = 2R1_eff β2=1.7β1=0.29,
R2_eff = R1_eff
75
Noise Analysis (Ignore Parasitic Capacitance of Resistors)
Assumption: switched resistor time constants are much longer than “on time” of switches- Single-sided voltage noise contributed by each resistor
is simply modeled as 4kTReff (same as for a resistor of the equivalent value)
Note: if switched resistor time constants are shorter than “on time” of switches- Resistors contribute kT/C noise instead of 4kTReff- We would not want to operate switched resistor filter in
this domain since time constants would not be boosted
Φref(t) R1_eff R2_eff
R3_eff
C1 C2 C3Cf
Vtune
Φdiv(t)
8
2π
Voltage
Signal
4kTR1_eff 4kTR2_eff 4kTR3_eff
Vdd
2
PDGain
SupplyGain
76
Issue: Nonlinearity in Switched Resistor Loop Filter
Nonlinearity is caused by- Exponential response of
RC filter to pulse width modulation
- Variation of Thold due to Sigma-Delta dithering of divide value
Note: to avoid additional nonlinearity, design divide value control logic to keep Ton a constant value
Ref(t)
Div_4x(t)
Up
Down
Vc1
Vc1
Vdd
Gnd
Phase
Detector
&
Pulse Gen
Ref(t)
Div_4x(t)
Up
Down
R1 R2/2
C1
Vc1[k]Vc1[k-1] Vc1[k+1]
Ton
Tperiod
Thold
77
Ref(t)
Div_4x(t)
Up
Down
Vc1
Vc1
Vdd
Gnd
Phase
Detector
&
Pulse Gen
Ref(t)
Div_4x(t)
Up
Down
R1 R2/2
C1
Vc1[k]Vc1[k-1]
Thold Ton
Ton/2+ΔT Ton/2-ΔT
Nonlinearity Due to Pulse Width Modulation
Pulse width modulation nonlinearity is reduced as ratio T/(R1C1) is reduced- If T/(R1C1) is small:
- This implies nonlinearity is reduced with lower PLL bandwidth
78
Key Design Issue: Folded Noise versus Other Noise
Folded quantization noise due to nonlinearity is reasonably below other noise sources for this example- However, could be an issue for wide bandwidth PLLs
Use (CppSim) behavioral simulation to evaluate this issue
Other PLLNoise Sources
Phase noise referred toVCO carrier frequency
Folded Sigma-DeltaQuant Noise
79
The Issue of Initial Frequency Acquisition
During initial frequency acquisition, Vtune(t) must be charged to proper bias point- Following through on previous example:
Large 16 MegaOhm resistance of R3_eff prevents fast settling of the voltage across C3
Regulated Vdd
Gnd
Up(t)
Down(t)
R1
C1 C2Cf
Vc1(t)
R2/2 R2/2
Cf
Vtune(t)
C3 = 35pF
R3_eff = 16MegaOhms
80
Capacitive Divider Sets Instantaneous Voltage Range
Φref-Φdiv
avg{Vc1(t)}
Vdd
Gnd
gain =
Phase Detector and Supply Gain Characteristic
2π
Vdd
Gnd
Phase
Detector
&
Pulse Gen
Ref(t)
Div_4x(t)
Up
Down
R1 R2/2 R2/2
R3/2 R3/2
C1 C2 C3Cf
Pulse_MidPulse_Last
Out
InstantaneousOut range
Vdd
Gnd
AC Gain
C3+Cf
Cf= Vdd
C3+Cf
Cf=
Vc1
Vdd
2
α
How do we quickly charge capacitor C3 to its correctDC operating point during initial frequency acquisition?
81
Utilize Switched Capacitor Charging Technique
Charge C3 high or low only when frequency error is detected- No steady-state noise penalty, minimal power consumption
Regulated Vdd
Gnd
Up(t)
Down(t)
R1
C1 C2Cf
Vc1(t)
R2/2 R2/2
Cf
Vtune(t)
C3
R3/2 R3/2
Cc
Vdd
Gnd
Counter Count > 4
Count < 4Ref(t)
Tdiv_4x
Tref
Count
Charge High
Ref(t)
Charge Low(t)
Charge High(t)
Div_4x(t)
Charge Low
Connect
Connect(t)
82
CppSim Behavioral Simulation of Frequency Locking
Switched capacitor technique allows relativelyfast frequency locking
0 10 20 30 40 50 60 70 80 90
Time (microseconds)
0
1
0
1
0
1
0.5
charge_high
charge_low
vtune
100
83
PLL Application: A MEMS-based Programmable Oscillator
A part for each frequency and non-plastic packaging- Non-typical frequencies
require long lead times
Same part for all frequencies and plastic packaging- Pick any frequency you want
without extra lead time
Quartz Oscillators MEMS-based Oscillator
We can achieve high volumes at low cost using IC fabrication
source: www.ecliptek.com
84
Architecture of MEMS-Based Programmable Oscillator
MEMS device provides high Q resonance at 5 MHz- CMOS circuits provide DC bias and sustaining amplifier
Fractional-N synthesizer multiplies 5 MHz MEMS reference to a programmable range of 750 to 900 MHz
Programmable frequency divider enables 1 to 115 MHz output
Fractional-N
Synthesizer
Oscillator Sustaining
Circuit and
Charge Pump Continuously
Programmable
MEMS
Resonator
5 MHz
DigitalFrequency Setting
750-900 MHz
Programmable
Frequency
Divider
1 to 115 MHz
85
Compensation of Temperature Variation
High resolution control of fractional-N synthesizer allows simple method of compensating for MEMS frequency variation with temperature- Simply add temperature sensor and digital compensation logic
Fractional-N
Synthesizer
Oscillator Sustaining
Circuit and
Charge Pump
Temp
Freq Error (ppm)
Digital
Logic
Temperature
Sensor
Temp
Freq Compensation (ppm)
Temp
Freq Error (ppm)
MEMS
Resonator
5 MHz
DigitalFrequency Setting
750-900 MHz
Programmable
Frequency
Divider Continuously
Programmable
1 to 115 MHz
86
Why Use An Alternative Fractional-N PLL Structure?
Want to achieve low area, low power, and low design complexity
Fractional-N
Synthesizer
Oscillator Sustaining
Circuit and
Charge Pump
Temp
Freq Error (ppm)
Digital
Logic
Temperature
Sensor
Temp
Freq Compensation (ppm)
Temp
Freq Error (ppm)
MEMS
Resonator
5 MHz
DigitalFrequency Setting
750-900 MHz
Programmable
Frequency
Divider Continuously
Programmable
1 to 115 MHz
Switched resistor PLL provides a nice solutionfor this application space
87
CMOS and MEMS Die Photos Show Low Area of PLL
Active area:- VCO & buffer &
bias: 0.25mm2
- PLL (PFD, Loop Filter, divider): 0.09 mm2
- Output divider: 0.02 mm2
External supply- 1.8/3.3V
Current (20 MHz output, no load)- ALL: 3.2/3.7mA- VCO: 1.3mA- PLL & Output
Divider: 0.7mA
88
Measured Phase Noise (100 MHz output)
Suitable for most serial applications, embedded systems and FPGAs, audio, USB 1.1 and 2.0, cameras, TVs, etc.
Integrated Phase Noise:17 ps (rms) from 1 kHz to 40 MHz
Ref. Spur: -65 dBc
-90 dBc/Hz
100 Hz 40 MHz30 kHz
-140 dBc/Hz
89
Calculated Phase Noise Profile of Overall PLL
Note that loop filter noise is well below other PLL noise sources
100 1k 10k 100k 1M 10M-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60P
hase N
ois
e (
dB
c/H
z)
Frequency Offset from Carrier (Hz)
Calculated Phase Noise (100 MHz carrier)
Integrated Phase Noise = 16.6 ps (rms) (1kHz to 40 MHz)
40M
MEMSVCO
S-D
OutputBuffer
LoopFilter
90
Simulated Impact of Switched Resistor Nonlinearity
Noise folding below other PLL noise sources- More significant for third order Sigma-Delta
-150
-140
-130
-120
-110
-100
-90
Simulated Phase Noise Impact of S-D Noise Folding (100 MHz carrier)
1k 10k 100k 1M
Frequency Offset from Carrier (Hz)
3M
2nd order S-D
3rd order S-D
Overall Phase Noise
Ph
as
e N
ois
e (
dB
c/H
z)
ideal
simulated
ideal
simulated
91
-50 0 50 100-50
-40
-30
-20
-10
0
10
20
30
40
50
Temperature (degC)
Fre
qu
en
cy V
ari
ati
on
(P
PM
)
Frequency Variation After Single-Temperature Calibration
< +/-30 ppm across industrial temperature rangewith single-temperature calibration
6600 Parts
92
Conclusion
We took a closer look at the classical charge pump PLL- Very versatile structure- Requires a fair amount of analog design effort
Alternative PLL structures can provide low area, low power, and reduced analog design effort- High gain phase detector lowers impact of loop filter noise- Switched resistor technique eliminates the charge pump
and reduces area through resistor multiplication- Switched capacitor frequency detection enables reasonable
frequency acquisition time with no noise penalty
Application specific PLL structures can provideworthwhile benefits over a classical analog PLL structure
