Clock Networks and PLLs - Altera · Clock Networks and PLLs in Arria 10 Devices 4 2013.12.02 A10-CLKPLL Subscribe Send Feedback Thischapterdescribestheadvancedfeaturesofhierarchicalclocknetworksandphase

4Clock Networks and PLLs in Arria 10 Devices

2013.12.02

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This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs)in Arria® 10 devices. The Quartus® II software enables the PLLs and their features without external devices.

Related InformationArria 10 Device Handbook: Known IssuesLists the planned updates to the Arria 10 Device Handbook chapters.

Clock NetworksThe Arria 10 devices contain the following clock networks that are organized into a hierarchical structure:

• Global clock (GCLK) networks• Regional clock (RCLK) networks• Periphery clock (PCLK) networks

• Small periphery clock (SPCLK) networks• Large periphery clock (LPCLK) networks

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Clock Resources in Arria 10 Devices

Table 4-1: Clock Resources in Arria 10 Devices—Preliminary

Source of Clock ResourceNumber of

Resources AvailableDeviceClock Resource

For HSSI:REFCLK_GXB[L,R][1,4][C..J]_[0,1][p,n]pins

For I/O:CLK_[2,3][A..L]_[0,1][p,n]pins

• HSSI: 8 single-ended

• I/O: 32 single-ended or 16differential

• 10AS016• 10AS022• 10AX016• 10AX022

Clock input pins



• 10AS027• 10AS032• 10AX027• 10AX032



• 10AS048• 10AX048



• 10AS057• 10AS066• 10AX057• 10AX066



• 10AT090• 10AT115• 10AX090• 10AX115

Clock Networks and PLLs in Arria 10 DevicesAltera Corporation

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• Physical medium attachment (PMA)and physical coding sublayer (PCS) TXand RX clocks per channel

• PMAand PCSTX andRXdivide clocksper channel

• Hard IP core clock output signals• DLL clock outputs• Fractional PLL and I/O PLL C counter

outputs• Fractional PLL and I/O PLL M counter

outputs for feedback• REFCLK and clock input pins• Core signals• Phase aligner counter outputs

32AllGCLK networks

8

• 10AS016• 10AS022• 10AS027• 10AS032• 10AX016• 10AX022• 10AX027• 10AX032

RCLK networks 12• 10AS048• 10AX048

16

• 10AS057• 10AS066• 10AX057• 10AX066• 10AT090• 10AT115• 10AX090• 10AX115

Altera CorporationClock Networks and PLLs in Arria 10 Devices

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4-3Clock Resources in Arria 10 DevicesA10-CLKPLL2013.12.02




For HSSI:

• Physical medium attachment (PMA)and physical coding sublayer (PCS) TXand RX clocks per channel

• PMAand PCSTX andRXdivide clocksper channel

• Hard IP core clock output signals• DLL clock outputs• Fractional PLL C and M counter outputs• REFCLK and clock input pins• Core signals

For I/O:

• DPA outputs (LVDS I/O only)• I/O PLL C and M counter outputs• Clock input pins• Core signals• Phase aligner counter outputs

144

• 10AS016• 10AS022• 10AX016• 10AX022• 10AS027• 10AS032• 10AX027• 10AX032

SPCLK networks 216• 10AS048• 10AX048

288

• 10AS057• 10AS066• 10AX057• 10AX066

384

• 10AT090• 10AT115• 10AX090• 10AX115

24

• 10AS016• 10AS022• 10AX016• 10AX022• 10AS027• 10AS032• 10AX027• 10AX032

LPCLK networks 36• 10AS048• 10AX048

48

• 10AS057• 10AS066• 10AX057• 10AX066

64

• 10AT090• 10AT115• 10AX090• 10AX115

For more information about the clock input pins connections, refer to the pin connection guidelines.

Related InformationArria 10 Device Family Pin Connection Guidelines


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Hierarchical Clock NetworksArria 10 devices cover 3 levels of clock networks hierarchy. The sequence of the hierarchy is as follows:

1. GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks2. Section clock (SCLK)3. Row clocks

EachHSSI and I/O column contains clock drivers to drive down shared buses to the respectiveGCLK, RCLK,and PCLK clock networks.

Arria 10 clock networks (GCLK, RCLK, and PCLK) are routed through SCLK before each clock is connectedto the clock routing for each HSSI or I/O bank. The settings for SCLK are transparent. The Quartus IIsoftware automatically routes the SCLK based on the GCLK, RCLK, and PCLK networks.

Each SCLK spine has a consistent height, matching that of HSSI and I/O banks. The number of SCLK spinein a device depends on the number of HSSI and I/O banks.

Figure 4-1: SCLK Spine Regions for Arria 10 Devices

HSSIColumn

I/OColumn

HSSIColumn

I/OColumn

SCLK spine region

Bank

Arria 10 devices provide 33 SCLK networks in each SCLK spine region. The SCLK networks can drive sixrow clocks in each HSSI or I/O bank. The row clocks are the clock resources to the core functional blocks,PLLs, and I/O interfaces, and HSSI interfaces of the device. The connectivity pattern of the multiplexers thatdrive each SCLK limits the clock sources to the SCLK spine region. Each SCLK can select the clock resourcesfrom GCLK, RCLK, LPCLK, or SPCLK lines. Six unique signals can route to each row clock in that SCLKspine region.

The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or GCLK and RCLK feedback clocknetworks in each SCLK spine region. The GCLK, RCLK, PCLK, and GCLK and RCLK feedback clocks sharethe same routing to the SCLKs. To ensure successful design fitting in the Quartus II software, the totalnumber of clock resources must not exceed the SCLK limits in each SCLK spine region.


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Figure 4-2: Hierarchical Clock Networks in SCLK Spine

GCLK/GCLK feedback

RCLK/RCLK feedback

Clock output from the PLLthat drives into the SCLKs.

SCLK

SPCLK

633

32

12

24

LPCLK8

The maximum number ofresources available for theclock networks that can drivethe SCLKs in each spineregion in the largest device.

Row clock

First level Second level Third level

Types of Clock Networks

Global Clock Networks

GCLK networks serve as low-skew clock sources for functional blocks, such as adaptive logic modules(ALMs), digital signal processing (DSP), embedded memory, and PLLs. Arria 10 I/O elements (IOEs) andinternal logic can also drive GCLKs to create internally-generated global clocks and other high fan-outcontrol signals, such as synchronous or asynchronous clear and clock enable signals.

Arria 10 devices provideGCLKs that can drive throughout the device. GCLKs cover every SCLK spine regionin the device.

Figure 4-3: Symbolic GCLK Networks in Arria 10 Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

GCLK[27:24]GCLK[23:16]GCLK[31:28]

GCLK[11:8]GCLK[7:0]

GCLK[15:12]

HSSIColumn

HSSIColumn

I/OColumn

I/OColumn

Bank

Regional Clock Networks

RCLKnetworks provide low clock insertion delay and skew for logic containedwithin a single RCLK region.TheArria 10 IOEs and internal logic within a given region can also drive RCLKs to create internally generatedregional clocks and other high fan-out signals.

Arria 10 devices provide RCLKs that can drive through the chip horizontally. RCLKs cover all the SCLKspine regions in the same row of the device. The top and bottom HSSI and I/O banks have RCLKs that cover


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2 rows vertically. The other intermittent HSSI and I/O banks have RCLKs that cover 6 rows vertically. Thefollowing figure shows the RCLK network coverage.

Figure 4-4: RCLK Networks in Arria 10 Devices


RCLK[3..0]

RCLK[7..4]

RCLK[11..8]

RCLK[15..12]

HSSIColumn

HSSIColumn

I/OColumn

I/OColumn

Bank

Network coverage for RCLK[3..0]




Periphery Clock Networks

PCLK networks provide the lowest insertion delay and the same skew as RCLK networks.

Small Periphery Clock Networks

Each HSSI or I/O bank has 12 SPCLKs. SPCLKs cover one SCLK spine region in HSSI bank and one SCLKspine region in I/O bank adjacent to each other in the same row.


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4-7Periphery Clock NetworksA10-CLKPLL2013.12.02


Figure 4-5: SPCLK Networks for Arria 10 Devices


HSSIColumn

I/OColumn

HSSIColumn

I/OColumn

Bank

12

12

Large Periphery Clock Networks

Each HSSI or I/O bank has 2 LPCLKs. LPCLKs have larger network coverage compared to SPCLKs. LPCLKscover one SCLK spine region in HSSI bank and one SCLK spine region in I/O bank adjacent to each otherin the same row. Top and bottom HSSI and I/O banks have LPCLKs that cover 2 rows vertically. The otherintermediate HSSI and I/O banks have LPCLKs that cover 4 rows vertically.


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A10-CLKPLLPeriphery Clock Networks4-8 2013.12.02


Figure 4-6: LPCLK Networks for Arria 10 Devices


HSSIColumn

I/OColumn

HSSIColumn

I/OColumn

2

4

2

42

2

2

2

Bank

Clock Network SourcesThis section describes the clock network sources that can drive the GCLK, RCLK, and PCLK networks.

Dedicated Clock Input Pins

You can use the dedicated clock input pins CLK_[2,3][A..L]_[0,1][p,n] for high fan-out controlsignals, such as asynchronous clears, presets, and clock enables, for protocol signals through the GCLK orRCLK networks.

The CLK pins can be either differential clocks or single-ended clocks. When you use the CLK pins as single-ended clock inputs, only the CLK_[2,3][A..L]_[0,1]p pins have dedicated connections to the PLL.The CLK_[2,3][A..L]_[0,1]n pins drive the PLLs over global or regional clock networks and do nothave dedicated routing paths to the PLLs.

Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will notbe able to fully compensate for the global or regional clock. Altera recommends using theCLK_[2,3][A..L]_[0,1]p pins for optimal performance when you use single-ended clock inputs todrive the PLLs.

Internal Logic

You can drive each GCLK, RCLK, and PCLK network using core routing to enable internal logic to drive ahigh fan-out, low-skew signal.

Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Arria 10 PLLs. The input clock tothe PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.

Note:


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DPA Outputs

Each DPA can drive the PCLK networks.

HSSI Outputs

HSSI outputs can drive the GCLK, RCLK, and PCLK networks.

PLL Clock Outputs

The Arria 10 PLL clock outputs can drive all clock networks.

Clock Control BlockEvery GCLK, RCLK, and PCLK network has its own clock control block. The control block provides thefollowing features:

• Clock source selection (dynamic selection available only for GCLKs)• Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)

Related InformationClock Control Block (ALTCLKCTRL) Megafunction User GuideProvides more information about ALTCLKCTRL megafunction and clock multiplexing schemes.

Pin Mapping in Arria 10 Devices

Table 4-4: Mapping Between the Clock Input Pins, PLL Counter Outputs, and Clock Control Block Inputs

Fed byClock

Any of the two dedicated clock pins on the same I/O bank of the Arria 10device.inclk[0] and inclk[1]

PLL counters C0 and C2 from adjacent PLLs of the Arria 10 devices.inclk[2]

PLL counters C1 and C3 from adjacent PLLs of the Arria 10 devices.inclk[3]

GCLK Control Block

You can select the clock source for the GCLK select block either statically or dynamically using internal logicto drive the multiplexer-select inputs.

When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or acombination of clock pins or PLL outputs.


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Figure 4-7: GCLK Control Block for Arria 10 Devices

CLKpPins

PLL CounterOutputs

CLKSELECT[1..0]

2

2

2

GCLK

Enable/Disable

This multiplexersupports user-controllabledynamic switching

InternalLogic

InternalLogic

Static ClockSelect

CLKnPin

When the device is in user mode,you can dynamically control theclock select signals throughinternal logic. When the device is in user mode, you can

only set the clock select signals through aconfiguration file (SRAM object file [.sof] orprogrammer object file [.pof]) because thesignals cannot be controlled dynamically.

The CLKn pin is not a dedicatedclock input when used as asingle-ended PLL clock input. TheCLKn pin can drive the PLL usingthe GCLK.

HSSIOutput

DPAOutput

You can set the input clock sources and the clkena signals for the GCLK network multiplexers throughthe Quartus II software using the ALTCLKCTRL megafunction.

When selecting the clock source dynamically using the ALTCLKCTRL megafunction, choose the inputsusing the CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1] ports ofthe multiplexer, and the PLL outputs feed the inclk[2..3] ports.

You can only switch dedicated clock inputs from the same core row.Note:

RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bitsettings in the configuration file (.sof or .pof) generated by the Quartus II software.

Figure 4-8: RCLK Control Block for Arria 10 Devices

CLKpPin

PLL CounterOutputs

Internal Logic

CLKnPin

Enable/Disable

RCLK

InternalLogic

Static Clock Select

2

When the device is in user mode,you can only set the clock selectsignals through a configuration file(.sof or .pof); they cannot becontrolled dynamically.

The CLKn pin is not a dedicatedclock input when used as asingle-ended PLL clock input. TheCLKn pin can drive the PLL usingthe RCLK.

HSSI Output DPA Output

You can set the input clock sources and the clkena signals for the RCLK networks through the Quartus IIsoftware using the ALTCLKCTRL megafunction.

PCLK Control Block

PCLK control block drives both SPCLK and LPCLK networks.


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4-11RCLK Control BlockA10-CLKPLL2013.12.02


To drive the HSSI PCLK, select the HSSI output, PLL output, clock input pin, or internal logic.

To drive the I/O PCLK, select the DPA clock output, PLL output, clock input pin, or internal logic.

Figure 4-9: PCLK Control Block for HSSI Column for Arria 10 Devices

Static Clock Select

PCLK fromHSSI Column

HSSI Output Internal Logic

PLL Output

Figure 4-10: PCLK Control Block for I/O Column for Arria 10 Devices

Static Clock Select

PCLK fromI/O Column

DPA Output Internal Logic

PLLOutput

CLKpPin

You can set the input clock sources and the clkena signals for the PCLK networks through the Quartus IIsoftware using the ALTCLKCTRL megafunction.

Clock Power DownYou can power down the GCLK and RCLK clock networks using both static and dynamic approaches.

When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing theoverall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automaticallypowered down through configuration bit settings in the configuration file (.sof or .pof) generated by theQuartus II software.

The dynamic clock enable or disable feature allows the internal logic to control power-up or power-downsynchronously on the GCLK and RCLK networks. This feature is independent of the PLL and is applieddirectly on the clock network.

You cannot dynamically enable or disable GCLK or RCLK networks that drive PLLs.Note:

Clock Enable SignalsYou cannot use the clock enable and disable circuit of the clock control block if the GCLK or RCLK outputdrives the input of a PLL.


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Figure 4-11: clkena Implementation with Clock Enable and Disable Circuit

This figure shows the implementation of the clock enable and disable circuit of the clock control block.

clkena

Clock SelectMultiplexer Output

GCLK/RCLK/PLL_[2,3][A..L]_CLKOUT[0..3][p,n]

D DQ Q

R1 R2

The R1 and R2 bypass pathsare not available for the PLLexternal clock outputs.

The select line is staticallycontrolled by a bit setting inthe .sof or .pof.

The clkena signals are supported at the clock network level instead of at the PLL output counter level.This allows you to gate off the clock evenwhen you are not using a PLL. You can also use the clkena signalsto control the dedicated external clocks from the PLLs.

Figure 4-12: Example of clkena Signals

This figure shows a waveform example for a clock output enable. The clkena signal is synchronous to thefalling edge of the clock output.

clkena

AND Gate Outputwith R2 Bypassed

(ena Port Registered asFalling Edge of Input Clock)

Clock SelectMultiplexer Output

AND Gate Outputwith R2 Not Bypassed

(ena Port Registered as DoubleRegister with Input Clock)

Use the clkena signals to enable or disablethe GCLK and RCLK networks or the

PLL_[2,3][A..L]_CLKOUT[0..3][p,n] pins.

Arria 10 devices have an additional metastability register that aids in asynchronous enable and disable ofthe GCLK and RCLK networks. You can optionally bypass this register in the Quartus II software.

The PLL can remain locked, independent of the clkena signals, because the loop-related counters are notaffected. This feature is useful for applications that require a low-power or sleep mode. The clkena signalcan also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.


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Arria 10 PLLsPLLs provide robust clock management and synthesis for device clock management, external system clockmanagement, and high-speed I/O interfaces.

The Arria 10 device family contains the following PLLs:

• Fractional PLLs—can function as fractional PLLs or integer PLLs• I/O PLLs—can only function as integer PLLs

The fractional PLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank consistsof two fractional PLLs. You can configure each fractional PLL independently in conventional integer mode.In fractional mode, the fractional PLL can operate with third-order delta-sigma modulation. Each fractionalPLL has four C counter outputs and one L counter output.

The I/OPLLs are located adjacent to the hardmemory controllers and LVDS serializer/deserializer (SERDES)blocks in the I/O banks. Each I/O bank consists of one I/O PLL. The I/O PLLs can operate in conventionalinteger mode. Each I/O PLL has nine C counter outputs.

Arria 10 devices have up to 32 fractional PLLs and 16 I/O PLLs in the largest densities. Arria 10 PLLs havedifferent core analog structure and features support.

Table 4-5: PLL Features in Arria 10 Devices —Preliminary

I/O PLLFractional PLLFeature

YesYesInteger PLL

—YesFractional PLL

94C output counters

2 to 5121 to 320M counter divide factors

1 to 5121 to 32N counter divide factors

1 to 5121 to 320C counter divide factors

—1, 2, 4, 8L counter divide factors

Yes—Dedicated external clock outputs

YesYesDedicated clock input pins

Yes—External feedback input pin

YesYesSpread-spectrum input clock tracking (1)

Yes—Source synchronous compensation

YesYesDirect compensation

YesYesNormal compensation

Yes—Zero-delay buffer compensation

Yes—External feedback compensation

Yes—LVDS compensation

(1) Provided input clock jitter is within input jitter tolerance specifications.


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I/O PLLFractional PLLFeature

—YesIQTXRXCLK compensation

—YesFractional PLL bonding compensation

Yes—Voltage-controlled oscillator (VCO) outputdrives the DPA clock

78.125 ps41.667 psPhase shift resolution (2)

YesFixed 50% duty cycleProgrammable duty cycle

YesYesPower down mode

PLL UsageFractional PLLs are optimized for use as transceiver transmit PLLs and for synthesizing reference clockfrequencies. You can use the fractional PLLs as follows:

• Reduce the number of required oscillators on the board• Reduce the clock pins used in the FPGAby synthesizingmultiple clock frequencies from a single reference

clock source• Compensate clock network delay• Transmit clocking for transceivers

I/O PLLs are optimized for use with memory interfaces and LVDS SERDES. You can use the I/O PLLs asfollows:

• Reduce the number of required oscillators on the board• Reduce the clock pins used in the FPGAby synthesizingmultiple clock frequencies from a single reference

clock source• Simplify the design of external memory interfaces and high-speed LVDS interfaces• Close timing easily because the I/O PLLs are tightly coupled with the I/Os• Compensate clock network delay• Zero delay buffering

(2) The smallest phase shift is determined by the VCO period divided by four (for fractional PLL) or eight (for I/O PLL). For degree increments, the Arria 10 device can shift all output frequencies in increments of at least45° (for I/OPLL) or 90° (for fractional PLL). Smaller degree increments are possible depending on the frequencyand divide parameters.


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PLL ArchitectureFigure 4-13: Fractional PLL High-Level Block Diagram for Arria 10 Devices

ClockSwitchover

Block

inclk0

inclk1

Dedicated Clock Inputs

Cascade Input fromAdjacent Fractional PLL

and Dedicated refclk

clkswitchclkbad0clkbad1activeclock

PFD

LockCircuit pll_locked

÷N CP LF VCO

GCLK/RCLK

44

GCLK/RCLK Network

Direct Compensation ModeNormal Mode

÷C0

÷C1

÷C2

÷C3

÷M

PLLOutpu

tMultiplexer

Casade Output toAdjacent Fractional PLLGCLKs

RCLKs

FBOUT

÷L

Delta SigmaModulator

This FBOUT port is fed bythe M counter in the PLLs.

For single-ended clock inputs, only the CLKp pinhas a dedicated connection to the PLL. If you use theCLKn pin, a global or regional clock is used.

PMA Clocks

Fractional PLL Bonding ModeIQTXRXCLK Mode

L CounterIQTXRXCLK Network

Figure 4-14: I/O PLL High-Level Block Diagram for Arria 10 Devices

ClockSwitchover

Block

inclk0

inclk1

Cascade Inputfrom Adjacent I/O PLLand Dedicated refclk

clkswitchclkbad0clkbad1activeclock

PFD

LockCircuit locked

÷N CP LF VCO

GCLK/RCLK

4

FBINDIFFIOCLK NetworkGCLK/RCLK Network

Direct Compensation ModeZero Delay Buffer, External Feedback ModesLVDS Compensation ModeSource Synchronous, Normal Modes

÷C0

÷C1

÷C2

÷C3

÷C8

÷M

PLLOutpu

tMultiplexer

Casade Outputto Adjacent I/O PLL

GCLKs

RCLKs

FBOUT

External MemoryInterface DLL

88

To DPA Block

RX/TX Clock

RX/TX Load Enable

For single-ended clock inputs, only the CLKp pinhas a dedicated connection to the PLL. If you use theCLKn pin, a global or regional clock is used.

Dedicated Clock Inputs

This FBOUT port is fed bythe M counter in the PLLs.

PLL Control SignalsYou can use the reset signal to control PLL operation and resynchronization, and use the locked signal toobserve the status of the PLL.

Reset

The reset signal port of the megafunction for each PLL is as follows:

• Fractional PLL—pll_powerdown

• I/O PLL—reset

The reset signal is the reset or resynchronization input for each PLL. The device input pins or internal logiccan drive these input signals.


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When the reset signal is driven high, the PLL counters reset, clearing the PLL output and placing the PLLout-of-lock. The VCO is then set back to its nominal setting. When the reset signal is driven low again, thePLL resynchronizes to its input as it re-locks.

You must assert the the reset signal every time the PLL loses lock to guarantee the correct phase relationshipbetween the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after aloss-of-lock condition using the Quartus II MegaWizard™ Plug-In Manager.

You must include the reset signal if either of the following conditions is true:

• PLL reconfiguration or clock switchover is enabled in the design• Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock

condition

If the input clock to the PLL is not toggling or is unstable after power up, assert the reset signal afterthe input clock is stable and within specifications.

Note:

Locked

The locked signal port of the megafunction for each PLL is as follows:

• Fractional PLL—pll_locked

• I/O PLL—locked

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clockhas locked onto the reference clock both in phase and frequency.

Clock Feedback ModesThe default clock feedback mode is direct compensation mode.

Fractional PLLs support the following clock feedback modes:

• Direct compensation• Normal compensation• Fractional PLL bonding compensation• IQTXRXCLK compensation

I/O PLLs support the following clock feedback modes:

• Direct compensation• Normal compensation• Source synchronous compensation• LVDS compensation• Zero delay buffer (ZDB) compensation• External feedback (EFB) compensation

Clock Multiplication and DivisionAn Arria 10 PLL output frequency is related to its input reference clock source by a scale factor of M/(N × C)in integer mode. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedbackfactor. The control loop drives the VCO to match fin × (M/N).


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4-17LockedA10-CLKPLL2013.12.02


TheQuartus II software automatically chooses the appropriate scale factors according to the input frequency,multiplication, and division values entered into theAltera PLLmegafunction for I/OPLL andArria_10_FPLLmegafunction for fractional PLL.

Pre-Scale Counter, N and Multiply Counter, M

Each PLL has one pre-scale counter, N, and one multiply counter, M. The M and N counters do not use duty-cycle control because the only purpose of these counters is to calculate frequency division.

Post-Scale Counter, C

Each output port has a unique post-scale counter, C. For multiple C counter outputs with differentfrequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequencyspecifications. For example, if the output frequencies required from one fractional or I/O PLL are 55 MHzand 100 MHz, the Quartus II software sets the VCO frequency to 1.1 GHz (the least common multiple of55 MHz and 100 MHz within the VCO operating frequency range). Then the post-scale counters, C, scaledown the VCO frequency for each output port.

Post-Scale Counter, L

The fractional PLL has an additional post-scale counter, L. The L counter synthesizes the frequency fromits clock source using the M/(N × L) scale factor. The L counter generates a differential clock pair (0 degreeand 180 degree) and drives the HSSI clock network.

Delta-Sigma Modulator

The delta-sigma modulator (DSM) is used together with the M multiply counter to enable the fractional PLLto operate in fractional mode. The DSM dynamically changes the M counter factor on a cycle-to-cycle basis.The different M counter factors allow the "average" M counter factor to be a non-integer.

Fractional Mode

In fractional mode, the M counter value equals to the sum of the M feedback factor and the fractional value.The fractional value is equal to K/2X, where K is an integer between 0 and (2X – 1), and X = 32.

Integer Mode

For a fractional PLL operating in integer mode, M is an integer value and DSM is disabled.

The I/O PLL can only operate in integer mode.

Related InformationAltera Phase-Locked Loop (Altera PLL) Megafunction User GuideProvides more information about I/O PLL software support in the Quartus II software.

Programmable Phase ShiftThe programmable phase shift feature allows both fractional PLLs and I/O PLLs to generate output clockswith a fixed phase offset.

The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shiftincrement is 1/8 (for I/O PLL) or 1/4 (for fractional PLL) of the VCO period. For example, if an I/O PLLoperates with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible.


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TheQuartus II software automatically adjusts theVCO frequency according to the user-specified phase shiftvalues entered into the megafunction.

Programmable Duty CycleThe programmable duty cycle feature allows I/O PLLs to generate clock outputs with a variable duty cycle.This feature is only supported by the I/O PLL post-scale counters, C. Fractional PLLs do not have supportprogrammable duty cycle feature and only have fixed 50% duty cycle. To determine the duty cycle options,the Quartus II software uses the frequency input and the required frequency scale factor.

The I/O PLL C counter value determines the precision of the duty cycle. The precision is 50% divided bythe post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty-cycleoptions from 5% to 90%. If the I/O PLL is in external feedback mode, set the duty cycle for the counterdriving the fbin pin to 50%.

Combining the programmable duty cycle with programmable phase shift allows the generation of precisenon-overlapping clocks.

Clock SwitchoverThe clock switchover feature allows the PLL to switch between two reference input clocks. Use this featurefor clock redundancy or for a dual-clock domain application where a system turns on the redundant clockif the previous clock stops running. The design can perform clock switchover automatically when the clockis no longer toggling or based on a user control signal, clkswitch.

Arria 10 PLLs support the following clock switchover modes:

• Automatic switchover—The clock sense circuit monitors the current reference clock. If the currentreference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.

• Manual clock switchover—Clock switchover is controlled using the clkswitch signal. When theclkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles for theinclk being switched to, the reference clock to the PLL is switched from inclk0 to inclk1, or vice-versa.

• Automatic switchover with manual override—This mode combines automatic switchover and manualclock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchoverfunction. As long as the clkswitch signal is high, further switchover action is blocked.

Automatic Switchover

Arria 10 PLLs support a fully configurable clock switchover capability.


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Figure 4-15: Automatic Clock Switchover Circuit Block Diagram

This figure shows a block diagram of the automatic switchover circuit built into the PLL.

ClockSense Switchover

State Machine

Clock SwitchControl Logic

N Counterinclk0

inclk1

MultiplexerOut

clkbad[0]

clkbad[1]

activeclock

clkswitch

refclkfbclk

clksw

PFD

When the current reference clock is not present, the clock sense block automatically switches to the backupclock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1port of the PLL in your design.

The clock switchover circuit sends out three status signals—clkbad[0], clkbad[1], andactiveclock—from the PLL to implement a custom switchover circuit in the logic array.

In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the twoclock inputs. When they are asserted, the clock sense block detects that the corresponding clock input hasstopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1is greater than 20%.

The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selectedas the reference clock to the PLL. When the frequency difference between the two clock inputs is more than20%, the activeclock signal is the only valid status signal.

Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the currentreference clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1any number of times when one of the two clocks fails and the other clock is available.

For example, in applications that require a redundant clock with the same frequency as the reference clock,the switchover state machine generates a signal (clksw) that controls the multiplexer select input. In thiscase, inclk1 becomes the reference clock for the PLL.

When using automatic clock switchover mode, the following requirements must be satisfied:

• Both clock inputs must be running when the FPGA is configured.• The period of the two clock inputs can differ by no more than 20%.

The input clocks must meet the input jitter specifications to ensure proper operation of the status signals.Glitches in the input clock may be seen as a greater than 20% difference in frequency between the inputclocks.

If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiatedand the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their


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period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLLmay lose lock after the switchover is completed and needs time to relock.

You must reset the PLL using the reset signal to maintain the phase relationships between the PLLinput and output clocks when using clock switchover.

Note:

Figure 4-16: Automatic Switchover After Loss of Clock Detection

This figure shows an example waveform of the switchover feature in automatic switchover mode. In thisexample, the inclk0 signal is stuck low. After the inclk0 signal is stuck at low for approximately twoclock cycles, the clock sense circuitry drives the clkbad[0] signal high. Since the reference clock signalis not toggling, the switchover state machine controls the multiplexer through the clkswitch signal toswitch to the backup clock, inclk1.

inclk0

inclk1

muxout

clkbad0

clkbad1

activeclock

Switchover is enabled on the fallingedge of inclk0 or inclk1, dependingon which clock is available. In thisfigure, switchover is enabled on thefalling edge of inclk1.

Automatic Switchover with Manual Override

In automatic switchoverwithmanual overridemode, you can use the clkswitch signal for user- or system-controlled switch conditions. You can use this mode for same-frequency switchover, or to switch betweeninputs of different frequencies.

For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using theclkswitch signal. The automatic clock-sense circuitry cannotmonitor clock input (inclk0 and inclk1)frequencies with a frequency difference of more than 100% (2×).

This feature is useful when the clock sources originate from multiple cards on the backplane, requiring asystem-controlled switchover between the frequencies of operation.

You must choose the backup clock frequency and set the M, N, C, L, and K counters so that the VCO operateswithin the recommended operating frequency range. The Altera PLL (for I/O PLL) and Arria_10_FPLL (forfractional PLL)MegaWizard Plug-inManagers notifies you if a given combination of inclk0 and inclk1frequencies cannot meet this requirement.


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4-21Automatic Switchover with Manual OverrideA10-CLKPLL2013.12.02


Figure 4-17: Clock Switchover Using the clkswitch (Manual) Control

This figure shows a clock switchover waveform controlled by the clkswitch signal. In this case, bothclock sources are functional and inclk0 is selected as the reference clock; the clkswitch signal goeshigh, which starts the switchover sequence. On the falling edge of inclk0, the counter’s reference clock,muxout, is gated off to prevent clock glitching.On the falling edge of inclk1, the reference clockmultiplexerswitches from inclk0 to inclk1 as the PLL reference. The activeclock signal changes to indicatethe clock which is currently feeding the PLL.

inclk0

inclk1

muxout

clkbad0

clkbad1

activeclock

clkswitch

To initiate a manual clock switchover event,both inclk0 and inclk1 must be running whenthe clkswitch signal goes high.

In automatic override with manual switchover mode, the activeclock signal mirrors the clkswitchsignal. Since both clocks are still functional during the manual switch, neither clkbad signal goes high.Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does notcause the circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again,the process repeats.

The clkswitch signal and automatic switch work only if the clock being switched to is available. If theclock is not available, the state machine waits until the clock is available.


Manual Clock Switchover

Inmanual clock switchovermode, the clkswitch signal controls whether inclk0 or inclk1 is selectedas the input clock to the PLL. By default, inclk0 is selected.

A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high,and being held high for at least three inclk cycles for the inclk being switched to.

You must bring the clkswitch signal back low again to perform another switchover event. If you do notrequire another switchover event, you can leave the clkswitch signal in a logic high state after the initialswitch.

Pulsing the clkswitch signal high for at least three inclk cycles for the inclk being switched toperforms another switchover event.


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If inclk0 and inclk1 are different frequencies and are always running, the clkswitch signalminimumhigh time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.

Figure 4-18: Manual Clock Switchover Circuitry in Arria 10 PLLs

Clock SwitchControl Logic

N Counter PFDinclk0

inclk1

muxout refclk fbclk

clkswitch

You can delay the clock switchover action by specifying the switchover delay in the Altera PLL (for I/O PLL)and Arria_10_FPLL (for fractional PLL) megafunctions. When you specify the switchover delay, theclkswitch signal must be held high for at least three inclk cycles for the inclk being switched to plusthe number of the delay cycles that has been specified to initiate a clock switchover.


Guidelines

When implementing clock switchover in Arria 10 PLLs, use the following guidelines:

• Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of eachother. Failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not functionproperly.

• When using manual clock switchover, the difference between inclk0 and inclk1 can be more than100% (2×). However, differences in frequency, phase, or both, of the two clock sources will likely causethe PLL to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships betweenthe input and output clocks.

• Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate themanual clock switchover event. Failing to meet this requirement causes the clock switchover to notfunction properly.

• Applications that require a clock switchover feature and a small frequency driftmust use a low-bandwidthPLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a high-bandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clockto the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLLalso increases lock time.

• After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a newclock. The time it takes for the PLL to relock depends on the PLL configuration.

• The phase relationship between the input clock to the PLL and the output clock from the PLL is importantin your design. Assert the reset signal for at least 10 ns after performing a clock switchover. Wait for thelocked signal to go high and be stable before re-enabling the output clocks from the PLL.

• The VCO frequency gradually decreases when the current clock is lost and then increases as the VCOlocks on to the backup clock, as shown in the following figure.


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Figure 4-19: VCO Switchover Operating Frequency

∆Fvco

Primary Clock Stops Running

VCO Tracks Secondary Clock

Switchover Occurs

PLL Reconfiguration and Dynamic Phase ShiftFractional PLLs and I/O PLLs support PLL reconfiguration and dynamic phase shift with the followingfeatures:

• PLL reconfiguration—Reconfigure the M, N, and C counters.• Dynamic phase shift—Perform positive or negative phase shift. Able to shift multiple phase steps each

time, with one phase step is equal to 1/8 (for I/O PLL) or 1/4 (for fractional PLL) of the VCO period.

Document Revision History

ChangesVersionDate

Initial release.2013.12.02December 2013


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Clock Networks and PLLs - Altera · Clock Networks and PLLs in Arria 10 Devices 4 2013.12.02 A10-CLKPLL Subscribe Send Feedback Thischapterdescribestheadvancedfeaturesofhierarchicalclocknetworksandphase