70
Altera Corporation 1 February 2002, ver. 1.0 Application Note 200 AN-200-1.0 Introduction Preliminary Information Stratix TM devices have highly versatile phase-locked loops (PLLs) that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces. There are two types of PLLs in each Stratix device: enhanced PLLs and fast Plls. Each device has up to four enhanced PLLs, which are feature-rich, general-purpose PLLs supporting advanced capabilities such as external feedback, clock switchover, phase and delay control, PLL reconfiguration, spread spectrum clocking, and programmable bandwidth. There are also up to eight fast PLLs per device, which offer general-purpose clock management with multiplication and phase shifting as well as high-speed outputs to manage the high-speed differential I/O interfaces. The Altera Quartus II software enables the PLLs and their features without requiring any external devices. Table 1 shows the PLLs available for each Stratix device and their type. Notes to Table 1: (1) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. (2) PLLs 11 and 12 each have one single-ended output. Table 1. Stratix Device PLL Availability Device Fast PLLs Enhanced PLLs 1 2 3 4 7 8 9 10 5 (1) 6 (1) 11 (2) 12 (2) EP1S10 v v v v v v EP1S20 v v v v v v EP1S25 v v v v v v EP1S30 v v v v v v v v v v EP1S40 v v v v v v v v v v v v EP1S60 v v v v v v v v v v v v EP1S80 v v v v v v v v v v v v EP1S120 v v v v v v v v v v v v Using PLLs in Stratix Devices

Using PLLs in Stratix Devices - extras.springer.comextras.springer.com/2001/978-0-306-47635-8/an/an200.pdf · (5) PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3,

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Page 1: Using PLLs in Stratix Devices - extras.springer.comextras.springer.com/2001/978-0-306-47635-8/an/an200.pdf · (5) PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3,

February 2002, ver. 1.0 Application Note 200

Using PLLs in StratixDevices

Introduction

Preliminary Information

StratixTM devices have highly versatile phase-locked loops (PLLs) that provide robust clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces. There are two types of PLLs in each Stratix device: enhanced PLLs and fast Plls. Each device has up to four enhanced PLLs, which are feature-rich, general-purpose PLLs supporting advanced capabilities such as external feedback, clock switchover, phase and delay control, PLL reconfiguration, spread spectrum clocking, and programmable bandwidth. There are also up to eight fast PLLs per device, which offer general-purpose clock management with multiplication and phase shifting as well as high-speed outputs to manage the high-speed differential I/O interfaces.

The Altera Quartus II software enables the PLLs and their features without requiring any external devices.

Table 1 shows the PLLs available for each Stratix device and their type.

Notes to Table 1:(1) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs.(2) PLLs 11 and 12 each have one single-ended output.

Table 1. Stratix Device PLL Availability

Device Fast PLLs Enhanced PLLs

1 2 3 4 7 8 9 10 5 (1) 6 (1) 11 (2) 12 (2)

EP1S10 v v v v v v

EP1S20 v v v v v v

EP1S25 v v v v v v

EP1S30 v v v v v v v v v v

EP1S40 v v v v v v v v v v v v

EP1S60 v v v v v v v v v v v v

EP1S80 v v v v v v v v v v v v

EP1S120 v v v v v v v v v v v v

Altera Corporation 1

AN-200-1.0

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Table 2 shows the enhanced PLL and fast PLL features in Stratix devices.

Notes to Table 2:(1) For enhanced PLLs, m and n counters range from 1 to 512.(2) For fast PLLs, m, n, and post-scale counters range from 1 to 32.(3) The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.(4) For degree increments, Stratix devices can shift all output frequencies in increments of at least 45°. Smaller degree

increments are possible depending on the frequency and divide parameters.(5) PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL.(6) Every Stratix device has two enhanced PLLs with eight single-ended or four differential outputs each. Two

additional enhanced PLLs in EP1S120, EP1S80, EP1S60, and EP1S40 devices each have one single-ended output.(7) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data

channel to generate txclkout.(8) Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.

Figure 1 shows a top-level diagram of the Stratix device and PLL floorplan. See “Clocking” on page 57 for more detail on PLL connections to global and regional clocks.

Table 2. Stratix PLL Features

Feature Enhanced PLL Fast PLL

Clock multiplication and division m/(n × post-scale counter) (1) m/(post-scale counter) (2)

Phase shift Down to 160-ps increments (3), (4) Down to 150-ps increments (3), (4)

Delay shift 250-ps increments for ±3 ns

Clock switchover v

PLL reconfiguration v

Programmable bandwidth v

Spread spectrum clocking v

Programmable duty cycle v v

Number of internal clock outputs 6 3 (5)

Number of external clock outputs Four differential/eight singled-ended or one single-ended (6)

(7)

Number of feedback clock inputs 4 (8)

2 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 1. PLL Locations

FPLL7CLK FPLL10CLK

FPLL9CLK

CLK8-11

FPLL8CLK

CLK0-3

7

1

2

8

10

4

3

9

115

126

CLK4-7

CLK12-15

PLLs

Altera Corporation 3

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Enhanced PLLs Stratix devices contain up to four enhanced PLLs with advanced clock management features. Figure 2 shows a diagram of the enhanced PLL.

Figure 2. Stratix Enhanced PLL

Notes to Figure 2:(1) External feedback is available in PLLs 5 and 6.(2) This external output is available from the g0 counter for PLLs 11 and 12.(3) These four counters and external outputs are available in PLLs 5 and 6.

÷n ChargePump VCO ÷g0

÷g1

÷g2

÷e0

8

4

GlobalClocks

÷e1

÷e2

I/O Buffers (3)

÷e3 ∆t

∆t

∆t

∆t

∆t

∆t

∆t

∆t

Lock Detect to I/O or generalrouting

INCLK0

INCLK1

FBIN

÷g3

÷l1

÷l0

From Adjacent PLL

÷m

SpreadSpectrum

I/O Buffers (2)(1)

LoopFilter

& Filter

Programmable Time Delay on Each PLL Port

Post-ScaleCounters

ClockSwitch-Over

Circuitry Phase FrequencyDetector (PFD)

VCO Phase SelectionSelectable at EachPLL Output Port

VCO Phase SelectionAffecting All Outputs

∆t

∆t

∆tn

∆tm

RegionalClocks

4

4 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 3 shows all the possible ports of the enhanced PLLs.

Figure 3. Enhanced PLL Signals

Notes to Figure 3:(1) This input pin is shared by all enhanced and fast PLLs.(2) These are either single-ended or differential pins.

inclk0

inclk1

clkswitch

scandata

scanclk

pllenableclk[5..0]

locked

Physical Pin

clklossareset

clkena[5..0]

pfdena

Signal Driven by Internal Logic

Signal Driven to Internal Logic

Internal Clock Signal

extclk4

extclkena[3..0]

extclk0_Afbin Only PLLs 5 and 6

clkbad[1..0]

(1)

(2)

(2)

extclk0_B

extclk1_A

extclk1_B

extclk2_A

extclk2_B

extclk3_A

extclk3_B

scanaclr

(2)

Only PLLs 11 and 12

Altera Corporation 5

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Tables 3 and 4 describe all the enhanced PLL ports.

Table 3. Enhanced PLL Input Signals

Port Description Source Destination

inclk[1..0] Primary and secondary reference clock inputs to PLL

Pin ÷n counter

fbin External feedback input to the PLL (PLLs 5 and 6 only)

Pin PFD

pllena Enable pin for enabling or disabling all or a set of PLLsactive high

Pin General PLL control signal

clkswitch Switch-over signal used to initiate external clock switch-over controlactive high

Logic array PLL switch-over circuit

areset Signal used to reset the PLL which will re-synchronize all the counter outputsactive high

Logic array General PLL control signal

clkena[5..0] Enable clock driving regional or global clockactive high

Logic array Clock output

extclkena[3..0] Enable clock driving external clock (PLLs 5 and 6 only)active high

Logic array Clock output

pfdena Enables the outputs from the phase frequency detectoractive high

Logic array PFD

scanclk Serial clock signal for the real-time PLL control feature

Logic array Reconfiguration circuit

scandata Serial input data stream for the real-time PLL control feature

Logic array Reconfiguration circuit

scanaclr Serial shift register reset clearing all registers in the serial shift chainactive low

Logic array Reconfiguration circuit

6 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Clock Multiplication & Division

Each Stratix device enhanced PLL provides clock synthesis for PLL output ports using m/(n × post-scale counter) scaling factors. The input clock is divided by a pre-scale counter, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN × (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale counters scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, set the VCO to 330 MHz (the least common multiple in the VCO’s range). There is one pre-scale counter, n, and one multiply counter, m, per PLL, with a range of 1 to 512 on each. There are two post-scale counters (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 512. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered.

Table 4. Enhanced PLL Output Signals

Port Description Source Destination

clk[5..0] PLL outputs driving regional or global clock PLL counter Internal Clock

extclk[3..0]p/n extclk[3..0] are PLL outputs driving the four differential or eight single-ended external clock output pins for PLLs 5 or 6. p or n are the positive (p) and negative (n) pins for differential pins. extclk0 is a PLL output driving the one single-ended clock pin for PLLs 11 or 12.

PLL counter Pin(s)

extclk4 PLL output driving external clock output pin from PLLs 11 and 12

PLL g0 counter

Pin

clkloss Signal indicating the switch-over circuit detected a switch-over condition

PLL switch-over circuit

Logic array

clkbad[1..0] Signals indicating which reference clock is no longer toggling. clkbad1 indicates inclk1 status, clkbad0 indicates inclk0 status

PLL switch-over circuit

Logic array

locked Lock or gated lock output from lock detect circuitactive high

PLL lock detect

Logic array

activeclock Signal to indicate which clock (1 = inclk0 or 0 = inclk1) is driving the PLL.

PLL clock multiplexer

Logic array

Altera Corporation 7

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AN 200: Using PLLs in Stratix Devices Preliminary Information

External Clock Outputs

Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). See Figure 4.

Figure 4. External Clock Outputs for PLLs 5 & 6

Notes to Figure 4:(1) LE: logic element.(2) The design can use each external clock output pin as a general-purpose output pin

from the logic array. These pins are multiplexed with IOE outputs.(3) Two single-ended outputs are possible per output countereither two outputs of

the same frequency and phase or one shifter 180°.

e0 Counter

extclk0_a

extclk0_b

extclk1_a

extclk1_b

extclk2_a

extclk2_b

extclk3_a

extclk3_b

e1 Counter

e2 Counter

e3 Counter

From IOE (1), (2)

From IOE (1)

From IOE (1)

From IOE (1)

From IOE (1)

From IOE (1)

From IOE (1)

From IOE (1)4

(3)

8 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock’s overall jitter by providing improved isolation from switching I/O pins.

For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180° out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, PCML, HyperTransportTM technology, differential HSTL, and differential SSTL. Table 5 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. Designers can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed.

Altera Corporation 9

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 5). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin.

Table 5. I/O Standards Supported for Enhanced PLL Pins

I/O Standard Input Output

INCLK FBIN PLLENABLE EXTCLK

LVTTL v v v v

LVCMOS v v v v

2.5 V v v v

1.8 V v v v

1.5 V v v v

3.3-V PCI v v v

3.3-V PCI-X v v v

LVPECL v v v

PCML v v v

LVDS v v v

HyperTransport technology v v v

Differential HSTL v v

Differential SSTL v

3.3-V GTL v v v

3.3-V GTL+ v v v

1.5-V HSTL class I v v v

1.5-V HSTL class II v v v

SSTL-18 class I v v v

SSTL-18 class II v v v

SSTL-2 class I v v v

SSTL-2 class II v v v

SSTL-3 class I v v v

SSTL-3 class II v v v

AGP (1× and 2×) v v v

CTT v v v

10 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 5. External Clock Outputs for Enhanced PLLs 11 & 12

Note to Figure 5:(1) For PLL11, this pin is CLK13n; for PLL 12 this pin is CLK6n.

Stratix devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases.

Clock Feedback

The following three feedback modes in Stratix device enhanced PLLs allow multiplication and/or phase and delay shifting:

Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay.

External feedback: The external feedback input pin, FBIN, is phase-aligned with the clock input, CLK, pin. Aligning these clocks allows the designer to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback for one of the dedicated external outputs, either one single-ended or one differential pair. In this mode, one e counter feeds back to the PLL FBIN input, becoming part of the feedback loop.

Normal mode: If an internal clock is used in this mode, it is phase-aligned to the input clock pin. The external clock output pin will have a phase delay relative to the clock input pin if connected in this mode.

Phase & Delay Shifting

Stratix device enhanced PLLs provide advanced programmable phase and clock delay shifting. These parameters are set in the Quartus II software.

CLK13n, I/O, PLL11_OUTor CLK6n, I/O, PLL12_OUT (1)

From InternalLogic or IOE

g0Counter

Altera Corporation 11

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Phase Delay

The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. The designer enters a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. For phase shifting, enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Designers can select phase-shifting values in time units with a resolution of 160 to 420 ps. This resolution is a function of frequency input and the multiplication and division factors (i.e., it is a function of the VCO period), with the finest step being equal to an eighth (×0.125) of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps for individual fine step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one VCO period. The combination of coarse and fine shifts allows phase shifting for the entire input clock period.

The equation to determine the precision of the phase shifting in degrees is: 45° ÷ post-scale counter value. Therefore, the maximum step size is 45°, and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port.

This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation.

Clock Delay

In addition to the phase shift feature, the ability to fine tune the ∆t clock delay provides advanced time delay shift control on each of the four PLL outputs. There are time delays for each post-scale counter (e, g, or l) from the PLL, the n counter, and m counter. Each of these can shift in 250-ps increments for a range of 3.0 ns. The m delay shifts all outputs earlier in time, while n delay shifts all outputs later in time. Individual delays on post-scale counters (e, g, and l) provide positive delay for each output. Table 6 shows the combined delay for each output for normal or zero delay buffer mode where ∆te, ∆tg, or ∆tl is unique for each PLL output.

The tOUTPUT for a single output can range from –3 ns to +6 ns. The total delay shift difference between any two PLL outputs, however, must be less than ±3 ns. For example, shifts on two outputs of –1 and +2 ns is allowed, but not –1 and +2.5 ns because these shifts would result in a difference of 3.5 ns. If the design uses external feedback, the ∆te delay will remove delay from outputs, represented by a negative sign (see Table 6). This effect occurs because the ∆te delay is then part of the feedback loop.

12 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Note to Table 6:(1) ∆te removes delay from outputs in external feedback mode.

There is some delay variation due to process, voltage, and temperature which is accounted for by a ±15% tolerance on the delay settings. PLL reconfiguration can control the clock delay shift elements, but not the VCO phase shift multiplexers, during system operation.

Lock Detect & Programmable Gated Locked

The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. A designer may need to gate the lock signal for use as a system control. The enhanced PLL includes a programmable counter that holds the lock signal low for a user-selected number of input clock transitions. This allows the PLL to lock before enabling the lock signal. The designer can use the Quartus II software to set the 20-bit counter value. Either a gated lock signal or an ungated lock signal from the locked port can drive the logic array or an output pin. The device resets and enables both the counter and the PLL simultaneously upon power-up and/or assertion of pllenable.

Designers can also combine the lock detection with the CONF_DONE signal. This signal indicates that the configuration is complete. The designer can use the programmable CONF_DONE qualifier in the Quartus II software to hold the CONF_DONE signal low until the PLL(s) lock.

Figure 6 shows the timing waveform for locked and gated locked signals.

Table 6. Output Clock Delay for Enhanced PLLs

Normal or Zero Delay Buffer Mode External Feedback Mode

∆teOUTPUT = ∆tn − ∆tm + ∆te∆tgOUTPUT = ∆tn − ∆tm + ∆tg∆tlOUTPUT = ∆tn − ∆tm + ∆tl

∆teOUTPUT = ∆tn − ∆tm − ∆te (1)∆tgOUTPUT = ∆tn − ∆tm + ∆tg∆tlOUTPUT = ∆tn − ∆tm + ∆tl

Altera Corporation 13

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 6. Gated Lock Signal

Programmable Duty Cycle

The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale counters. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices. The precision of the duty cycle is determined by the post-scale counter value chosen on an output. The precision is defined by 50% divided by the post-scale counter value. The closest value to 100% is not achievable for a given counter value. For example, if the g0 counter is 10, then steps of 5% are possible for duty cycle choices between 5 to 90%.

If the device uses external feedback, the designer must set the duty cycle for the counter driving off the device to 50%.

General Advanced Clear & Enable Control

There are several control signals for clearing and enabling PLLs and their outputs. The designer can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications.

REFCLK

FBCLK

LOCKED

Gated LOCKED

PLLENABLE

Counter ReachesProgrammed Count

14 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. The designer can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin.

The areset signals are reset/resynchronization inputs for each PLL. Stratix device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters will reset, clearing the PLL output and placing the PLL out of lock. The VCO will set back to its nominal setting (~700 MHz). When driven low again, the PLL will resynchronize to its input as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency will start at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks.

The pfdena signals control the PFD output with a programmable gate. If the designer disables the PFD, the VCO will operate at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system will continue running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. Designers can either use their own control signal or clkloss or gated locked status signals to trigger pdfena.

The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 7 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization.

The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin.

Altera Corporation 15

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 7. extclkena Signals

Programmable Bandwidth

Enhanced PLLs provide advanced control of the PLL bandwidth using the programmable characteristics of the PLL loop, including loop filter and charge pump.

1 For more information, see Application Note 213 (Understanding PLL & Timing Terminology).

Background

The PLL bandwidth is the measure of the PLLs ability to track the input clock and jitter. It is determined by the −3-dB frequency of the closed-loop gain in the PLL or approximately the unity gain point for open loop PLL response. As Figure 8 shows, these points correspond to approximately the same frequency.

COUNTEROUTPUT

CLKENA

CLKOUT

16 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 8. Open- & Closed-Loop Response Bode Plots

Increasing the PLL'sbandwidth in effect pushesthe open loop response out.

Gain

Gain

0 dB

Frequency

Frequency

Open-Loop Reponse Bode Plot

Closed-Loop Reponse Bode Plot

Altera Corporation 17

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AN 200: Using PLLs in Stratix Devices Preliminary Information

A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference clock source, passing it through to the PLL output. A low-bandwidth PLL filters out reference clock jitter, but increases lock time. Stratix device enhanced PLLs allow the designer to control the bandwidth over a finite range to customize the PLL characteristics for a particular application. Applications that require clock switch-over (such as TDMA, frequency hopping wireless, and redundant clocking) can benefit from the programmable bandwidth feature of the Stratix PLLs.

The bandwidth and stability of such a system is determined by a number of factors including the charge pump current, the loop filter resistor value, the high-frequency capacitor value (in the loop filter), and the m-counter value. The designer can use the Quartus II software to control these factors and to set the bandwidth to the desired value within a given range.

The designer can set the bandwidth to the appropriate value to balance the need for jitter filtering and lock time. Figures 9 and 10 show the output of a low- and high-bandwidth PLL, respectively, as it locks onto the input clock.

18 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 9. Low-Bandwidth PLL Lock Time

0 5 1510

Time (µs)

Frequency (MHz)

120

125

130

135

140

145

150

155

160

Lock Time = 8 µs

Altera Corporation 19

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 10. High-Bandwidth PLL Lock Time

A high-bandwidth PLL may benefit a system with two cascaded PLLs. If the first PLL uses spread spectrum (as user-induced jitter), the second PLL needs a high bandwidth so it can track the jitter that is feeding it. A low-bandwidth PLL may, in this case, lose lock due to the spread spectrum-induced jitter on the input clock.

A low-bandwidth PLL may benefit a system using clock switchover. When the clock switchover happens, the PLL input temporarily stops. A low-bandwidth PLL would react more slowly to changes to its input clock and take longer to drift to a lower frequency (caused by the input stopping) than a high-bandwidth PLL. Figures 11 and 12 demonstrate this property. The two plots show the effects of clock switchover with a low- or high-bandwidth PLL. When the clock switchover happens, the output of the low-bandwidth PLL (see Figure 11) drifts to lower frequency much slower than the high-bandwidth PLL output (see Figure 12).

0120

125

130

135

140

145

150

155

160

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (µs)

Frequency (MHz)

Lock Time = 4 µs

20 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 11. Effect of Low Bandwidth on Clock Switchover

0150

152

154

156

158

160

162

164

5 10 15 20 25 30 35 40

Time (µs)

Frequency (MHz)

Initial Lock

Input Clock Stops Re-lock

Switchover

Altera Corporation 21

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 12. Effect of High Bandwidth on Clock Switchover

Implementation

Traditionally, external components such as the VCO or loop filter control a PLL’s bandwidth. Most loop filters are made up of passive components, such as resistors and capacitors, which take up unnecessary board space and increase cost. With Stratix device enhanced PLLs, all the components are contained within the device to increase performance and decrease cost.

Stratix device enhanced PLLs implement programmable bandwidth by giving the designer control of the charge pump current and loop filter resistor (R) and high-frequency capacitor (Ch) values (see Table 7). The Stratix device enhanced PLL bandwidth ranges from approximately 200 kHz to 1.5 MHz.

The charge pump current directly affects the PLL bandwidth. The higher the charge pump current, the higher the PLL bandwidth. The designer can choose from a fixed set of values for the charge pump current. Figure 13 shows the loop filter and the components that designers can set via the Quartus II software.

0

125

130

135

140

145

150

155

160

2 4 6 8 10 12 14 16 18 20

Time (µs)

Frequency (MHz)

Initial Lock

Input Clock Stops Re-lock

Switchover

22 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 13. Loop Filter Programmable Components

Software Support

The Quartus II software provides two levels of programmable bandwidth control. The first level allows the designer to enter a value for the desired bandwidth directly into the Quartus II software using the MegaWizardTM Plug-In Manager. Alternatively, designers can set the bandwidth parameter in the altpll function to the desired bandwidth. The Quartus II software then chooses each individual bandwidth parameter to achieve the desired setting. If designs cannot achieve the desired bandwidth setting, the Quartus II software will select the closest achievable value. This feature is not supported in version 2.0 of the Quartus II software.

An advanced level of control is also possible for precise control of the loop filter parameters. This level allows the designer to specifically select the charge pump current, loop filter resistor value, and loop filter (high frequency) capacitor value. These parameters are: charge_pump_current, loop_filter_r, and loop_filter_c. Each parameter supports the specific range of values listed in Table 7.

IUP

IDN

Ch

PFD

R

C

Altera Corporation 23

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AN 200: Using PLLs in Stratix Devices Preliminary Information

The designer manually enters these values into the Quartus II software via the PLL instance’s parameters using the following steps:

1. Open the PLL instance with the MegaWizard Plug-In Manager.

2. Enter the desired value for each parameter in the appropriate box.

3. Once the desired values are entered, click Finish to update the PLL instance with the new settings.

4. After compiling the design, check the Compiler Report for detailed information regarding the PLL, including the settings.

1 If a design uses one advanced parameter, it must use all of them. For example, if the MegaWizard Plug-In Manager specifies the charge_pump_current parameter, it must also specify the loop_filter_r and loop_filter_c parameters. Also, when the MegaWizard Plug-In Manager uses the advanced parameters, it ignores the non-advanced bandwidth parameters.

Contact Altera Applications for more information on how the PLL parameters affect bandwidth.

Clock Switchover

The clock switchover feature allows the PLL to switch between two reference input clocks. Designers can use this feature for clock redundancy or for a dual clock domain application such as in a system where the system can switch the redundant clock on if the primary clock stops running for some reason. The design can perform clock switchover automatically, when the clock is no longer toggling, or based on a user control signal.

Table 7. Advanced Loop Filter Parameters

Parameter Values

Resistor values (kΩ) 1, 2, 3, 4, 7, 8, 9, 10

High-frequency capacitance values (pF)

5, 10, 15, 20

Charge pump current settings (µA)

2, 3, 6, 9, 14, 20, 23, 30, 33, 41, 45, 50, 54, 61, 70, 82, 91, 98, 122, 148,160, 205

24 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Description

Stratix device PLLs support a fully configurable clock switch-over capability. Figure 14 shows the block diagram of the switch-over circuit built into the enhanced PLL. The major component of this circuitry is the clock inputs sense block that automatically switches from primary to secondary clock for PLL reference when the primary clock signal is not present. The design can send out the clk0_bad and clk1_bad clock sense block outputs and the clk_loss signal to LEs to implement a custom switch-over circuit.

Figure 14. Clock Switch-Over Circuit Block Diagram

There are at least three possible ways use of the clock switch-over feature.

n Counter

CLKLOSS

LOCK

INCLK0

INCLK1

Gated Lock

CLK1_BAD

CLK0_BAD

EXTSWITCH

PFD

FBCLK

ClockSense

SMCLKSW

Enhanced PLL

Active Clock

Switch-OverState Machine

∆t

MUXOUT

Altera Corporation 25

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Designers can use the switch-over circuitry for switching from a primary to secondary input of the same frequency. For example, in applications that require a redundant clock with the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of Figure 14. In this case, the secondary clock becomes the reference clock for the PLL. This automatic switch only words for the primary to secondary direction.

Designers can use the extswitch input for user- or system-controlled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if extclk0 is 66 MHz and extclk1 is 100 MHz, the designer must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than ±20%. This feature is useful when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. Also, designers should choose the secondary clock frequency such that the VCO operates within the recommended range of 300 to 800 MHz. Designers can set the m and n counters accordingly to keep the VCO operating frequency in the recommended range.

If the PLL loses lock for some reason, designers can set the gated lock to control switchover. The gated lock signal goes low to force the switch-over state machine to switch to the secondary clock. If an external PLL is driving the Stratix device PLL, excessive jitter on the clock input could cause the PLL to lose lock. Since the switch-over circuit still senses clock edges, it might not sense a switch condition. In this case, the designer can control switchover using the gated version of the locked signal based on the loss of the primary clock.

Automatic Switchover

Figure 15 shows an example of a waveform illustrating the switchover feature when using automatic clkloss detection. Here, the INCLK0 signal gets stuck low. After the INCLK1 signal gets stuck at low for approximately two clock cycles, the clock sense circuitry drives the clk0_bad signal high. Also, since the reference clock signal is not toggling, the clk_loss signal goes low indicating a switch condition. Then, the switchover state machine controls the multiplexer through the CLKSW signal to switch to the secondary clock.

26 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 15. Automatic Switchover Upon clkloss Detection

Notes to Figure 15:(1) The number of clock edges before allowing switchover is determined by the counter setting.(2) Switchover is enabled on the falling edge of INCLK1.(3) The rising edge of FBCLK causes the VCO frequency to decrease.(4) The rising edge of REFCLK starts the PLL lock process again, and the VCO frequency will increase.

INCLK0

INCLK1

MUXOUT

REFCLK

FBCLK

CLK0BAD

CLK1BAD

LOCK

ACTIVECLOCK

CLKLOSS

PLL ClockOutput

(1) (2)

(3) (4)

Altera Corporation 27

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AN 200: Using PLLs in Stratix Devices Preliminary Information

The switchover state machine has two counters that count the edges of the primary and the secondary clocks. counter0 counts the number of inclk0 edges and counter1 counts the number of inclk1 edges. The counters get reset to zero when the count values reach 1,1; 1,2; 2,1; or 2,2 for nclock0 and nclock1, respectively. For example, if counter0 counts two edges, its count is set to two and if counter1 counts two edges before the counter0 sees another edge, they are both reset to 0. If for some reason, one of the counters counts to 3, it means the other clock missed an edge. clkbad0 or clkbad1 goes high, and the switch-over circuitry signals a switch condition. See Figure 16.

Figure 16. Clock-Edge Detection for Switchover

Manual Switchover

Figure 17 shows an example of a waveform illustrating the switch-over feature when controlled by extswitch. In this case, both clock sources are functional and INCLK0 is selected as the primary clock. EXTSWITCH goes high, which starts the switch-over sequence. On the falling edge of INCLK0, the reference clock to the n counter, MUXOUT, is gated off to prevent any clock glitching. On the falling edge of INCLK1, the reference clock multiplexer switches from INCLK0 to INCLK1 as the PLL reference. This is also the point the CLKSW signal changes to indicate which clock is selected as primary and which is secondary. The CLKLOSS signal mirrors the EXTSWITCH signal in this mode. Since both clocks are still functional during the manual switch, neither CLK_BAD signal goes high. Since the switch-over circuit is edge-sensitive, the falling edge of the EXTSWITCH signal does not cause the circuit to switch back from INCLK1 to INCLK0. When the EXTSWITCH signal goes high again, the process repeats. EXTSWITCH and automatic switch will only work if the clock being switched to is available.

inclk0

inclk1

clkbad0

Count of three onsingle clock indicatesother missed edge.Reset

28 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 17. Clock Switch-Over Using the EXTSWITCH Control

Figure 18 shows a simulation of using switchover for two different reference frequencies. In this example simulation, the reference clock is either 100 or 66 MHz. The PLL begins with fIN = 100 MHz and is allowed to lock. At 20 µs, the clock is switched to the secondary clock, which is at 66 MHz.

INCLK0

INCLK1

MUXOUT

EXTSWTCH

CLKSW

CLKLOSS

CLK0BAD

CLK1BAD

Altera Corporation 29

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 18. Switchover Simulation Note (1)

Note to Figure 18:(1) This simulation was performed under the following conditions: the n counter is set to 2, the m counter is set to 16,

and the output counter is set to 8. Therefore, the VCO operates at 800 MHz for the 100-MHz input and at 528 MHz for the 66-MHz reference input.

Lock-Signal-Based Switchover

The lock circuitry can initiate the automatic switchover. This is useful for cases where the input clock is still clocking, but its characteristics have changed so that the PLL is not locked to it. The switchover lock input is based on both the gated and ungated lock signals. If the ungated lock is low, the switch-over lock will not enable until the gated lock has reached its terminal count. The design will activate the switch-over enable if the gated lock is high, but the ungated lock goes low. The switch-over timing for this mode is similar to the waveform shown in Figure 17 for EXTSWITCH control, except the lock switch-over enable replaces EXTSWITCH. Figure 19 shows the switch-over enable circuit when controlled by lock and gated lock.

PLL OutputFrequency (MHz)

Time (µs)

0

1

2

3

4

5

6

7

8

9

10

5 10 15 20 25 30 35 400

30 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 19. Switch-Over State Machine

Table 8 summarizes the signals used for clock switchover.

Software Support

All the switchover ports shown in Table 8 are supported in the MegaWizard Plug-In Manager. The MegaWizard Plug-In Manager supports two methods for clock switchover:

Automatic switchover, upon loss of the reference clock An internal user-controlled signal to trigger switchover

If the primary and secondary clock frequencies are different, the Quartus II software will select the proper parameters to keep the VCO within the recommended frequency range.

Lock

Gated lock

Switch-overenable

Table 8. Clock Switchover Ports

Port Description Source Destination

inclk0 Reference clk0 to the PLL I/O pin Clock switch-over circuit

inclk1 Reference clk1 to the PLL I/O pin Clock switch-over circuit

clkbad0 Signal indicating that refclk0 is no longer toggling

Clock switch-over circuit

Logic array

clkbad1 Signal indicating that refclk1 is no longer toggling

Clock switch-over circuit

Logic array

extswitch Switchover signal used to initiate clock switchover

Logic array or I/O pin Clock switch-over circuit

clkloss Signal indicating that the switch-over circuit detected a switch condition

Clock switch-over circuit

Logic array

locked Signal indicating that the PLL has lost lock PLL Clock switch-over circuit

activeclock Signal to indicate which clock (1 = inclk0 or 0 = inclk1) is driving the PLL

PLL Logic array

Altera Corporation 31

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Guidelines

Use the following guidelines to design with clock switchover in PLLs.

The EXTSWTCH signal has a minimum pulse width that is based on the two reference clock periods. The EXTSWTCH pulse width must be greater than or equal to the period of the current reference clock (tfrom_clk) multiplied by two plus the rounded up version of the ratio of the two reference clock periods. As an example, assume nominally tto_clk is equal to tfrom_clk. Then the EXTSWTCH pulse width should be at least three times the period of the clock pulse.tEXTSWTCHmin ≥ tfrom_clk × [2 + intround_up (tto_clk/tfrom_clk)]

Applications that require a clock switch-over feature and a small frequency drift should use a low-bandwidth PLL. The low-bandwidth PLL reacts slower than a high-bandwidth PLL to changes to its reference input clock. When the switchover happens, a low-bandwidth PLL propagates this stopping of the clock to the output slower than a high-bandwidth PLL. However, the trade-off when using a low-bandwidth PLL is that it filters out jitter on the reference clock and increases lock time.

Stratix device PLLs can use both the automatic clock switch-over and the extswitch input simultaneously. Therefore, the switch-over circuitry can automatically switch from the primary to the secondary clock, and once the primary clock stabilizes again, the clkswitch signal can switch back to the primary clock. During switchover, the PLL VCO continues to run and will slow down, generating frequency drift on the PLL outputs. The extswitch signal controls switchover with its rising edge only.

The clock switchover event is glitch-free. After the switch occurs, there is still a finite resynchronization period to lock onto a new clock as the VCO ramps up. The exact amount of time it takes for the PLL to relock is dependent on the PLL configuration. Designers can use the programmable bandwidth feature of the PLL to adjust the relock time.

Figure 20 shows how the VCO frequency gradually decreases when the primary clock is lost and then increases as the VCO locks on to the secondary clock. After the VCO locks on to the secondary clock, there may be some overshoot (an over-frequency condition) in the VCO frequency.

32 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 20. VCO Switchover Operating Frequency

Disable the system during switchover if it is not tolerant to frequency variations during the PLL resynchronization period. There are two ways to disable the system. First, the system may require some time to stop before switchover occurs. The switch-over circuitry includes an optional five-bit counter to delay when the reference clock is switched. The designer can control the time-out setting on this counter (up to 32 cycles of latency) before the clock source switches. The designer can use these cycles for disaster recovery. The clock output frequency will vary slightly during those 32 cycles since the VCO can still drift without an input clock. Programmable bandwidth can control the PLL response to limit drift during this 32-cycle period.

A second option available is the ability to use the PFD enable signal (pfdena) along with user-defined control logic. In this case, the designer can use clk0_bad and clk1_bad status signals to turn off the PFD so the VCO maintains its last frequency. Designers can also use their own state machine to switch over to the secondary clock. Upon re-enabling the PFD, output clock enable signals (clkena) can disable clock outputs during the switchover and resynchronization period. Once the lock indication is stable, the system can re-enable the output clock(s).

∆Fvco

Primary Clock Stops Running

Switchover Occurs

Frequency Overshoot

VCO Tracks Secondary Clock

Altera Corporation 33

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Spread-Spectrum Clocking

Digital clocks are generally square waves with short rise times and a 50% duty cycle. These high-speed digital clocks concentrate a significant amount of energy in a narrow bandwidth at the target frequency and at the higher frequency harmonics. This results in high energy peaks and increased electromagnetic interference (EMI). The radiated noise from the energy peaks travels in free air and, if not minimized, can lead to corrupted data and intermittent system errors, which can jeopardize system reliability.

Background

Traditional methods for limiting EMI include shielding, filtering, and multi-layer printed circuit boards (PCBs). However, these methods significantly increase the overall system cost and sometimes are not enough to meet EMI compliance. Spread-spectrum technology gives designers a simple and effective technique for reducing EMI emissions without additional cost and the trouble of re-designing a board.

Spread-spectrum technology modulates the target frequency over a small range. For example, if a 100-MHz signal has a 0.5% down-spread modulation, then the frequency is swept from 99.5 to 100 MHz. Figure 21 gives a graphical representation of the energy present in a spread-spectrum signal vs. a non-spread-spectrum signal. It is apparent that instead of concentrating the energy at the target frequency, the energy is re-distributed across a wider band of frequencies, which reduces peak energy. Not only is there a reduction in the fundamental peak EMI components, but there is also a reduction in EMI of the higher order harmonics. Since some regulations focus on peak EMI emissions, and not average EMI emissions, spread-spectrum technology is a valuable method of EMI reduction.

34 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 21. Spread-Spectrum Signal Energy vs. Non-Spread-Spectrum Signal Energy

Spread-spectrum technology would benefit a design with high EMI emissions and/or strict EMI requirements. Device-generated EMI is dependent on frequency, output voltage swing amplitude, and slew rate. For example, a design using LVDS already has low EMI emissions because of the low-voltage swing. The differential LVDS signal also allows for EMI rejection within the signal. Therefore, this situation may not require spread-spectrum technology.

Description

Stratix device enhanced PLLs feature spread-spectrum technology to reduce the EMI emitted from the device. The enhanced PLL provides up to a 0.5% down spread (−0.5%) using a triangular, also known as linear, modulation profile. The modulation frequency is programmable and ranges from approximately 150 to 500 kHz. The spread percentage is based on the clock input to the PLL and the m and n settings. Spread-spectrum technology reduces the peak energy by 4 to 6 dB at the target frequency. However, this number is dependent on bandwidth and the m and n counter values and can vary from design to design.

δ = 0.5%

∆ = ~6 dB

Amplitude(dB)

Frequency(MHz)

Spread-Spectrum Signal

Non-Spread-Spectrum Signal

Altera Corporation 35

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Spread percentage, also known as modulation width, is defined as the percentage that the design modulates the target frequency. A negative (−) percentage indicates a down spread, a positive (+) percentage indicates an up spread, and a (±) indicates a center spread. Modulation frequency is the frequency of the spreading signal or how fast the signal sweeps from the minimum to the maximum frequency. Down-spread modulation shifts the target frequency down by half the spread percentage, centering the modulated waveforms on a new target frequency.

The m and n counter values are toggled at the same time between two fixed values. The loop filter then slowly changes the VCO frequency to provide the spreading effect, which results in a triangular modulation. An additional spread-spectrum counter (shown in Figure 22) sets the modulation frequency. Figure 22 shows how spread-spectrum technology is implemented in the Stratix device enhanced PLL.

Figure 22. Spread-Spectrum Circuit Block Diagram

Figure 23 shows a VCO frequency waveform when toggling between different counter values. Since the enhanced PLL switches between two different m and n values, the result is a straight line between two frequencies, which gives a linear modulation. The magnitude of modulation is determined by the ratio of two m/n sets. The percent spread is determined by:

percent spread = (fVCOmax − fVCOmin)/fVCOmax = 1 − [(m2 × n1)/(m1 × n2)]

÷ n

n count1 n count2

PFDUp

Down

SpreadSpectrumCounter

÷ m

m count1 m count2

refclk

36 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

The maximum and minimum VCO frequency is defined as:

fVCOmax = (m1/n1) × fref

fVCOmin = (m2/n2) × fref

Figure 23. VCO Frequency Modulation Waveforms

Software Support

The designer can enter the desired down-spread percentage and modulation frequency in the MegaWizard Plug-In Manager through the Quartus II software. Alternatively, the MegaWizard Plug-In Manager can set the downspread parameter in the altpll megafunction to the desired down-spread percentage. Timing analysis ensures the design operates at the maximum spread frequency and meets all timing requirements. This feature is not supported in version 2.0 of the Quartus II software.

Guidelines

If the design cascades PLLs, the source, or upstream, PLL should have a low bandwidth setting, while the destination, or downstream, PLL should have a high bandwidth setting. The upstream PLL must have a low bandwidth setting because a PLL will not generate jitter higher than its bandwidth. The downstream PLL must have high bandwidth setting to track the jitter. The design must use the spread-spectrum feature in a low-bandwidth PLL, and, therefore, the Quartus II software automatically sets the spread-spectrum PLL’s bandwidth to low.

1 Designs cannot use spread-spectrum PLLs with the programmable bandwidth feature.

Stratix devices can accept a spread-spectrum input with typical modulation frequencies. However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal will look like deterministic jitter at the input of the downstream PLL.

count2 values

count1 values

VCO Frequency

Altera Corporation 37

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Spread spectrum should only have a minor effect on cycle-to-cycle jitter, but period jitter will increase. Cycle-to-cycle jitter is the deviation of a clock’s cycle time from its previous cycle position. Period jitter measures the variation of a clock’s output transition from its ideal position over consecutive edges.

With down-spread modulation, the peak of the modulated waveform is the actual target frequency. Therefore, the system will never exceed the maximum clock speed. To maintain reliable communication, the entire system/subsystem should use the Stratix device as the clock source. Communication could fail if the Stratix logic array is clocked by the spread-spectrum clock, but the data it receives from another device is not.

Since spread spectrum affects the m counter values, all spread-spectrum PLL outputs are affected. Therefore, if only one spread-spectrum signal is needed, the clock signal should use a separate PLL without other outputs from that PLL.

No special considerations are needed when using spread spectrum with the clock switchover feature. This is because the clock switchover feature does not affect the m and n counter values, which are the counter values that are switching when using spread spectrum.

PLL Reconfiguration

PLLs use several divide counters and delay elements to perform frequency synthesis and phase shifts. In Stratix device enhanced PLLs, these counters and delay elements are configurable in real-time. Designers can use these PLL components to adjust output frequency and clock delay in real-time without reloading a Programmer Object File (.pof). This provides considerable flexibility for frequency synthesis.

Description

Enhanced PLLs support real-time PLL reconfiguration. The PLL components that are configurable in real-time include the following:

Pre-scale counter and delay element (n, ∆tn) Feedback counter and delay element (m, ∆tm) Post-scale output counters and delay elements (g, ∆tg, l, ∆tl, e, ∆te)

The designer cannot dynamically adjust the charge pump current, loop filter components, and phase shifts using VCO taps.

38 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Designers can dynamically adjust PLL counters and delay elements by shifting their new settings into a serial shift register chain or scan chain, shown in Figure 24. Serial data is input to the scan chain via the SCANDATA port and the shift registers are clocked by SCANCLK. After the last bit of data is clocked in, the PLL configuration bits are synchronously updated with the data in the scan registers. Although the counter and delay element settings are updated synchronously, they are not all updated at the same time. The maximum input shift clock rate equals 25 MHz. Designers can use SCANACLR to asynchronously clear the registers in the scan chain. The Stratix logic array or I/O pins can drive each of these signals (see Table 9).

Figure 24. PLL Reconfiguration Circuit Block Diagram

Table 9. Real-Time PLL Reconfiguration Ports

PLL Port Name Description Source Destination

scandata Serial input data stream Logic array or I/O pin PLL reconfiguration circuit

scanclk Serial clock input signal Logic array or I/O pin PLL reconfiguration circuit

scanaclr Active high, asynchronous clear signal for serial shift register chain

Logic array or I/O pin PLL reconfiguration circuit

÷n ∆tn

∆tm÷m

÷g ∆tg

÷l ∆tl

÷e ∆te

PFD VCOChargePump

LoopFilter

fREF

scandata

scanclk

scanaclr

Counters and ClockDelay Settings areProgrammable

All Output Counters andClock Delay Settings canbe Programmed Dynamically

Altera Corporation 39

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AN 200: Using PLLs in Stratix Devices Preliminary Information

All PLL counters have 20 configuration bits and all delay elements have 4 configuration bits. The counters are classified into two types.

1. Spread-spectrum counters (m, n): The pre-scale counter, n, and feedback counter, m, implement spread spectrum by switching between two different divide settings. These counters range from 1 to 512. Therefore, the nominal count value and the spread-spectrum count value need 9 configuration bits each, for a total of 18 configuration bits. An additional configuration bit (RBYPASS) bypasses the counter (i.e., divide by 1). This brings the total number of counter configuration bits to 20, including one reserved bit that must be set to 0. When the design does not use spread spectrum, it uses the nominal count value and ignores the spread-spectrum count value.

2. Post-scale counters (g, l, e): The g, l, and e post-scale counters can implement programmable duty cycle. Each counter has a 9-bit high-time setting and a 9-bit low-time setting. The duty cycle is the ratio of output high or low time to the total cycle time, which is the sum of the two. Additionally, these counters have two control bits (RBYPASS and RSELODD) bringing the total number of configuration bits to 20.

When the RBYPASS bit is set to 1, it bypasses the counter, resulting in a ÷1. When the RBYPASS bit is set to 0, the high- and low-time counters are added to compute the division of the VCO output frequency. For example, if the post-scale divide factor is 10, the designer could set the high-and low-count values to 5 and 5, respectively, to achieve a 50-50% duty cycle. On the other hand, a 4 and 6 setting would produce an output clock with 40-60% duty cycle.

The RSELODD bit indicates an odd divide factor for the VCO output frequency along with a 50% duty cycle. For example, if the post-scale divide factor is 3, the designer could set the high- and low-time count values to 2 and 1, respectively, to achieve this division. However, this would also generate a 33-67% duty cycle. If the system requires a 50-50% duty cycle, set the RSELODD control bit to 1. The PLL implements this duty cycle by transiting the output clock from high to low on a falling edge of the VCO output clock.

All configurable delay elements are identical and their settings are shown in Table 10. The delay elements can add delay in steps of 250 ps with a maximum delay of 3 ns. All counters inside the Stratix device enhanced PLL have an associated delay element. For instance, the ∆tm delay element is associated with the feedback counter and can advance all PLL clock outputs, which has the effect of adding negative delay.

40 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

The length of the scan chain is different for different PLLs. Enhanced PLLs 5 and 6 have 12 counters and delay elements and a 289-bit scan chain. The last register in the scan chain holds the transfer enable bit. Set this bit high to load new configuration information. Figure 25 shows the scan chain order of PLL components in these PLLs.

Enhanced PLLs 11 and 12 have only 8 counters and delay elements and a 193-bit scan chain. Figure 26 shows the scan chain order of components in these PLLs. Scan registers for the counter settings are marked n, m, g0, g1, whereas scan registers for the delay elements are marked ∆tm, ∆tn, ∆tg0, ∆tg1.

Table 10. Delay Element Settings

Delay Element Bit Settings Delay (ns)

3 2 1 0

0 0 0 0 0.00

0 0 0 1 0.25

0 0 1 0 0.50

0 0 1 1 0.75

0 1 0 0 1.00

0 1 0 1 1.25

0 1 1 0 1.50

0 1 1 1 1.75

1 0 0 0 2.00

1 0 0 1 2.25

1 0 1 0 2.50

1 0 1 1 2.75

1 1 1 1 3.00

Altera Corporation 41

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 25. Scan Chain Order for Enhanced PLLs 5 & 6

Figure 26. Scan Chain Order for Enhanced PLLs 11 & 12

N

∆tN

M

∆tM

G0

∆tG0

G1

∆tG1

G2

∆tG2

G3

∆tG3

L0

∆tL0

L1

∆tL1

E0

∆tE0

E1

∆tE1

E2

∆tE2

E3

∆tE3

DATA

N

∆tN

M

∆tM

G0

∆tG0

G1

∆tG1

G2

∆tG2

G3

∆tG3

L0

∆tL0

L1

∆tL1

DATA

42 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Software Support

Designers can use the Quartus II software MegaWizard plug-in to specify the PLL input/output frequencies and phase/time shifts. Based on these parameters, the Quartus II software will select internal settings for the PLL. These internal settings are stored in the PLD configuration file and used by the PLL after configuration and power-up. The compiler report file shows the serial chain corresponding to the configuration in the SOF. Designers can then use the MegaWizard plug-in to make some preliminary configurations and replace values in the scan chain.

Designers can also select the counter and delay element settings manually based on information detailed in the hardware implementation section. After determining the individual configuration bit settings for the different counters and delay elements, arrange the bits as shown in Table 11. Table 11 provides a bit map for the scan chain registers. Bit 0 is the last bit shifted into the scan chain. Bit 282 is the first bit shifted in for enhanced PLLs 5 and 6, while bit 192 is the first bit for PLLs 11 and12.

Table 11. PLL Configuration Scan Chain Bit Map (Part 1 of 3) Notes (1), (2), (3)

PLL Scan Chain Bit Map (4) PLL Parameter Size (Bits)

0 1 2 3 4 5 6 7 8 n counter nominal count 9

9 n counter bypass bit 1

10 11 12 13 14 15 16 17 18 n counter spread count 9

19 RESERVED (set to 0) 1

20 21 22 23 n delay element setting 4

24 25 26 27 28 29 30 31 32 m counter nominal count 9

33 m counter bypass bit 1

34 35 36 37 38 39 40 41 42 m counter spread count 9

43 RESERVED (set to 0) 1

44 45 46 47 m delay element setting 4

48 49 50 51 52 53 54 55 56 g0 counter high cycles count 9

57 g0 counter bypass bit 1

58 59 60 61 62 63 64 65 66 g0 counter low cycles count 9

67 g0 counter odd division bit 1

68 69 70 71 g0 delay element setting 4

72 73 74 75 76 77 78 79 80 g1 counter high cycles count 9

81 g1 counter bypass bit 1

82 83 84 85 86 87 88 89 90 g1 counter low cycles count 9

91 g1 counter odd division bit 1

92 93 94 95 g1 delay element setting 4

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AN 200: Using PLLs in Stratix Devices Preliminary Information

96 97 98 99 100 101 102 103 104 g2 counter high cycles count 9

106 107 108 109 110 111 112 113 114 g2 counter low cycles count 9

115 g2 counter odd division bit 1

116 117 118 119 g2 delay element setting 4

120 121 122 123 124 125 126 127 128 g3 counter high cycles count 9

129 g3 counter bypass bit 1

130 131 132 133 134 135 136 137 138 g3 counter low cycles count 9

139 g3 counter odd division bit 1

140 141 142 143 g3 delay element setting 4

144 145 146 147 148 149 150 151 152 l0 counter high cycles count 9

153 l0 counter bypass bit 1

154 155 156 157 158 159 160 161 162 l0 counter low cycles count 9

163 l0 counter odd division bit 1

164 165 166 167 l0 delay element setting 4

168 169 170 171 172 173 174 175 176 l1 counter high cycles count 9

177 l1 counter bypass bit 1

178 179 180 181 182 183 184 185 186 l1 counter low cycles count 9

187 l1 counter odd division bit 1

188 189 190 191 l1 delay element setting 4

192 193 194 195 196 197 198 199 200 e0 counter high cycles count (5) 9

201 e0 counter bypass bit (5) 1

202 203 204 205 206 207 208 209 210 e0 counter low cycles count (5) 9

211 e0 counter odd division bit (5) 1

212 213 214 215 e0 delay element setting (5) 4

216 217 218 219 220 221 222 223 224 e1 counter high cycles count (5) 9

225 e1 counter Bypass bit (5) 1

226 227 228 229 230 231 232 233 234 e1 counter low cycles count (5) 9

235 e1 counter Odd division bit (5) 1

236 237 238 239 e1 delay element setting (5) 4

240 241 242 243 244 245 246 247 248 e2 counter high cycles count (5) 9

249 e2 counter Bypass bit (5) 1

250 251 252 253 254 255 256 257 258 e2 counter low cycles count (5) 9

259 e2 counter Odd division bit (5) 1

260 261 262 263 e2 delay element setting (5) 4

264 265 266 267 268 269 270 271 272 e3 counter high cycles count (5) 9

273 e3 counter bypass bit (5) 1

Table 11. PLL Configuration Scan Chain Bit Map (Part 2 of 3) Notes (1), (2), (3)

PLL Scan Chain Bit Map (4) PLL Parameter Size (Bits)

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Notes to Table 11:(1) The first bit shifted into the scan chain is the transfer enable bit. The designer should set this bit to logic high.(2) For all registers in the chain, the most significant bit (MSB) is shifted in first and least significant bit (LSB) last.(3) For enhanced PLLs 11 and 12, the scan chain ends with the L1 delay element setting and total scan chain length is

193 (including a one-bit transfer enable register bit).(4) The LSB is shown in Table 11 on the left; the MSB is on the right.(5) These values are for enhanced general-purpose PLLs with only eight external outputs (PLLs 5 and 6).(6) Bit 192 for PLLs 11 and 12.

Guidelines

Changing the pre-scale and feedback counter settings (m, n) affects the PLL VCO frequency, which will require the PLL to relock to the reference clock. Changing the delay element settings (∆tm, ∆tn) changes the phase relationship of the output clocks with respect to the reference clock, which also requires the PLL to relock. Although the exact effect depends on how drastic the change is, any change typically requires resynchronization.

Adding delay using the ∆tn delay element delays all PLL clock outputs with respect to the reference clock. This delay element can delay all outputs by up to +3.0 ns. Post-scale delay elements can add an additional +3.0 ns of delay, for a total of +6.0 ns. The maximum time difference between PLL outputs cannot exceed 3.0 ns.

Adding delay using the ∆tm delay element pulls in all the PLL clock outputs with respect to the reference clock, effectively adding a negative delay. This is because the ∆tm delay element is in the feedback path. This delay element can advance the clock by +3.0 ns or delay the clock by –3.0 ns.

274 275 276 277 278 279 280 281 282 e3 counter low cycles count (5) 9

283 e3 counter odd division bit (5) 1

284 285 286 287 e3 delay element setting (5) 4

288 Transfer enable register (5), (6) 1

Scan chain length (5) 289

Table 11. PLL Configuration Scan Chain Bit Map (Part 3 of 3) Notes (1), (2), (3)

PLL Scan Chain Bit Map (4) PLL Parameter Size (Bits)

Altera Corporation 45

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Use the CLKENA signals to disable PLL outputs when changing the loop elements (m, n, ∆tm, ∆tn). This will eliminate the possibility of an over-frequency condition affecting system logic. For instance, a designer could use the following sequence of operations to reconfigure a PLL:

1. Use the CLKENA signals to disable all PLL outputs.

2. Use the SCANDATA port to scan in new counter and delay element settings.

3. Use ARESET to reset the PLL to maintain phase relationships between output clocks.

4. Re-enable PLL outputs after detecting a valid lock.

If a design cannot disable the PLL outputs, make gradual and incremental changes to internal components. For example, if the reference clock input is 100 MHz and the counters n and m are set to 5 and 25 respectively, the VCO will run at 500 MHz. To change the VCO frequency to 600 MHz, set n and m to 5 and 30, respectively. The designer should set the feedback counter (m) to change from 25 to 30 gradually in increments of 1 to reduce the risk of an over-frequency condition (where output frequency is higher than required) and avoid a loss of lock condition.

Although changes to post-scale counters or delay elements will not affect PLL lock or VCO frequency, large changes to delay element settings could lead to glitches on the output clock. Designers should either use the CLKENA signals as discussed before or change the delay element settings in small increments rather than in a single large step. The design may lose the phase relationship between output counters when they are reconfigured without an immediate reset. When the phase relationship between output clocks is important, use the ARESET signal to resynchronize the PLL. This resets all internal PLL counters and reinitiates the locking process. During PLL reconfiguration and/or reset, designers can disable clock outputs from the PLL to avoid any change of state in their system. Then the PLLs’ gated lock signal could reactivate clock outputs after successful PLL reconfiguration.

Pins

Table 12 shows the physical pins and their purpose for the Enhanced PLLs. For inclk port connections to pins see “Clocking” on page 57.

46 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Table 12. Enhanced PLL Pins (Part 1 of 2)

Pin Description

CLK4p/n Single-ended or differential pins that can drive the inclk port for PLL 6.

CLK5p/n Single-ended or differential pins that can drive the inclk port for PLL 6.

CLK6p/n Single-ended or differential pins that can drive the inclk port for PLL 12.

CLK7p/n Single-ended or differential pins that can drive the inclk port for PLL 12.

CLK12p/n Single-ended or differential pins that can drive the inclk port for PLL 11.

CLK13p/n Single-ended or differential pins that can drive the inclk port for PLL 11.

CLK14p/n Single-ended or differential pins that can drive the inclk port for PLL 5.

CLK15p/n Single-ended or differential pins that can drive the inclk port for PLL 5.

PLL5_FBp/n Single-ended or differential pins that can drive the fbin port for PLL 5.

PLL6_FBp/n Single-ended or differential pins that can drive the fbin port for PLL 6.

PLLENABLE Dedicated input pin that drives the pllena port of all or a set of PLLs.

PLL5_OUT[3..0]p/n Single-ended or differential pins driven by extclk[3..0] ports from PLL 5.

PLL6_OUT[3..0]p/n Single-ended or differential pins driven by extclk[3..0] ports from PLL 6.

PLL11_OUT, CLK13n Single-ended output pin driven by clk0 port from PLL 6.

PLL12_OUT, CLK6n Single-ended output pin driven by clk0 port from PLL 6.VCCA_PLL5 Analog power for PLL 5. The designer must connect this pin to 1.5 V, even if the PLL

is not used.VCCG_PLL5 Guard ring power for PLL 5. The designer must connect this pin to 1.5 V, even if the

PLL is not used.GNDA_PLL5 Analog ground for PLL 5. The designer can connect this pin to the GND plane on the

board.GNDG_PLL5 Guard ring ground for PLL 5. The designer can connect this pin to the GND plane on

the board.VCCA_PLL6 Analog power for PLL 6. The designer must connect this pin to 1.5 V, even if the PLL

is not used.VCCG_PLL6 Guard ring power for PLL 6. The designer must connect this pin to 1.5 V, even if the

PLL is not used.GNDA_PLL6 Analog ground for PLL 6. The designer can connect this pin to the GND plane on the

board.GNDG_PLL6 Guard ring ground for PLL 6. The designer can connect this pin to the GND plane on

the board.VCCA_PLL11 Analog power for PLL 11. The designer must connect this pin to 1.5 V, even if the PLL

is not used.VCCG_PLL11 Guard ring power for PLL 11. The designer must connect this pin to 1.5 V, even if the

PLL is not used.GNDA_PLL11 Analog ground for PLL 11. The designer can connect this pin to the GND plane on the

board.

Altera Corporation 47

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Fast PLLs Stratix devices contain up to eight fast PLLs with high-speed differential I/O interface ability, along with general-purpose features. Figure 27 shows a diagram of the fast PLL. This section discusses the general purpose abilities of the Fast PLL. For information on the high-speed differential I/O interface capabilities, see Application Note 202 (Using High-Speed Differential I/O Interfaces in Stratix Devices).

GNDG_PLL11 Guard ring ground for PLL 11. The designer can connect this pin to the GND plane on the board.

VCCA_PLL12 Analog power for PLL 12. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL12 Guard ring power for PLL 12. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL12 Analog ground for PLL 12. The designer can connect this pin to the GND plane on the board.

GNDG_PLL12 Guard ring ground for PLL 12. The designer can connect this pin to the GND plane on the board.

VCC_PLL5_OUTA/B External clock output VCCIO power for all extclk outputs from PLL5.VCC_PLL6_OUTA/B External clock output VCCIO power for all extclk outputs from PLL6.

Table 12. Enhanced PLL Pins (Part 2 of 2)

Pin Description

48 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 27. Stratix Fast PLL Block Diagram

Notes to Figure 27:(1) For high-speed differential I/O mode, the high-speed PLL clock feeds the serializer/deserializer (SERDES). Stratix

devices only support one rate of data transfer per fast PLL in high-speed differential I/O mode.(2) High-speed differential I/O SERDES control signal.

ChargePump VCO ÷l1

8EXTCLK1PFD

÷l0

÷g0

m

LoopFilter

VCO Phase SelectionSelectable at each PLLOutput Port

Post-ScaleCounters

Global orregional clock

Global orregional clock

Global orregional clock

lvds_clk2 (1)

lvds_clk1 (1)

txload_en (2)

rxload_en (2)

Global orregional clock

Altera Corporation 49

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 28 shows all possible ports related to fast PLLs.

Figure 28. Fast PLL Ports & Physical Destinations

Notes to Figure 28:(1) This input pin is shared by all enhanced and fast PLLs.(2) This input pin is either single-ended or differential.

Tables 13 and 14 show the description of all fast PLL ports.

ck[5..0]

locked

pllena

inclk0

areset

pfdena

Fast PLL Signals

(1)

(2)

Physical Pin

Signal Driven by Internal Logic

Signal Driven to Internal Logic

Internal Clock Signal

Table 13. Fast PLL Input Signals

Name Description Source Destination

inclk1 Reference clock input to PLL Pin PFD

pllena Enable pin for enabling or disabling all or a set of PLLs – active high

Pin PLL control signal

areset Signal used to reset the PLL which will re-synchronize all the counter outputsactive high

Logic array PLL control signal

pfdena Enables the up/down outputs from the phase-frequency detectoractive high

Logic array PFD

Table 14. Fast PLL Output Signals

Name Description Source Destination

clk[2..0] PLL outputs driving regional or global clock PLL counter Internal clock

locked Lock output from lock detect circuitactive high PLL lock detect

Logic array

50 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Clock Multiplication & Division

Stratix device enhanced PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply counter, m, per fast PLL with a range of 1 to 16. There are three post-scale counters (g0, l0, and l1) for the regional and global clock output ports. All post-scale counters range from 1 to 16. If the design uses a high-speed serial interface, the designer can set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES.

External Clock Outputs

Each fast PLL supports differential or single-ended outputs for source-synchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. The fast PLL global or regional outputs can drive any I/O pin as an external clock output pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank. Refer to Application Note 201 (Using Selectable I/O Standards in Stratix Devices) for output standard support.

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Table 15 shows the I/O standards supported by fast PLL input pins.

Phase Shifting

Stratix device fast PLLs have advanced clock shift ability to provide programmable phase shift. These parameters are set in the Quartus II software.

Table 15. Fast PLL Port I/O Standards

I/O Standard Input

INCLK PLLENABLE

LVTTL v v

LVCMOS v v

2.5 V v

1.8 V v

1.5 V v

3.3-V PCI

3.3-V PCI-X

LVPECL v

PCML v

LVDS v

HyperTransport technology v

Differential HSTL

Differential SSTL

3.3-V GTL

3.3-V GTL+ v

1.5-V HSTL class I v

1.5-V HSTL class II

SSTL-18 class I v

SSTL-18 class II

SSTL-2 class I v

SSTL-2 class II v

SSTL-3 class I v

SSTL-3 class II v

AGP (1× and 2×)

CTT v

52 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. Designers enter a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. Designers can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. Designers can perform phase shifting in time units with a resolution range of 150 to 400 ps to create a function of frequency input and the multiplication and division factors (i.e., it is a function of the VCO period), with the finest step being equal to an eighth (×0.125) of the VCO period. Each clock output counter can choose a different phase of the VCO period from up to eight taps for individual fine-step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one VCO period. The combination of coarse shift and grain shift allows phase shifting for the entire input clock period.

The equation to determine the precision of phase in degrees is: 45° ÷ post-scale counter value. Therefore, the maximum step size is 45°, and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port.

This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation.

Programmable Duty Cycle

The programmable duty cycle allows the fast PLL to generate clock outputs with a variable duty cycle. This feature is supported on each fast PLL post-scale counter. g0, l0, and l1 all support programmable duty. The designer uses a low- and high-time count setting for the post-scale counters to set the duty cycle. The Quartus II software uses the frequency input and multiply/divide rate desired to select the post-scale counter, which determines the possible choices for each duty cycle. The precision of the duty cycle is determined by the post-scale counter value chosen on an output. The precision is defined by 50% divided by the post-scale counter value. The closest value to 100% is not achievable for a given counter value. For example, if the g0 counter is 10, then steps of 5% are possible for duty cycle choices between 5 to 90%.

If the device uses external feedback, the designer must set the duty cycle for the counter driving off the device to 50%.

Altera Corporation 53

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Control Signals

The lock output indicates a stable clock output signal in phase with the reference clock. Unlike enhanced PLLs, fast PLLs do not have a lock filter counter.

The pllenable pin is a dedicated pin that enables/disables both PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. The designer can choose which PLLs are controlled by the pllenable by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin.

The areset signals are reset/resynchronization inputs for each fast PLL. The Stratix device can drive these input signals from an input pin or from LEs. When driven high, the PLL counters reset, clearing the PLL output and placing the PLL out of lock. The VCO will set back to its nominal setting (~700 MHz). When driven low again, the PLL will resynchronize to its input clock as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency will start at a higher value then desired as it locks. The areset signal for fast PLLs will be supported in a future version of the Quartus II software.

The pfdena signals control the PFD output with a programmable gate. If the designer disables the PFD, the VCO will operate at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system will continue running when the PLL goes out of lock or the input clock disables. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. The pfdena signal for fast PLLs will be supported in a future version of the Quartus II software.

Pins

Table 16 shows the physical pins and their purpose for the Fast PLLs. For inclk port connections to pins see “Clocking” on page 57.

Table 16. Fast PLL Pins (Part 1 of 3)

Pin Description

CLK0p/n Single-ended or differential pins that can drive the inclk port for PLL 1 or 7.

CLK1p/n Single-ended or differential pins that can drive the inclk port for PLL 1.

CLK2p/n Single-ended or differential pins that can drive the inclk port for PLL 2.

54 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

CLK3p/n Single-ended or differential pins that can drive the inclk port for PLL 2 or 8.

CLK8p/n Single-ended or differential pins that can drive the inclk port for PLL 3.

CLK9p/n Single-ended or differential pins that can drive the inclk port for PLL 3 or 9.

CLK10p/n Single-ended or differential pins that can drive the inclk port for PLL 4 or 10.

CLK11p/n Single-ended or differential pins that can drive the inclk port for PLL 4.

FPLL7CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 7.

FPLL8CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 8.

FPLL9CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 9.

FPLL10CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 10.

PLLENABLE Dedicated input pin that drives the pllena port of all or a set of PLLs.

VCCA_PLL1 Analog power for PLL 1. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL1 Guard ring power for PLL 1. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL1 Analog ground for PLL 1. The designer can connect this pin to the GND plane on the board.

GNDG_PLL1 Guard ring ground for PLL 1. The designer can connect this pin to the GND plane on the board.

VCCA_PLL2 Analog power for PLL 2. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL2 Guard ring power for PLL 2. The designer must connect this pin to1.5 V, even if the PLL is not used.

GNDA_PLL2 Analog ground for PLL 2. The designer can connect this pin to the GND plane on the board.

GNDG_PLL2 Guard ring ground for PLL 2. The designer can connect this pin to the GND plane on the board.

VCCA_PLL3 Analog power for PLL 3. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL3 Guard ring power for PLL 3. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL3 Analog ground for PLL 3. The designer can connect this pin to the GND plane on the board.

GNDG_PLL3 Guard ring ground for PLL 3. The designer can connect this pin to the GND plane on the board.

VCCA_PLL4 Analog power for PLL 4. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL4 Guard ring power for PLL 4. The designer must connect this pin to 1.5 V, even if the PLL is not used.

Table 16. Fast PLL Pins (Part 2 of 3)

Pin Description

Altera Corporation 55

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AN 200: Using PLLs in Stratix Devices Preliminary Information

GNDA_PLL4 Analog ground for PLL 4. The designer can connect this pin to the GND plane on the board.

GNDG_PLL4 Guard ring ground for PLL 4. The designer can connect this pin to the GND plane on the board.

VCCA_PLL7 Analog power for PLL 7. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL7 Guard ring power for PLL 7. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL7 Analog ground for PLL 7. The designer can connect this pin to the GND plane on the board.

GNDG_PLL7 Guard ring ground for PLL 7. The designer can connect this pin to the GND plane on the board.

VCCA_PLL8 Analog power for PLL 8. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL8 Guard ring power for PLL 8. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL8 Analog ground for PLL 8. The designer can connect this pin to the GND plane on the board.

GNDG_PLL8 Guard ring ground for PLL 8. The designer can connect this pin to the GND plane on the board.

VCCA_PLL9 Analog power for PLL 9. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL9 Guard ring power for PLL 9. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL9 Analog ground for PLL 9. The designer can connect this pin to the GND plane on the board.

GNDG_PLL9 Guard ring ground for PLL 9. The designer can connect this pin to the GND plane on the board.

VCCA_PLL10 Analog power for PLL 10. The designer must connect this pin to 1.5 V, even if the PLL is not used.

VCCG_PLL10 Guard ring power for PLL 10. The designer must connect this pin to 1.5 V, even if the PLL is not used.

GNDA_PLL10 Analog ground for PLL 10. The designer can connect this pin to the GND plane on the board.

GNDG_PLL10 Guard ring ground for PLL 10. The designer can connect this pin to the GND plane on the board.

Table 16. Fast PLL Pins (Part 3 of 3)

Pin Description

56 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Clocking Stratix devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution.

Global & Hierarchical Clocking

Stratix devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), and 8 dedicated fast regional clock networks. These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains within Stratix devices.

There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figures 29 and 30. Enhanced and fast PLL outputs can also drive the global and regional clock networks.

Global Clock Network

These clocks drive throughout the entire device, feeding all device quadrants. All resources within the device—IOEs, LEs, DSP blocks, and all memory blocks—can use the global clock networks as clock sources. The device can also use these resources can as control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. Internal logic can also drive the global clock networks for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 29 shows the 16 dedicated CLK pins driving global clock networks.

Altera Corporation 57

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 29. Global Clocking

Regional Clock Network

There are four regional clock networks RCLK[3..0] within each quadrant of the Stratix device that are driven by the same dedicated CLK[15..0] input pins or from PLL outputs. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 30.

Global Clock [15..0]

CLK[15..12]

CLK[3..0]

CLK[7..4]

CLK[11..8] Global Clock [15..0]

58 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Figure 30. Regional Clocks

Clock Input Connections

Two CLK pins drive each enhanced PLL. Designers can use either one or both pins for clock switch-over inputs into the PLL. Either pin can be the primary clock source for clock switch-over, which is controlled in the Quartus II software. Enhanced PLLs 5 and 6 also have feedback input pins as shown in Table 17.

Input clocks for fast PLLs 1, 2, 3, and 4 come from CLK pins. A multiplexer chooses one of two possible CLK pins to drive each PLL. This multiplexer is not a clock switch-over multiplexer and is only used for clock input connectivity.

Either a FPLLCLK input pin or a CLK pin can drive the fast PLLs in the corners (7, 8, 9, and 10) when used for general purpose. CLK pins cannot drive these fast PLLs in high-speed differential I/O mode.

RCLK[1..0]

RCLK[3..2]

RCLK[5..4] RCLK[7..6]

RCLK[15..14] RCLK[13..12]

RCLK[9..8]

RCLK[11..10]

CLK[15..12]

CLK[3..0]

CLK[7..4]

CLK[11..8]

Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins or PLLs within that Quadrant

Altera Corporation 59

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Table 17 shows which PLLs are available for each Stratix device. It shows in tabular format which input clock pin drives which PLLs.

Notes to Table 17:(1) This is a fast PLL.(2) This is an enhanced PLL.(3) This clock is available, but its performance is not guaranteed. Contact Altera Applications for more information.

Table 17. Clock Input Sources for Enhanced & Fast PLLs

Clock Input Pins

All Devices EP1S30, EP1S40, EP1S60, EP1S80 & EP1S120 Devices

Only

EP1S40, EP1S60,

EP1S80 & EP1S120

Devices Only

PLL 1 (1)

PLL 2 (1)

PLL 3 (1)

PLL 4 (1)

PLL 5 (2)

PLL 6 (2)

PLL 7 (1)

PLL 8 (1)

PLL 9 (1)

PLL 10 (1)

PLL 11 (2)

PLL 12 (2)

CLK0p/n v v (3)

CLK1p/n v

CLK2p/n v v (3)

CLK3p/n v

CLK4p/n v

CLK5p/n v

CLK6p/n v

CLK7p/n v

CLK8p/n v v (3)

CLK9p/n v

CLK10p/n v v (3)

CLK11p/n v

CLK12p/n v

CLK13p/n v

CLK14p/n v

CLK15p/n v

FPLL7CLK v

FPLL8CLK v

FPLL9CLK v

FPLL10CLK v

Clock Feedback Input Pins

PLL5_FBp/n v

PLL6_FBp/n v

60 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Clock Output Connections

Enhanced PLLs have outputs for two regional clock outputs and four global outputs. There is line sharing between clock pins, global and regional clock networks and all PLL outputs. Check Tables 18 and 19 and Figures 31 and 32 to make sure that the clocking scheme is valid. The Quartus II software automatically maps to regional and global clocks to avoid any restrictions. Enhanced PLLs 5 and 6 drive out to single-ended pins as shown in Table 18. PLLs 11 and 12 drive out to single-ended pins.

Designers can connect each fast PLL 1, 2, 3, or 4 outputs (g0, l0, and l1) to either a global or a regional clock. There is line sharing between clock pins, fpllclk pins, global and regional clock networks and all PLL outputs. Check Figures 31 and 32 to make sure that the clocking is valid. The Quartus II software will automatically map to regional and global clocks to avoid any restrictions.

Table 18 shows the global and regional clocks that each PLL drives outputs to. Table 19 shows the global and regional clock network each of the CLK and FPLLCLK pins drive when bypassing the PLL.

Altera Corporation 61

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Table 18. Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 1 of 2)

Clock Network

All Devices EP1S30, EP1S40, EP1S60, EP1S80 & EP1S120 Devices

Only

EP1S40, EP1S60,

EP1S80 & EP1S120

Devices Only

PLL 1 (1)

PLL 2 (1)

PLL 3 (1)

PLL 4 (1)

PLL 5 (2)

PLL 6 (2)

PLL 7 (1)

PLL 8 (1)

PLL 9 (1)

PLL 10 (1)

PLL 11 (2)

PLL 12 (2)

GCLK0 v v v v

GCLK1 v v v v

GCLK2 v v v v

GCLK3 v v v v

GCLK4 v v

GCLK5 v v

GCLK6 v v

GCLK7 v v

GCLK8 v v v v

GCLK9 v v v v

GCLK10 v v v v

GCLK11 v v v v

GCLK12 v v

GCLK13 v v

GCLK14 v v

GCLK15 v v

RCLK0 v v (3) v

RCLK1 v v (3) v

RCLK2 v (3) v v

RCLK3 v (3) v v

RCLK4 v v

RCLK5 v v

RCLK6 v v

RCLK7 v v

RCLK8 v v (3) v

RCLK9 v v (3) v

RCLK10 v (3) v v

RCLK11 v (3) v v

RCLK12 v v

RCLK13 v v

RCLK14 v v

RCLK15 v v

62 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Notes to Table 18:(1) This is a fast PLL.(2) This is an enhanced PLL.(3) This connection is available, but Altera does not guarantee the performance. Contact Altera Applications for more

information.(4) This pin is a tri-purpose pin; it can be an I/O pin, CLK13n, or used for PLL 11 output.(5) This pin is a tri-purpose pin; it can be an I/O pin, CLK6n, or used for PLL 12 output.

External Clock Output

PLL5_OUT[

3..0]p/n

v

PLL6_OUT[

3..0]p/n

v

PLL11_OUT

(4)v

PLL12_OUT

(5)v

Table 18. Global & Regional Clock Output Line Sharing for Enhanced & Fast PLLs (Part 2 of 2)

Clock Network

All Devices EP1S30, EP1S40, EP1S60, EP1S80 & EP1S120 Devices

Only

EP1S40, EP1S60,

EP1S80 & EP1S120

Devices Only

PLL 1 (1)

PLL 2 (1)

PLL 3 (1)

PLL 4 (1)

PLL 5 (2)

PLL 6 (2)

PLL 7 (1)

PLL 8 (1)

PLL 9 (1)

PLL 10 (1)

PLL 11 (2)

PLL 12 (2)

Altera Corporation 63

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Note to Table 19:(1) The FPLLCLK pin is only available in EP1S120, EP1S80, EP1S60, EP1S40, and EP1S30 devices.

Table 19. CLK & FPLLCLK Input Pin Connections to Global & Regional Clock Networks

Clock Network CLK Pins FPLLCLK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 8 9 10

GCLK0 v v v

GCLK1 v v v

GCLK2 v v v

GCLK3 v v v

GCLK4 v

GCLK5 v

GCLK6 v

GCLK7 v

GCLK8 v v v

GCLK9 v v v

GCLK10 v v v

GCLK11 v v v

GCLK12 v

GCLK13 v

GCLK14 v

GCLK15 v

RCLK0 v v

RCLK1 v v

RCLK2 v v

RCLK3 v v

RCLK4 v

RCLK5 v

RCLK6 v

RCLK7 v

RCLK8 v v

RCLK9 v v

RCLK10 v v

RCLK11 v v

RCLK12 v

RCLK13 v

RCLK14 v

RCLK15 v

64 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

The fast PLLs also drive high-speed SERDES clocks for differential I/O interfacing. For information on these FPLLCLK pins, see the Application Note 202 (Using High-Speed Differential I/O Interfaces in Stratix Devices).

Figures 31 and 32 show the global and regional clock input and output connections from the enhanced and fast PLLs, respectively. Figures 31 and 32 show graphically the same information as Tables 18 and 19 but with the added detail of where each specific PLL output port drives to.

Figure 31. Global & Regional Clock Connections from Side Clock Pins & Fast PLL Outputs

2

CLK0CLK1

CLK2CLK3

G0

FPLL7CLK

G1G2

G3RCLK0

RCLK1

RCLK2

RCLK3

G11G10

G9G8

RCLK11RCLK10

RCLK9

RCLK8

GlobalClocks

RegionalClocks

PLL 7

l0

l1

g0

PLL 1

PLL 2

FPLL8CLK

PLL 8

2

CLK10

CLK11

CLK8

CLK9

FPLL10CLK

PLL 10

PLL 4

PLL 3

FPLL9CLK

PLL 9

RegionalClocks

l0

l1

g0

l0

l1

g0

l0

l1

g0

l0

l1

g0

l0

l1

g0

l0

l1

g0

l0

l1

g0

Altera Corporation 65

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Figure 32. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs

G12G13G14G15

RCLK12RCLK13

RCLK14RCLK15

G7

G6G5G4

RCLK7

RCLK6RCLK5RCLK4

PLL 12

L0 L1 G0 G1 G2 G3

CLK7CLK6

CLK5CLK4

PLL 6

G0 G1 G2 G3 L0 L1

PLL 11

L0 L1 G0 G1 G2 G3

CLK13CLK12

CLK14

CLK15

PLL 5

G0 G1 G2 G3 L0 L1

E[0..3]

PLL12_OUT

PLL6_OUT[3..0]

PLL11_OUT

PLL5_OUT[3..0]

PLL5_FB

PLL6_FB

GlobalClocks

RegionalClocks

RegionalClocks

66 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Specifications Table 20 describes the Stratix device enhanced PLL specifications.

Notes to Table 20:(1) Actual PLL performance depends on the settings made.(2) tFCOMP can also equal 50% of the input clock period multiplied by n.(3) Actual jitter performance may vary based on the system configuration.(4) Lock time is a function of PLL configuration and may be significantly faster.(5) Exact, user-controllable value depends on the PLL settings.

Table 20. Enhanced PLL Specifications

Symbol Parameter Min Typ Max Unit

fIN Input frequency (1) 3 462 MHz

fIN DUTY Input clock duty cycle 40 60 %

fEIN DUTY External feedback clock input duty cycle 40 60 %

tIN JITTER Input clock cycle-to-cycle jitter ±150 ps

tEIN JITTER External feedback clock cycle-to-cycle jitter

±150 ps

tFCOMP External feedback clock compensation time (2)

6 ns

fOUT PLL output frequency 0.6 462 MHz

tOUT DUTY Duty cycle for external clock output (when set to 50%)

45 55 %

tJITTER PLL external clock cycle-to-cycle output jitter (3)

±100 ps

tDLOCK Time required to lock dynamically (after switchover or counter value change)

(4) 100 µs

tLOCK Time required to lock from end of device configuration

10 1,000 µs

fVCO PLL internal VCO operating range 300 800 MHz

tLSKEW Clock skew between two external clock outputs driven by the same counter

±50 ps

tSKEW Clock skew between two external clock outputs driven by the different counters with the same settings

±75 ps

fSS Spread spectrum modulation frequency 150 500 kHz

% spread Percentage spread for spread spectrum frequency (5)

0.5 %

Altera Corporation 67

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AN 200: Using PLLs in Stratix Devices Preliminary Information

Table 21 describes the Stratix device fast PLL specifications.

Notes to Table 21:(1) PLLs 7, 8, 9, and 10 support up to 462-MHz input clock frequency. PLLs 1, 2, 3, and

4 support up to 644.5-MHz input clock frequency on the CLK0, CLK2, CLK9, and CLK11 pins only.

(2) This parameter is for high-speed differential I/O mode only.(3) These counters have a maximum of 32 if programmed for 50/50 duty cycle.

Otherwise, they have a maximum of 16. High-speed differential I/O mode supports 1, 2, 4, 8, or 10.

Conclusion Stratix devices’ enhanced PLLs provide designers with complete control of their clocks and system timing. Stratix PLLs are capable of offering flexible system level clock management that was previously only available in discrete PLL devices. Stratix embedded PLLs meet and exceed the features offered by these high-end discrete devices, reducing the need for other timing devices in the system.

Table 21. Fast PLL Specifications

Symbol Parameter Min Max Unit

fIN (1) CLKIN frequency (for m = 9, 10) 33 84 MHz

CLKIN frequency (for m = 7, 8) 43 105 MHz

CLKIN frequency (for m = 4, 5, 6) 75 140 MHz

CLKIN frequency (for m = 2) 150 420 MHz

CLKIN frequency (for m = 1) 300 644.5 Mhz

tINDUTY CLKIN duty cycle 40 60 %

tINJITTER Cycle-to-cycle jitter for CLKIN pin ±100 ps

tDUTY Duty cycle for DFFIO 1× CLKOUT pin

40 60 %

tJITTER Cycle-to-cycle jitter for DIFFIO clock out (2)

±100 ps

Cycle-to-cycle jitter for internal global or regional clock

±100 ps

tLOCK Time required for PLL to acquire lock

10 100 µs

fVCO VCO operating frequency 300 840 MHz

m (3) Multiplication factors for m counter

1 32 Integer

l0, l1, g0 (3) Multiplication factors for l0, l1, and g0 counter

1 32 Integer

68 Altera Corporation

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Preliminary Information AN 200: Using PLLs in Stratix Devices

Altera Corporation 69

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AN 200: Using PLLs in Stratix Devices Preliminary Information

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