Design of CMOS

8/9/2019 Design of CMOS

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Design of CMOS circuitsD. Radhakrishnan

I nd ex in g t m : i rc ui t th eo ry and design, Digital circuits, CM OS circuits

Abstract: The paper presents a formal approachto the design of optimal CMOS networks bymeans of pass logic design techniques. Twoapproaches are given: one for CMOS pass net-works and the other for CMOS gate networks.First, the paper gives an overview of pass net-works, and then presents methods for the designof optimal CMOS pass networks. Differentapproaches are then presented for the design ofCMOS gate networks. The designer is thus pro-vided with a number of choices. The design ofCMO S complementary logic, pseudo-nMOS logic,dynamic logic and domino CMOS uses the min-terms and maxterms separately to form thenetwork function, whereas cascode voltage switchlogic (CVSL) uses them together. Finally, it isshown that optimal CVSL networks may notalways be the best choice in terms of switchingspeed.

1 IntroductionClassical logic design is based on a set of basic logicgates: AND, OR, NAND, NOR, NOT etc. and theirinterconnection to obtain the desired switching function.These design techniques, when applied to MOS designsprove to be very inefficient. With regard to this, manydifferent types of CMOS designs evolved. Newapproaches to the design of combinational circuits usingMOS complex gates are discussed in Reference 1. Designtypes can be characterised into two major classes:CMOS pass networks and CMOS gate networks. CMOSgate networks pass either V,, or V,, to the output,depending o n the s tate of input signals. CMOS pass net-works, on the other hand, can, in addition, pass a vari-able to the output.CMOS gate networks include CMOS complementarylogic, pseudo-nMOS logic, dynamic CMOS, dominoCMO S and cascode voltage switch logic (CVSL). CMOScomplementary logic is intrinsically slow and area ineffi-cient. Pseudo-nMOS logic uses less area, but consumesstatic power. Dynamic CMOS has low capacitance andhigh current capability, but at the cost of circuit stabilityand operational complexity. Domino CMOS, on theother hand, combines the advantages of dynamic CMOSwith the stability and simplicity of static circuits [l , 21.Limitations of this circuit technique are that all of thegates are noninverting and that each gate must be buf-fered. The CVSL family proposed by Heller et al. [3] hasPaper 75156 (ElO), first received 13th February 1989 and in revisedform 14th March 1989The author is with the NETECH Corporation, 60 Bethpage Drive,Hicksville, NY 11801, US AI E E P R O C E E D I N G S - G , Vol. 138, No . I , F E B R U A R Y 1991

been found to offer a performance advantage of up tofour times compared to CMOS/nMOS primitive NAND/NOR logic families.The design of CMOS gate networks is treated differ-ently by many authors. In many cases, they use intuitionand cleverness to come up with optimal designs. Thispaper instead presents a formal approach to the design ofoptimal CMOS gate networks tha t uses pass logic designprinciples [4, 51. In fact, these networks belong to aspecial class of pass networks, where the pass variable isrestricted to the set (0, ).2 Pass networksA pass network is an interconnection of a number of passtransistors to achieve a particular switching function. Adetailed analysis and design procedure for pass networksis given in References 4 and 5. An overview of pass net-works is given here to provide enough background forthe reader to follow the rest of the material.A pass transistor is an nMOS (pMOS) transistor withthe signal input fed to the drain (source) and the signaloutpu t taken from source (drain). The propagation of thesignal through the transistor is controlled by a signalapplied to its gate. In the case of an nMOS transistor, alogic 1 at the gate passes the input from source to drainand a logic 0 opens the source to drain circuit. A PMOStransistor exhibits similar behaviour, except for a changein the control signal logic level. If signals X and Y areconnected to the gate and drain of an nMOS transistor,respectively, then this is represented as X ( Y ) and read as'X passing Y ' . When both an nMOS and a PMOS tran-sistor are used to pass the signal Y , the circuit is referredto as a CMOS transmission gate. The logic symbols forthe above three types of pass gate are shown in Fig. 1.v+ ""I

a bX

CFig. 1(I nMOS transistor for X(Y)b PMOS transistor for X ( Y )c CMOS transmission gate for X(YJ

Logic representations for M O S transistors

A series connection of a number of nMOS (pMOS)transistors passes the input to the output when allcontrol signals are high (low). For an nMOS chain, this isrepresented by the expression X , X , . . .X, (V) , where X , ,83

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X , , . . ,X, re the control variables applied to the gatesof the transistors and V is the pass variable.A product term P = X I X , . . .X,, assing an inputsignal V, is defined as a pass implicant and is denoted byP( V). A pass function is formed by the sum of a numberof pass implicants. In a minimal pass function, all passimplicants belong to the set of pass prime implicants. Apass prime implicant is a pass implicant that cannotsubsume any other pass implicant with a smaller numberof literals in it that implies the same function.The major difference in the design of a pass network,as compared to a gate network, is that both Os and 1s ofthe function must be included. The pass network designprocedures given in Reference 4, which make use of aK-map and modified Quine-McCluskey algorithmicapproach, first select all essential pass prime implicantsfrom the function and then a minimal set of pass primeimplicants to cover the whole function.The K-map minimisation procedure is based on thefollowing:(a) Each and every entry in the map must be coveredat least once.(b) Pass implicants are identified in accordance withthe following rules:(i) Each implicant PAC) consists of 2' adjacent cellsin the K-map and the product term P i is formedin an identical manner to traditional implicants.in the implicant must be

equal to one of the elements from the set {O, 1,X i , Xi} throughout the implicant.A pass function obtained from a K-map may be factor-ised to reduce the transisto r count in the implementation.The following example illustrates the design of an nMOSpass function by the use of a K-map.Example I: The K-map for a four-variable function isshown in Fig. 2.The nMOS pass function is given by

(ii) The pass variable

f = AD(1) + CD(A)+ D ( B )+ A'C' ( B)

Fig. 2 Four-ouriable K -ma p

Factorisation of the above yieldsf = (A(1) + C ( A ) )+ D ( B )+ A ' C ' ( B )

Its implementation as an nMOS pass network is shownin Fig. 3.The nMOS pass function obtained from the aboveprocedure may not always be minimal in its transistorcount when implemented as a series-parallel network.This happens because in the K-map cells are shared bymore than one pass prime implicant. To overcome this, amodified pass network s tructure is defined, called abinary tree structured pass network (BTS). A BTS pass84

network is a special type of pass network where thenumber of branches from each node is limited to two [6].The control variables for the two branches are alwayscomplements of each other. Hence, in the design of a BTSpass network the K-map is always divided into two equalhalves at each step of the minimisation process. The

Fig. 3f = (A(1) + C( A) )+ d(S)+ 6C(B)nMOS ass network fo r Fig. 2

nMOS BTS pass function and its pass network for theK-map in Fig. 2are given in Fig. 4.BTS pass networks, if designed properly, provideoptimal realisations in most cases because of their inher-ent factorising nature. The only nonoptimal networksfound so far correspond to XOR functions. The following;I1 fFig. 4 nMOS BT S puss ne twork for the K -map in Fig. 2f = ca + RO)) A(1) )+ LxB)definition is useful for the minimisation of BTS pass func-tions.Definition I: A complementary sum (CS) is defined asSi= PAX,) + PAX,), where X , and X , are either passvariables or are complementary sums themselves.From the above definition, a BTS pass function is aspecial case of a complementary sum Si , where Si denotesthe switching functionfC71.For X O R functions, it is seen that factorisation of thefunction by taking the largest complementary sum Sigives minimum literals in its expression. These functions,when implemented, use the minimum number of tran-sistors. BTS pass networks are also claimed to exhibitgood fault detection properties [8]. However, the delaysin BTS networks may be worse compared to a non-BTSpass network.Two problems that we face in the implementation ofan nMOS pass function are:(a) The delay of the network depends on the numberof transistors in the series chain. The behaviour of thischain is similar to that of an electrical transmission lineand, hence, the delay increases as a quadratic power ofthe number of transistors in the chain. For short chainsof pass transistors this poses no problem.

(b) An nMOS transistor passes a good 0, but a poor 1,thus causing the deteriora tion of the logic level of a 1input through the chain. On the other hand, a PMOStransistor passes a good 1, but a p oor 0.I E E P R O C E E D I N G S - G ,vol. 38 , N ~ ., F E B R U A R Y I991



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The first problem can be overcome if we break longerchains of pass transistors into smaller ones by interposingbuffer stages. The second has two solutions:(i)Use CMO S pass networks.(ii) Design an nMOS pass network for the complemen-tary pass functionf and then invert it to getf by meansof a CMOS inverter. The inverter threshold may beadjusted to take into account the worst case logic levelson f. In addition to restoring the logic levels on theoutput, this solution gives some drive capability to theoutput signal.3 CMOS networksCMO S networks can be classified into two types, CMOSpass networks and CMOS gate networks. C MOS passnetworks behave similarly to nMOS pass networks. Theyuse fewer transistors compared to CMOS gate networksand can be used to advantage in the design of complexCMO S networks.3.1 NotationThe following notation is used in the remainder of thispaper to represent the different switching functions:f: represents the switching function of a network.

f ( 1 ) : partial pass function obtained by combining thef ( 0 ) :partial pass function obtained by combining thef (P): partial pass function for a PMOS pass network.f(N):artial pass function for an nMOS pass network.f: Dual of functionf:

The following relationship is valid for switching func-tions:

1s of the function.Os of the function.

f = f ( l ) +f@)3.2 CMOS pass networksCMOS pass networks use both nMOS and PMOS tran-sistors in their implementation. An nMOS pass networkcan be easily converted to a CMOS pass network by thefollowing two steps:(a) Replace all nMOS transistors with PMOS tran-sistors if the pass variable is a 1 and with transmissiongates if the pass variable is not constant (i.e. variable).(b) Complement all variables applied to the gates ofPMOS transistors.

The modified pass network implementation for thenMOS pass network in Fig. 3, where a CMOS passnetwork has been formed by means of the above steps, isgiven in Fig. 5. A CMOS pass network designed in thismanner may not always be optimal in its transistor count[SI. A minimal transistor design for a CM OS passnetwork must minimise the nMOS and PMOS transistorsseparately. A primary objective in the design of thenMOS network in a CMO S pass network is to pass all Osof the switching function, but it may also be used to passsome of the 1s if the transistor count can thereby bereduced. The same applies to PMOS networks also, withthe logic values interchanged.The design of a minimal transistor CMOS passnetwork is illus trated by the following example.Example 2: Consider the K-map in Fig. 2. The nMOSpass network to cover the Os of the function is given by:

The first pass prime implicant D(B) covers the 0 cells4, 6, 12 and 14. To reduce the transistor count, this passf ( N ) = D(B)+ C D ( A )+ AB(0).IEE PRO CEED IN G S -G , Vol.1 3 8 , N o . I , FEBRU ARY 1 9 9 1

implicant is augmented with the 1 cells 0, 2, 8 and 10.The same is true of other pass implicants inf(N). Thetwo pass prime implicants D(B) and C D ( A ) together-A D

I

E n I

Fig. 5 C M O S pass networkfrom Fig. 3

cover all the 0 cells except cell 5. This 0 cell can becovered in three different ways. They are AB(O), AC(B)or BD(A). If B D (A ) is chosen instead of AB(O), thenf ( N ) = D(B)+ D( C( A)+ B(A)) . This complementationneeds 4 nMOS transistors. Similarly, the PMOS network,to cover the 1s of the function, is given byf(P) D(B)+ AD(1) + BC(1).A second choice is possible where BC(1) is replacedwith AC(B).In both cases, the PMOS transistor count isfive. The complete CMOS pass network is shown in Fig.6.

--f

B1Fig. 6 Optimal CMOS pass network for Fig. 3

3.3 CMOS gate networksCMOS gate networks consist of two separate networks,one to pull up the output to logic 1 and the other to pulldown the output to logic 0 as shown in Fig. 7 [9].Thepull up network is connected between the output nodeand VDo,and is purely a PMOS network @-net), so as topass good 1s to the output. The pull down network, onthe other hand, is connected between the output nodeand V,,, and is purely an nMOS network (n-net) so as topass good Os to the output. By the nature of the intercon-nections in the two networks, it is guaranteed that onlyone of the networks (either p-net or n-net) will be activat-ed by the inputs at any instant of time. Thus, any closedpaths between the two supply rails are eliminated.The design of these structures simplifies the design ofthe p-net and n-net. Since these two structures basicallypass a 1 and a 0, respectively, to the output, they belong

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to the special class of pass networks where the pass vari-ables belong to the set {0, I} .Some additional notation is introduced here to sim-plify the presentation in the remainder of this paper:7-DD

4

r-7-netf

n - n e tr-lI554

Fig. 7 CMOS gate networkfp: Boolean expression for the p-net. This is obtainedfrom f (1 ) by dropping the pass variable 1 and com-plementing all literals.f N : Boolean expression for the n-net. This is same asf(0) with its pass variable 0 removed.

From the above,f= yN.Five different realisations of CMO S complex gates arepresented below. All of these realisations are derived bymeans of the pass network techniques mentioned inSection 2.

3.3.1 CMOS complementary logicThis structure consists of two complete networks, i.e. ap-net and an n-net. Each of these networks can beobtained from the K-map. For the K-map in Fig. 8 , f ( O )andf(1) are given by:f ( 1 ) = A'C(1) + BC'(1)+ AB'C(1)

= C(A'(1) + B(1))+ ABC(1)= C(A'(0)+ B(0))+ AB'C(0)f ( 0 )= A'C(0) + BC(0)+ AB'C'(0)

\ A E

Fig. 8 Three-variable K- m opFrom f (1 ) and f ( O ) , four different realisations are pos-sible for CMO S complementary gates:(i) Design the n-net and p-net separately, fromf(0) andf ( l ) , respectively,(ii) design the n-net fromf(0) and form its dua l for thep-net,(iii) design the p-net fromf(1) and form its dual for then-net.

(iv) Design the n-net and p-net separately, from f(1)andf(O), respectively.The CMOS complementary gate implementation produc-ed by (i) above, for the K-map in Fig. 8, is given in Fig. 9.86



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will be incurred because of the finite pull down time.Thus, the precharged node can discharge the output nodeof the following gate before the first gate is correctlyevaluated.The n-net design is exactly the same as in the pseudo-nMOS gate. Thus, the two possible implementations of adynamic CMOS gate for the K-map in Fig. 8 are asshown in Fig. 10.

TDD

0 --$ vss

c - l

-$ vssFig. 10 Dynamic CM OS implementations of the K-map in Fig . 8

3.3.4CMOS domino logicThis is a modification to the clocked CMOS logic thatallows a single clock to precharge and evaluate a cas-caded set of dynamic logic blocks. A static CMOS bufferis included in each logic gate, as shown in Fig. 11.Owing

dss d -

In a cascaded set of logic blocks, each stage evaluatesand causes the next stage to evaluate. Any number oflogic stages may be cascaded, provided the sequence canevaluate within the evaluate clock phase. A single clockcan be used to precharge and evaluate all logic gateswithin a block. The limitations of this structure includethe charge redistribution problem and the buffering ofeach gate. Furthermore, only noninverting structures arepossible. The two possible implementations for this gate,corresponding to the K-map in Fig. 8, are shown in Fig.11.3.3.5Cascode voltage switch logic (CVSL)CVSL gates are formed by cascoding differential pairs ofMOS transistors into powerful combinational logic treenetworks to provide both true and false outputs. This isachieved at the expense of the extra routing, active areaand complexity associated with double rail logic.However, the ability to generate any logic function isadvantageous where automated logic synthesis isrequired.Two different forms of static CVSL gates exist: one isthe fully differential type and the other is a simplifiedversion of this. In fully differential CVSL, two comple-mentary nMOS networks are connected to a pair ofcrosscoupled PMOS pullup transistors, as shown in Fig.12.When the input switches, the nodesfandf switch inopposite directions, each node being either pulled high orlow. Positive feedback, applied to the PMOSpull up tran-sistors, causes the gate to switch. The n-nets may befurther minimised from the fully differential form bymeans of logic minimisation algorithms to form the sim-plified static gate.

Fig. 11 CM OS domino implementations of the K-map in Fig. 8to the presence of the inverter at the output, the n-net isdesigned according to the function. During the prechargephase (4 = 0), the output node of the dynamic gate isprecharged high and, hence, the output of the buffer iskept low. As subsequent logic stages are fed from thisbuffer, transistors in subsequent logic blocks will beturned off during the precharge phase. When the gate isevaluated, the output will conditionally discharge,causing the output of the buffer, conditionally, to go high.Thus, each gate in sequence can make, at most, one tran -sition 1 -+ 0. Hence, the buffer can only make a transitionfrom 0+ 1.IEE PRO CEED IN G S -G , Vol. 138, N o . I , FEBRU ARY 1 9 9 1

A K-map minimisation procedure and a tabularapproach to the design of the n-nets is given in Reference10. This procedure is based on the generation of four dif-ferent lists: 10, 01, 1 and 0. For a function of n variablesXI, ,, . ,X, he transistor trees formed by the use of10 and 01 lists are always connected to the ou tpu tsfa ndf by transistors controlled by X, nd X,. In addition,the contro l variables X i n each of the tree branches arearranged from top to bottom in ascending order, withmagnitudes of i. This procedure does not always guar-antee minimal transistor implementations, as shown laterin this paper. Furthermore, the four lists, 1401, 1 and 0,

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. .. . .



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the CVSL gate in example 3 is ten. This justifies ourearlier statement regarding the nonoptimality of Chusprocedure [IO] for the design of CVSL gates.One way to find a minimal transistor implementationis by trying all possible choices for the n-nets, N o and NIin Fig. 12, with maximum sharing of transistors betweenthem. This can be done in the following manner. First,assume that the two n-nets are labelled NI and N o , asshown in Fig. 12. Their cor responding logic expressionsare denoted by f N 1 and f N o , respectively. f N o can beobtained either from f (O ) , by simply dropping the passvariables, or from f ( l ) , by dropping the pass variablesand complementing the expression. In a similar manner,f N ,can be obtained either fromf(1) or fromf(0).fN, andf N ocan then be factorised in different ways, which givesmany choices for the implementation of the CVSL gate.This is illustrated by the following example.Example 4 : Consider again the K-map shown in Fig.14a. From this K-map,

f ( 1 ) = BD(1)+ BD(1)+ C D ( 1 )+ AB(1)Other choices exist for CD( 1)and AB(1).They are:

f N , = B(A + D) + D (B + C )f N , = BD + D ( A + B + C )f N , =B(A + C + D) BD

orf N ,= B(C + D ) + D (A + B )

Similarly, f (O ) , from the K-map, is given byf ( 0 ) =BD(0)+ ABCD(0) and, hence, f N o= B D +ABCD.If we take all possible combinations, this gives a totalof 21 different implementations for the CVSL gate. Oneof the minimal transistor implementations is found byusing f N ,= B(A + C + D)+ BD and f N o= B D +ABCD. This is shown in Fig. 1 5 . Transistors B and BTDD

(b) Connect the output node to V,.(c) Connect each input node of the pass network to

(i) If the pass variable is 0, then connect the inputnode to$(ii) If the pass variable is 1 , then connect the inputnode tof.(iii) If the pass variable is X, then connect the inputnode tof through a transistor controlled by Xand tof through a transistor controlled by X.(iv) If the pass variable is X , hen connect the inputnode to f through a transistor controlled byX and to f through a transistor controlled byX.

The following example illustrates the design of a staticCVSL gate by means of procedure 2.

eith erfo rf according to the following criteria:

Example 5 : Consider again the four variable K-mapshown in Fig. 14a. This is redrawn in Fig. 16a. The BTSpass function for this K-map is given byf = D(B)+D(A(1)+ A(B(1)+ B(C))).The BTS pass network is shown in Fig. 16b. Thisnetwork can easily be converted to a CVSL gate by pro-cedure 2 and the result is shown in Fig. 16c. As can beseen in Fig. 16c, it uses only ten nMOS transistors. It hasbeen verified by an exhaustive search that ten is theminimum transistor count for this gate (example 4).BTS pass networks are shown to use the minimumnumber of transistors to realise a switching function [ S I .Hence, CVSL gates implemented by means of BTS passnetworks also use the minimum number of transistors.The only exception to this is the XOR function. ForXOR functions, however, as mentioned earlier, factor-isation by taking the largest complementary sum Si ivesminimum literals in the expression, thereby minimisingthe transis tor count. These functions can then be used toimplement minimum transistor CVSL gates. However, asearch for an example that uses fewer transistors than theabove design has been unsuccessful. Hence, the followingconjecture.

1 Conjecture I : CVSL design by means of a modifiedversion of a BTS pass network that uses variable sharinggives a minimal transistor realisation.The following example illustrates the design of anXOR function as a CVSL gate with a minimum numberof transistors.

1 I I

Fig. 15/*, = ED + B(A + C + D ) , f * , = E D + BDCAOptimal C V S L gate for the K-map in Fig. 14aare shared between the two n-nets. Thus, the total nMOStransistor count is ten.The method used in example 4 for optimal design of aCVSL gate is very laborious and time-consuming. Hence,a modified procedure for the design of an optimal CVSLgate is given below. This procedure is based on the opti-mality property of BTS pass networks.Procedure 2 :( a )Form the BTS pass network for the function.IEE PRO CEED IN G S -G , Vol. 138,N o . I, F E B R U A R Y 1991

Example 6 : Consider the XOR function f ( A , B , C,D)= A 8 B 0 C 0 D . A minimal trans istor implementa-tion of this function uses 14nMOS transistors and isgiven in Reference 9. An nMOS BTS pass function forfcan be written asf = (B(C(D) C(D))+ B( C ( D)+ C(D)) )+ A(B(C(D)+ C ( D ) )+ B(C(D)+ C ( D ) ) )

If we use the two complementary sums C ( D )+ C ( D )andC(D)+ C ( D ) nJ this can be factorised and rewritten asf = AB + A B }(C (D )+ C ( D ) )

+ { A B+ A B }(C (D )+ C ( D ) )This function gives the same minimal transistor imple-mentation as in Reference 9.

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Even though CVSL gates designed by means of BTSpass networks give minimum transistor implementations,they may not always be the best choice in terms ofswitching speed. In many implementations, the stack

CD00E d l

I P P IFig. 16n Four-variableK-map of Fig. 140b BTS pass networke CVSL network

Optimal CV SL gate realisation from BT S pass network

height increases because of the BTS nature, whichincreases the switching delay. This can be seen by com-paring the CVSL gates in Figs. 14b and 16c. For min-terms m 5 nd m, off, the switching network in Fig. 146consists of the series circuit controlled by the two tran-sistors B and D connectingf to Vss . On the other hand,in Fig. 16b, the switching network consists of the seriescircuit controlled by the three transistors D, A and B.This introduces an extra delay in switching, which slowsthe gate. Hence, in high performance designs, there is atradeoff between speed and transistor count.

4 ConclusionsDifferent methods for the design of complex CMOS net-works are given in this paper. All of these designs areshown to follow directly from the design of pass net-works. These methods always provide a means for thedesign of optimal networks. It is also shown that CVSLdesigns based on BTS pass networks always use theminimum number of transistors.5 AcknowledgmentThis work was supported in part by the Idaho StateBoard of Education, USA under grant 696-XOO8.I alsothank Dr. Gary K. Maki for many valuable discussionsand for his unfailing support.6 References1 KRA MBE CK, R.H., LEE, C.M., and LAW, H.S.: High speedcompact circuits with CM OS , IEEE J., 1982,SC-17, pp. 6146192 MURPHY, B.T., EDWARDS, R., THOMAS, L.C., and MOLIN-ELLI, J.J.: A CMOS 32-bit single chip microprocessor. Pro-ceedings of IEEE International Solid-state Circuits Conference,Feb. 19813 HEL LER, L.G., GRIF FIN , W.R., DAVIS, J.W., and THO MA ,N.G.: Cascode voltage switch logic: a differential CMO S logicfamily. Proceedin gs of IEEE Inte rnational S olid-state C ircuits Con-ference, 1984, pp. 1 6 1 74 RADHA KRISHNAN , D., WHITAK ER, S.R., and MA KI, G.K.:Formal design procedures for pass transistor switching circuits,IEEE J., 1985,SC-U), pp. 531-5365 PED RO N, C., and STAU FFER, A.: Analysis and synthe sis of com-binational pass transistor circuits, IEEE Trans. , 1988, 7 , (7). pp.775-7866 PETERSON , G.E., and MAKI, G.K.: Binary tree structured logiccircuits: design and fa ult detection. Proceedin gs of Inte rnationalConference on Computer Design, Port Chester, NY, USA, Oct.1984, pp . 6714767 FEIZI, A.. and RA DHA KRIS HNA N, D.: Multiple output passnetwork s: design and testing. Proceedin gs of IEEE Internatio nalTest Co nference, Nov. 1985, pp. 907-9118 JACKSHA, I., RADHA KRISHNA N, D., and M AKI, G.K.:Reverse testing of NMOS binary tree structured networks. Pro-ceedings of 21st Annual Asilomar Conference on Signals, Systemsand Com puters, Nov. 1987, pp. 52S-5309 WESTE , N., and ESHR AGH IAN, K.: Principles of CMO S VLSIdesign (Addison-Wesley, Massach usetts, USA, 1985)10 CHU, K.M., and PULFREY, D.1.: Design procedures for differen-tial cascode voltage switch circuits, IEEE J., 1986, SC-21, pp. 1082-1087

Biographical detailsDamu Rndhakrishono received the BScdegree in Elec t ronics and Commu nica t ionEngineer ing f rom the Univers i ty ofKera la , India in 1968 a n d t h e M T e c h a n dPh D degrees f rom the Indian Ins t i tu te ofTechnology, Kanpur , India and the Uni-versity of Idaho, Moscow, Idaho, USA,both in Electrical Engineering, in 1975a n d 1983, respectively.F r o m 1983 t o 1985 h e w a s a n A s s i s t an tProfessor in the Department of ElectricalEngineering, Old Dominion University, Norfolk, Virginia. Since1985 he has been with the Department of Electrical Engineer-ing, Univers i ty of Idaho, Moscow, Idaho . At present he is th eVice Pres ident of the NETECH Corpora t ion, New York. H iscur rent r e sea rch in te res ts inc lude VLSI des ign, f aul t to le rantdigital systems, computer architecture and switching theory.

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Design of CMOS